diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests')
116 files changed, 70243 insertions, 69521 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 96524a9ce..3b6b51422 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887168 # Number of seconds simulated -sim_ticks 1887168480000 # Number of ticks simulated -final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906037 # Number of seconds simulated +sim_ticks 1906037467000 # Number of ticks simulated +final_tick 1906037467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181674 # Simulator instruction rate (inst/s) -host_op_rate 181674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6108559174 # Simulator tick rate (ticks/s) -host_mem_usage 367844 # Number of bytes of host memory used -host_seconds 308.94 # Real time elapsed on the host -sim_insts 56125948 # Number of instructions simulated -sim_ops 56125948 # Number of ops (including micro ops) simulated +host_inst_rate 252781 # Simulator instruction rate (inst/s) +host_op_rate 252781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8583432112 # Simulator tick rate (ticks/s) +host_mem_usage 376892 # Number of bytes of host memory used +host_seconds 222.06 # Real time elapsed on the host +sim_insts 56132533 # Number of instructions simulated +sim_ops 56132533 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1050496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory -system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25909440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1050496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1050496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404702 # Number of read requests accepted -system.physmem.writeReqs 118023 # Number of write requests accepted -system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118142 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118142 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 551141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13041708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13593353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 551141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 551141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3966915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3966915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3966915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 551141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13041708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17560268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404835 # Number of read requests accepted +system.physmem.writeReqs 118142 # Number of write requests accepted +system.physmem.readBursts 404835 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118142 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25902720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 7559680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25909440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7561088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25482 # Per bank write bursts -system.physmem.perBankRdBursts::1 25721 # Per bank write bursts -system.physmem.perBankRdBursts::2 25818 # Per bank write bursts -system.physmem.perBankRdBursts::3 25768 # Per bank write bursts -system.physmem.perBankRdBursts::4 25084 # Per bank write bursts -system.physmem.perBankRdBursts::5 25019 # Per bank write bursts -system.physmem.perBankRdBursts::6 24651 # Per bank write bursts -system.physmem.perBankRdBursts::7 24525 # Per bank write bursts -system.physmem.perBankRdBursts::8 25293 # Per bank write bursts -system.physmem.perBankRdBursts::9 25189 # Per bank write bursts -system.physmem.perBankRdBursts::10 25397 # Per bank write bursts -system.physmem.perBankRdBursts::11 24988 # Per bank write bursts -system.physmem.perBankRdBursts::12 24521 # Per bank write bursts -system.physmem.perBankRdBursts::13 25565 # Per bank write bursts -system.physmem.perBankRdBursts::14 25830 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41709 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25494 # Per bank write bursts +system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::2 25829 # Per bank write bursts +system.physmem.perBankRdBursts::3 25773 # Per bank write bursts +system.physmem.perBankRdBursts::4 25090 # Per bank write bursts +system.physmem.perBankRdBursts::5 25012 # Per bank write bursts +system.physmem.perBankRdBursts::6 24715 # Per bank write bursts +system.physmem.perBankRdBursts::7 24579 # Per bank write bursts +system.physmem.perBankRdBursts::8 25194 # Per bank write bursts +system.physmem.perBankRdBursts::9 25292 # Per bank write bursts +system.physmem.perBankRdBursts::10 25390 # Per bank write bursts +system.physmem.perBankRdBursts::11 24989 # Per bank write bursts +system.physmem.perBankRdBursts::12 24533 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25835 # Per bank write bursts system.physmem.perBankRdBursts::15 25740 # Per bank write bursts -system.physmem.perBankWrBursts::0 7815 # Per bank write bursts -system.physmem.perBankWrBursts::1 7682 # Per bank write bursts -system.physmem.perBankWrBursts::2 8062 # Per bank write bursts -system.physmem.perBankWrBursts::3 7737 # Per bank write bursts -system.physmem.perBankWrBursts::4 7196 # Per bank write bursts -system.physmem.perBankWrBursts::5 7012 # Per bank write bursts -system.physmem.perBankWrBursts::6 6647 # Per bank write bursts -system.physmem.perBankWrBursts::7 6398 # Per bank write bursts -system.physmem.perBankWrBursts::8 7404 # Per bank write bursts -system.physmem.perBankWrBursts::9 6806 # Per bank write bursts -system.physmem.perBankWrBursts::10 7277 # Per bank write bursts -system.physmem.perBankWrBursts::11 6969 # Per bank write bursts -system.physmem.perBankWrBursts::12 7052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::0 7824 # Per bank write bursts +system.physmem.perBankWrBursts::1 7665 # Per bank write bursts +system.physmem.perBankWrBursts::2 8071 # Per bank write bursts +system.physmem.perBankWrBursts::3 7733 # Per bank write bursts +system.physmem.perBankWrBursts::4 7203 # Per bank write bursts +system.physmem.perBankWrBursts::5 7017 # Per bank write bursts +system.physmem.perBankWrBursts::6 6707 # Per bank write bursts +system.physmem.perBankWrBursts::7 6431 # Per bank write bursts +system.physmem.perBankWrBursts::8 7312 # Per bank write bursts +system.physmem.perBankWrBursts::9 6902 # Per bank write bursts +system.physmem.perBankWrBursts::10 7273 # Per bank write bursts +system.physmem.perBankWrBursts::11 6973 # Per bank write bursts +system.physmem.perBankWrBursts::12 7066 # Per bank write bursts +system.physmem.perBankWrBursts::13 8009 # Per bank write bursts +system.physmem.perBankWrBursts::14 7985 # Per bank write bursts system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 29 # Number of times write queue was full causing retry -system.physmem.totGap 1887159671500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 1906028705500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404702 # Read request sizes (log2) +system.physmem.readPktSize::6 404835 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118023 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118142 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 64 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,187 +148,196 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.304127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.318074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.802576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14872 23.08% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11053 17.15% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5024 7.80% 48.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3269 5.07% 53.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2580 4.00% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1937 3.01% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4194 6.51% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1317 2.04% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20191 31.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64437 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.190700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2898.366893 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5309 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads -system.physmem.totQLat 2194493000 # Total ticks spent queuing -system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5312 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.236446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.912972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.909399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4665 87.82% 87.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.36% 88.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18 0.34% 88.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 199 3.75% 92.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.09% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.47% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 40 0.75% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.11% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.43% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.08% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.17% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.38% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.45% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 32 0.60% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 171 3.22% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.08% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 8 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5312 # Writes before turning the bus around for reads +system.physmem.totQLat 2653633250 # Total ticks spent queuing +system.physmem.totMemAccLat 10242320750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6556.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25306.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing -system.physmem.readRowHits 363582 # Number of row buffer hits during reads -system.physmem.writeRowHits 95445 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes -system.physmem.avgGap 3610234.20 # Average gap between requests -system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.470116 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states -system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states +system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing +system.physmem.readRowHits 362859 # Number of row buffer hits during reads +system.physmem.writeRowHits 95554 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes +system.physmem.avgGap 3644574.63 # Average gap between requests +system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238049280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129888000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577136600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380058480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67941192465 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084023651750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278782921775 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.912502 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803110214250 # Time in different power states +system.physmem_0.memoryStateTime::REF 63646700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39278414500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.547722 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states -system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states +system.physmem_1.actEnergy 249094440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135914625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579757400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385359120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68603580630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083442617750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278889269165 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.968292 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802146960250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63646700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40241682250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14997890 # Number of BP lookups -system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits +system.cpu.branchPred.lookups 15005157 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016352 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370563 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9544476 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5200630 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.488376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807259 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30802 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241004 # DTB read hits -system.cpu.dtb.read_misses 17472 # DTB read misses +system.cpu.dtb.read_hits 9242284 # DTB read hits +system.cpu.dtb.read_misses 17197 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766036 # DTB read accesses -system.cpu.dtb.write_hits 6386411 # DTB write hits -system.cpu.dtb.write_misses 2301 # DTB write misses +system.cpu.dtb.read_accesses 765766 # DTB read accesses +system.cpu.dtb.write_hits 6387071 # DTB write hits +system.cpu.dtb.write_misses 2294 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298419 # DTB write accesses -system.cpu.dtb.data_hits 15627415 # DTB hits -system.cpu.dtb.data_misses 19773 # DTB misses +system.cpu.dtb.write_accesses 298411 # DTB write accesses +system.cpu.dtb.data_hits 15629355 # DTB hits +system.cpu.dtb.data_misses 19491 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064455 # DTB accesses -system.cpu.itb.fetch_hits 4013195 # ITB hits -system.cpu.itb.fetch_misses 6857 # ITB misses -system.cpu.itb.fetch_acv 677 # ITB acv -system.cpu.itb.fetch_accesses 4020052 # ITB accesses +system.cpu.dtb.data_accesses 1064177 # DTB accesses +system.cpu.itb.fetch_hits 4015320 # ITB hits +system.cpu.itb.fetch_misses 6841 # ITB misses +system.cpu.itb.fetch_acv 659 # ITB acv +system.cpu.itb.fetch_accesses 4022161 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,39 +350,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 182043546 # number of cpu cycles simulated +system.cpu.numCycles 223168437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125948 # Number of instructions committed -system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.243483 # CPI: cycles per instruction -system.cpu.ipc 0.308311 # IPC: instructions per cycle +system.cpu.committedInsts 56132533 # Number of instructions committed +system.cpu.committedOps 56132533 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2504504 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5489 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590815720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.975741 # CPI: cycles per instruction +system.cpu.ipc 0.251525 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211546 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74811 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105910 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182756 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73444 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73444 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148923 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837436986000 96.40% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 81017000 0.00% 96.41% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 682412000 0.04% 96.44% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67836062500 3.56% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906036477500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981727 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693457 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814873 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -409,115 +418,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175591 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5129 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192398 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192481 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.325047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395484 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393243 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38636753000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4528404000 0.24% 2.26% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862871310500 97.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.tickCycles 86394668 # Number of cycles that the object actually ticked +system.cpu.idleCycles 136773769 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395457 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.977331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13772866 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395969 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866169 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 121717500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.977331 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits -system.cpu.dcache.overall_hits::total 13389812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses -system.cpu.dcache.overall_misses::total 1776395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63663599 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63663599 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575814 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182834 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182834 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199026 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199026 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13390973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13390973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13390973 # number of overall hits +system.cpu.dcache.overall_hits::total 13390973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575091 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575091 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17213 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17213 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776861 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776861 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776861 # number of overall misses +system.cpu.dcache.overall_misses::total 1776861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46961675000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46961675000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33993891500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33993891500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 235176000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 235176000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80955566500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80955566500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80955566500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80955566500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150905 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150905 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200047 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200047 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199026 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199026 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167834 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167834 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167834 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167834 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093497 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45561.001395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45561.001395 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,129 +535,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks -system.cpu.dcache.writebacks::total 838310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127379 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125070.657444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131083.368870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125070.657444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,126 +809,132 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76511 # number of writebacks -system.cpu.l2cache.writebacks::total 76511 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76630 # number of writebacks +system.cpu.l2cache.writebacks::total 76630 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # 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number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # 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number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1214500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1214500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13695042500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13695042500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1987583500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1987583500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30951837500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30951837500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1987583500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44646880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46634463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1987583500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44646880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46634463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364010000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364010000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931836500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931836500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3295846500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3295846500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383239 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383239 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011240 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249344 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249344 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141874 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141874 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5711775 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2855459 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277896 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304379 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304379 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1460498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091781 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422854 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4380147 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219373 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8599520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93467712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143047028 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236514740 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422969 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6151080 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000871 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029504 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6145721 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5359 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6151080 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3707269500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 284383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2190955582 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105716998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -935,9 +950,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51172 # Transaction distribution -system.iobus.trans_dist::WriteResp 51172 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51174 # Transaction distribution +system.iobus.trans_dist::WriteResp 51174 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5100 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -949,11 +964,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33104 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116554 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20400 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -965,11 +980,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44340 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705948 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4711000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -991,23 +1006,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215087245 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23482000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290787 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748608829000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290787 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080674 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080674 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1021,14 +1036,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21943883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21943883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427163362 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427163362 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21943883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21943883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21943883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21943883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1045,19 +1060,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126843.254335 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126843.254335 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126843.254335 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1071,14 +1086,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13293883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13293883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3349563362 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3349563362 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13293883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13293883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13293883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13293883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1087,63 +1102,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295659 # Transaction distribution -system.membus.trans_dist::WriteReq 9620 # Transaction distribution -system.membus.trans_dist::WriteResp 9620 # Transaction distribution -system.membus.trans_dist::Writeback 118023 # Transaction distribution -system.membus.trans_dist::CleanEvict 262178 # Transaction distribution -system.membus.trans_dist::UpgradeReq 157 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157 # Transaction distribution -system.membus.trans_dist::ReadExReq 116404 # Transaction distribution -system.membus.trans_dist::ReadExResp 116404 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution +system.membus.trans_dist::ReadResp 295688 # Transaction distribution +system.membus.trans_dist::WriteReq 9622 # Transaction distribution +system.membus.trans_dist::WriteResp 9622 # Transaction distribution +system.membus.trans_dist::Writeback 118142 # Transaction distribution +system.membus.trans_dist::CleanEvict 262192 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116508 # Transaction distribution +system.membus.trans_dist::ReadExResp 116508 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288774 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1149038 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1182174 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306991 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44340 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30812800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30857140 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33514868 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843798 # Request fanout histogram +system.membus.snoop_fanout::samples 844052 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 844052 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843798 # Request fanout histogram -system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 844052 # Request fanout histogram +system.membus.reqLayer0.occupancy 29776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319401645 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160603841 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69882415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7571a76a8..c3ff68c1f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906957 # Number of seconds simulated -sim_ticks 1906956794000 # Number of ticks simulated -final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.921764 # Number of seconds simulated +sim_ticks 1921763645000 # Number of ticks simulated +final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101212 # Simulator instruction rate (inst/s) -host_op_rate 101212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3411514986 # Simulator tick rate (ticks/s) -host_mem_usage 375140 # Number of bytes of host memory used -host_seconds 558.98 # Real time elapsed on the host -sim_insts 56575230 # Number of instructions simulated -sim_ops 56575230 # Number of ops (including micro ops) simulated +host_inst_rate 133766 # Simulator instruction rate (inst/s) +host_op_rate 133766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4532754153 # Simulator tick rate (ticks/s) +host_mem_usage 384052 # Number of bytes of host memory used +host_seconds 423.97 # Real time elapsed on the host +sim_insts 56713315 # Number of instructions simulated +sim_ops 56713315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410454 # Number of read requests accepted -system.physmem.writeReqs 122837 # Number of write requests accepted -system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410427 # Number of read requests accepted +system.physmem.writeReqs 123049 # Number of write requests accepted +system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26161 # Per bank write bursts -system.physmem.perBankRdBursts::1 25973 # Per bank write bursts -system.physmem.perBankRdBursts::2 26108 # Per bank write bursts -system.physmem.perBankRdBursts::3 25765 # Per bank write bursts -system.physmem.perBankRdBursts::4 25066 # Per bank write bursts -system.physmem.perBankRdBursts::5 25574 # Per bank write bursts -system.physmem.perBankRdBursts::6 25905 # Per bank write bursts -system.physmem.perBankRdBursts::7 25241 # Per bank write bursts -system.physmem.perBankRdBursts::8 25825 # Per bank write bursts -system.physmem.perBankRdBursts::9 26325 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25205 # Per bank write bursts -system.physmem.perBankRdBursts::12 25472 # Per bank write bursts -system.physmem.perBankRdBursts::13 25390 # Per bank write bursts -system.physmem.perBankRdBursts::14 25632 # Per bank write bursts -system.physmem.perBankRdBursts::15 25396 # Per bank write bursts -system.physmem.perBankWrBursts::0 8442 # Per bank write bursts -system.physmem.perBankWrBursts::1 7958 # Per bank write bursts -system.physmem.perBankWrBursts::2 8052 # Per bank write bursts -system.physmem.perBankWrBursts::3 7723 # Per bank write bursts -system.physmem.perBankWrBursts::4 7027 # Per bank write bursts -system.physmem.perBankWrBursts::5 7199 # Per bank write bursts -system.physmem.perBankWrBursts::6 7428 # Per bank write bursts -system.physmem.perBankWrBursts::7 6815 # Per bank write bursts -system.physmem.perBankWrBursts::8 7536 # Per bank write bursts -system.physmem.perBankWrBursts::9 7897 # Per bank write bursts -system.physmem.perBankWrBursts::10 7294 # Per bank write bursts -system.physmem.perBankWrBursts::11 7366 # Per bank write bursts -system.physmem.perBankWrBursts::12 7733 # Per bank write bursts -system.physmem.perBankWrBursts::13 8096 # Per bank write bursts -system.physmem.perBankWrBursts::14 8387 # Per bank write bursts -system.physmem.perBankWrBursts::15 7862 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25500 # Per bank write bursts +system.physmem.perBankRdBursts::1 25969 # Per bank write bursts +system.physmem.perBankRdBursts::2 26011 # Per bank write bursts +system.physmem.perBankRdBursts::3 25727 # Per bank write bursts +system.physmem.perBankRdBursts::4 25508 # Per bank write bursts +system.physmem.perBankRdBursts::5 25811 # Per bank write bursts +system.physmem.perBankRdBursts::6 25519 # Per bank write bursts +system.physmem.perBankRdBursts::7 25160 # Per bank write bursts +system.physmem.perBankRdBursts::8 25451 # Per bank write bursts +system.physmem.perBankRdBursts::9 25839 # Per bank write bursts +system.physmem.perBankRdBursts::10 25659 # Per bank write bursts +system.physmem.perBankRdBursts::11 25030 # Per bank write bursts +system.physmem.perBankRdBursts::12 26076 # Per bank write bursts +system.physmem.perBankRdBursts::13 25978 # Per bank write bursts +system.physmem.perBankRdBursts::14 25473 # Per bank write bursts +system.physmem.perBankRdBursts::15 25600 # Per bank write bursts +system.physmem.perBankWrBursts::0 8066 # Per bank write bursts +system.physmem.perBankWrBursts::1 8046 # Per bank write bursts +system.physmem.perBankWrBursts::2 8027 # Per bank write bursts +system.physmem.perBankWrBursts::3 7668 # Per bank write bursts +system.physmem.perBankWrBursts::4 7376 # Per bank write bursts +system.physmem.perBankWrBursts::5 7761 # Per bank write bursts +system.physmem.perBankWrBursts::6 7583 # Per bank write bursts +system.physmem.perBankWrBursts::7 6991 # Per bank write bursts +system.physmem.perBankWrBursts::8 7326 # Per bank write bursts +system.physmem.perBankWrBursts::9 7600 # Per bank write bursts +system.physmem.perBankWrBursts::10 7532 # Per bank write bursts +system.physmem.perBankWrBursts::11 7413 # Per bank write bursts +system.physmem.perBankWrBursts::12 7962 # Per bank write bursts +system.physmem.perBankWrBursts::13 8267 # Per bank write bursts +system.physmem.perBankWrBursts::14 7722 # Per bank write bursts +system.physmem.perBankWrBursts::15 7694 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1906952476500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1921759329500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410454 # Read request sizes (log2) +system.physmem.readPktSize::6 410427 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122837 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads -system.physmem.totQLat 4043689250 # Total ticks spent queuing -system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads +system.physmem.totQLat 4465229000 # Total ticks spent queuing +system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 369741 # Number of row buffer hits during reads -system.physmem.writeRowHits 98545 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes -system.physmem.avgGap 3575819.72 # Average gap between requests -system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.251160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing +system.physmem.readRowHits 369445 # Number of row buffer hits during reads +system.physmem.writeRowHits 98595 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes +system.physmem.avgGap 3602335.12 # Average gap between requests +system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.590642 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.278071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.579840 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16421216 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits +system.cpu0.branchPred.lookups 16172722 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9282981 # DTB read hits -system.cpu0.dtb.read_misses 32197 # DTB read misses -system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 681404 # DTB read accesses -system.cpu0.dtb.write_hits 5956980 # DTB write hits -system.cpu0.dtb.write_misses 7300 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 235779 # DTB write accesses -system.cpu0.dtb.data_hits 15239961 # DTB hits -system.cpu0.dtb.data_misses 39497 # DTB misses -system.cpu0.dtb.data_acv 931 # DTB access violations -system.cpu0.dtb.data_accesses 917183 # DTB accesses -system.cpu0.itb.fetch_hits 1451467 # ITB hits -system.cpu0.itb.fetch_misses 20802 # ITB misses -system.cpu0.itb.fetch_acv 603 # ITB acv -system.cpu0.itb.fetch_accesses 1472269 # ITB accesses +system.cpu0.dtb.read_hits 9178933 # DTB read hits +system.cpu0.dtb.read_misses 32423 # DTB read misses +system.cpu0.dtb.read_acv 530 # DTB read access violations +system.cpu0.dtb.read_accesses 683199 # DTB read accesses +system.cpu0.dtb.write_hits 5878949 # DTB write hits +system.cpu0.dtb.write_misses 7260 # DTB write misses +system.cpu0.dtb.write_acv 384 # DTB write access violations +system.cpu0.dtb.write_accesses 235377 # DTB write accesses +system.cpu0.dtb.data_hits 15057882 # DTB hits +system.cpu0.dtb.data_misses 39683 # DTB misses +system.cpu0.dtb.data_acv 914 # DTB access violations +system.cpu0.dtb.data_accesses 918576 # DTB accesses +system.cpu0.itb.fetch_hits 1433805 # ITB hits +system.cpu0.itb.fetch_misses 20098 # ITB misses +system.cpu0.itb.fetch_acv 602 # ITB acv +system.cpu0.itb.fetch_accesses 1453903 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,598 +363,599 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115722397 # number of cpu cycles simulated +system.cpu0.numCycles 146988157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued -system.cpu0.iq.rate 0.455897 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued +system.cpu0.iq.rate 0.355242 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3417639 # number of nop insts executed -system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8298030 # Number of branches executed -system.cpu0.iew.exec_stores 5978029 # Number of stores executed -system.cpu0.iew.exec_rate 0.451498 # Inst execution rate -system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26562977 # num instructions producing a value -system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value +system.cpu0.iew.exec_nop 3376381 # number of nop insts executed +system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8213447 # Number of branches executed +system.cpu0.iew.exec_stores 5899836 # Number of stores executed +system.cpu0.iew.exec_rate 0.351823 # Inst execution rate +system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26321891 # num instructions producing a value +system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51918164 # Number of instructions committed -system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51342045 # Number of instructions committed +system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14033539 # Number of memory references committed -system.cpu0.commit.loads 8292663 # Number of loads committed -system.cpu0.commit.membars 202804 # Number of memory barriers committed -system.cpu0.commit.branches 7846921 # Number of branches committed -system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666824 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13846709 # Number of memory references committed +system.cpu0.commit.loads 8192690 # Number of loads committed +system.cpu0.commit.membars 198882 # Number of memory barriers committed +system.cpu0.commit.branches 7762297 # Number of branches committed +system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions. +system.cpu0.commit.function_calls 657143 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166079481 # The number of ROB reads -system.cpu0.rob.rob_writes 118719518 # The number of ROB writes -system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48933669 # Number of Instructions Simulated -system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads -system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes -system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads -system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads -system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1296864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 195675599 # The number of ROB reads +system.cpu0.rob.rob_writes 117488366 # The number of ROB writes +system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48394452 # Number of Instructions Simulated +system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads +system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads +system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1282830 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits -system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses -system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits +system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses +system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks -system.cpu0.dcache.writebacks::total 766891 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks +system.cpu0.dcache.writebacks::total 756224 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 927295 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits -system.cpu0.icache.overall_hits::total 7224199 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses -system.cpu0.icache.overall_misses::total 974618 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 909478 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits +system.cpu0.icache.overall_hits::total 7170024 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses +system.cpu0.icache.overall_misses::total 955631 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3314305 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits +system.cpu1.branchPred.lookups 3566695 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755656 # DTB read hits -system.cpu1.dtb.read_misses 9508 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 286377 # DTB read accesses -system.cpu1.dtb.write_hits 1073642 # DTB write hits -system.cpu1.dtb.write_misses 1995 # DTB write misses -system.cpu1.dtb.write_acv 40 # DTB write access violations -system.cpu1.dtb.write_accesses 108795 # DTB write accesses -system.cpu1.dtb.data_hits 2829298 # DTB hits -system.cpu1.dtb.data_misses 11503 # DTB misses -system.cpu1.dtb.data_acv 45 # DTB access violations -system.cpu1.dtb.data_accesses 395172 # DTB accesses -system.cpu1.itb.fetch_hits 497795 # ITB hits -system.cpu1.itb.fetch_misses 4809 # ITB misses -system.cpu1.itb.fetch_acv 84 # ITB acv -system.cpu1.itb.fetch_accesses 502604 # ITB accesses +system.cpu1.dtb.read_hits 1880373 # DTB read hits +system.cpu1.dtb.read_misses 9576 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 286028 # DTB read accesses +system.cpu1.dtb.write_hits 1172828 # DTB write hits +system.cpu1.dtb.write_misses 2034 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 108538 # DTB write accesses +system.cpu1.dtb.data_hits 3053201 # DTB hits +system.cpu1.dtb.data_misses 11610 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 394566 # DTB accesses +system.cpu1.itb.fetch_hits 516269 # ITB hits +system.cpu1.itb.fetch_misses 4737 # ITB misses +system.cpu1.itb.fetch_acv 64 # ITB acv +system.cpu1.itb.fetch_accesses 521006 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -955,563 +968,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13378620 # number of cpu cycles simulated +system.cpu1.numCycles 14959639 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued -system.cpu1.iq.rate 0.628992 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued +system.cpu1.iq.rate 0.609112 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 464508 # number of nop insts executed -system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1230259 # Number of branches executed -system.cpu1.iew.exec_stores 1080816 # Number of stores executed -system.cpu1.iew.exec_rate 0.621067 # Inst execution rate -system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3916216 # num instructions producing a value -system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value +system.cpu1.iew.exec_nop 516366 # number of nop insts executed +system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1335580 # Number of branches executed +system.cpu1.iew.exec_stores 1180544 # Number of stores executed +system.cpu1.iew.exec_rate 0.601481 # Inst execution rate +system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4235192 # num instructions producing a value +system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8020551 # Number of instructions committed -system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8743092 # Number of instructions committed +system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2563717 # Number of memory references committed -system.cpu1.commit.loads 1543225 # Number of loads committed -system.cpu1.commit.membars 37500 # Number of memory barriers committed -system.cpu1.commit.branches 1142801 # Number of branches committed -system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions. -system.cpu1.commit.function_calls 128494 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2784903 # Number of memory references committed +system.cpu1.commit.loads 1665249 # Number of loads committed +system.cpu1.commit.membars 42287 # Number of memory barriers committed +system.cpu1.commit.branches 1247450 # Number of branches committed +system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139604 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction -system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 21604416 # The number of ROB reads -system.cpu1.rob.rob_writes 19248787 # The number of ROB writes -system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7641561 # Number of Instructions Simulated -system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads -system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes -system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes -system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads -system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 88757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits -system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses -system.cpu1.dcache.overall_misses::total 341978 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 23719092 # The number of ROB reads +system.cpu1.rob.rob_writes 20805392 # The number of ROB writes +system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8318863 # Number of Instructions Simulated +system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads +system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes +system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads +system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 98586 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits +system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses +system.cpu1.dcache.overall_misses::total 379686 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks -system.cpu1.dcache.writebacks::total 56462 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks +system.cpu1.dcache.writebacks::total 63787 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 200477 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits -system.cpu1.icache.overall_hits::total 1230816 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses -system.cpu1.icache.overall_misses::total 208101 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 222828 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits +system.cpu1.icache.overall_hits::total 1300089 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses +system.cpu1.icache.overall_misses::total 230461 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1527,10 +1541,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7371 # Transaction distribution system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54460 # Transaction distribution -system.iobus.trans_dist::WriteResp 54460 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54607 # Transaction distribution +system.iobus.trans_dist::WriteResp 54607 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1541,12 +1555,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1557,13 +1571,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1583,52 +1597,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1637,40 +1651,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13318883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13318883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829721346 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829721346 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13318883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13318883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13318883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13318883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350397858 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13449883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13449883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13449883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13449883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1679,195 +1693,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74825.185393 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.725501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.725501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 344930 # number of replacements -system.l2c.tags.tagsinuse 65239.787598 # Cycle average of tags in use -system.l2c.tags.total_refs 3999339 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410104 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.752012 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7535462000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53414.062989 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5366.108277 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6187.949092 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 208.288223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 63.379017 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.815034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081880 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.094421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000967 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995480 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2299 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5773 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50615 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38456225 # Number of tag accesses -system.l2c.tags.data_accesses 38456225 # Number of data accesses -system.l2c.Writeback_hits::writebacks 823353 # number of Writeback hits -system.l2c.Writeback_hits::total 823353 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 230 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 400 # number of UpgradeReq hits +system.l2c.tags.replacements 344948 # number of replacements +system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use +system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38374495 # Number of tag accesses +system.l2c.tags.data_accesses 38374495 # Number of data accesses +system.l2c.Writeback_hits::writebacks 820011 # number of Writeback hits +system.l2c.Writeback_hits::total 820011 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 159888 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19633 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179521 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 914307 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 199175 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1113482 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 746483 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 59707 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 806190 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 914307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 906371 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 199175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 79340 # number of demand (read+write) hits -system.l2c.demand_hits::total 2099193 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 914307 # number of overall hits -system.l2c.overall_hits::cpu0.data 906371 # number of overall hits -system.l2c.overall_hits::cpu1.inst 199175 # number of overall hits -system.l2c.overall_hits::cpu1.data 79340 # number of overall hits -system.l2c.overall_hits::total 2099193 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2738 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1002 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3740 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 352 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 366 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 718 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114723 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7302 # 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number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1122774000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 155099500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1277873500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 19926572000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 76887500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20003459500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1122774000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 30101005000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 155099500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 879940500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 32258819000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1122774000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 30101005000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 155099500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 879940500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 32258819000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 823353 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 823353 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1232 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4140 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 401 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 392 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 793 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 274611 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 26935 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301546 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 927784 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 201024 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1128808 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1019471 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 60548 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1080019 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 927784 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7193 # Transaction distribution -system.membus.trans_dist::ReadResp 296434 # Transaction distribution -system.membus.trans_dist::WriteReq 12908 # Transaction distribution -system.membus.trans_dist::WriteResp 12908 # Transaction distribution -system.membus.trans_dist::Writeback 122837 # Transaction distribution -system.membus.trans_dist::CleanEvict 263082 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution -system.membus.trans_dist::ReadExReq 122000 # Transaction distribution -system.membus.trans_dist::ReadExResp 121659 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution +system.membus.trans_dist::ReadReq 7195 # Transaction distribution +system.membus.trans_dist::ReadResp 296388 # Transaction distribution +system.membus.trans_dist::WriteReq 13055 # Transaction distribution +system.membus.trans_dist::WriteResp 13055 # Transaction distribution +system.membus.trans_dist::Writeback 123049 # Transaction distribution +system.membus.trans_dist::CleanEvict 262884 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution +system.membus.trans_dist::ReadExReq 122086 # Transaction distribution +system.membus.trans_dist::ReadExResp 121678 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution +system.membus.trans_dist::BadAddressError 75 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10191 # Total snoops (count) -system.membus.snoop_fanout::samples 873294 # Request fanout histogram +system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11781 # Total snoops (count) +system.membus.snoop_fanout::samples 875308 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 873294 # Request fanout histogram -system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875308 # Request fanout histogram +system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 458492 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462162 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2152,161 +2172,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed +system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 172559 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches +system.cpu0.kern.callpal::total 169199 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1342 -system.cpu0.kern.mode_good::user 1343 +system.cpu0.kern.mode_good::kernel 1346 +system.cpu0.kern.mode_good::user 1347 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3604 # number of times the context was actually changed +system.cpu0.kern.swap_context 3534 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed -system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed -system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed +system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed +system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 45176 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches -system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 568 -system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 173 -system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48843 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 600 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 208 +system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 912 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1057 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 275b5ad07..3a598fe00 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860990 # Number of seconds simulated -sim_ticks 1860990273000 # Number of ticks simulated -final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875745 # Number of seconds simulated +sim_ticks 1875745192000 # Number of ticks simulated +final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102674 # Simulator instruction rate (inst/s) -host_op_rate 102674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3606509618 # Simulator tick rate (ticks/s) -host_mem_usage 370916 # Number of bytes of host memory used -host_seconds 516.01 # Real time elapsed on the host -sim_insts 52980740 # Number of instructions simulated -sim_ops 52980740 # Number of ops (including micro ops) simulated +host_inst_rate 131976 # Simulator instruction rate (inst/s) +host_op_rate 131976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4672432142 # Simulator tick rate (ticks/s) +host_mem_usage 378172 # Number of bytes of host memory used +host_seconds 401.45 # Real time elapsed on the host +sim_insts 52981683 # Number of instructions simulated +sim_ops 52981683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory +system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403829 # Number of read requests accepted -system.physmem.writeReqs 117554 # Number of write requests accepted -system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403822 # Number of read requests accepted +system.physmem.writeReqs 117557 # Number of write requests accepted +system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25640 # Per bank write bursts -system.physmem.perBankRdBursts::1 25420 # Per bank write bursts -system.physmem.perBankRdBursts::2 25567 # Per bank write bursts -system.physmem.perBankRdBursts::3 25490 # Per bank write bursts -system.physmem.perBankRdBursts::4 25392 # Per bank write bursts -system.physmem.perBankRdBursts::5 24736 # Per bank write bursts -system.physmem.perBankRdBursts::6 24946 # Per bank write bursts -system.physmem.perBankRdBursts::7 25069 # Per bank write bursts -system.physmem.perBankRdBursts::8 24934 # Per bank write bursts -system.physmem.perBankRdBursts::9 25024 # Per bank write bursts -system.physmem.perBankRdBursts::10 25571 # Per bank write bursts -system.physmem.perBankRdBursts::11 24874 # Per bank write bursts -system.physmem.perBankRdBursts::12 24488 # Per bank write bursts -system.physmem.perBankRdBursts::13 25240 # Per bank write bursts -system.physmem.perBankRdBursts::14 25741 # Per bank write bursts -system.physmem.perBankRdBursts::15 25582 # Per bank write bursts -system.physmem.perBankWrBursts::0 7942 # Per bank write bursts +system.physmem.perBankRdBursts::0 25633 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25565 # Per bank write bursts +system.physmem.perBankRdBursts::3 25492 # Per bank write bursts +system.physmem.perBankRdBursts::4 25387 # Per bank write bursts +system.physmem.perBankRdBursts::5 24737 # Per bank write bursts +system.physmem.perBankRdBursts::6 24937 # Per bank write bursts +system.physmem.perBankRdBursts::7 25080 # Per bank write bursts +system.physmem.perBankRdBursts::8 24933 # Per bank write bursts +system.physmem.perBankRdBursts::9 25019 # Per bank write bursts +system.physmem.perBankRdBursts::10 25561 # Per bank write bursts +system.physmem.perBankRdBursts::11 24878 # Per bank write bursts +system.physmem.perBankRdBursts::12 24487 # Per bank write bursts +system.physmem.perBankRdBursts::13 25242 # Per bank write bursts +system.physmem.perBankRdBursts::14 25745 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 7946 # Per bank write bursts system.physmem.perBankWrBursts::1 7515 # Per bank write bursts -system.physmem.perBankWrBursts::2 7958 # Per bank write bursts -system.physmem.perBankWrBursts::3 7515 # Per bank write bursts -system.physmem.perBankWrBursts::4 7335 # Per bank write bursts -system.physmem.perBankWrBursts::5 6671 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 6705 # Per bank write bursts -system.physmem.perBankWrBursts::8 7147 # Per bank write bursts -system.physmem.perBankWrBursts::9 6708 # Per bank write bursts -system.physmem.perBankWrBursts::10 7414 # Per bank write bursts -system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::2 7960 # Per bank write bursts +system.physmem.perBankWrBursts::3 7517 # Per bank write bursts +system.physmem.perBankWrBursts::4 7330 # Per bank write bursts +system.physmem.perBankWrBursts::5 6676 # Per bank write bursts +system.physmem.perBankWrBursts::6 6762 # Per bank write bursts +system.physmem.perBankWrBursts::7 6719 # Per bank write bursts +system.physmem.perBankWrBursts::8 7146 # Per bank write bursts +system.physmem.perBankWrBursts::9 6702 # Per bank write bursts +system.physmem.perBankWrBursts::10 7407 # Per bank write bursts +system.physmem.perBankWrBursts::11 6970 # Per bank write bursts system.physmem.perBankWrBursts::12 7148 # Per bank write bursts -system.physmem.perBankWrBursts::13 7857 # Per bank write bursts -system.physmem.perBankWrBursts::14 8057 # Per bank write bursts +system.physmem.perBankWrBursts::13 7861 # Per bank write bursts +system.physmem.perBankWrBursts::14 8061 # Per bank write bursts system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 22 # Number of times write queue was full causing retry -system.physmem.totGap 1860985018500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1875739913500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403829 # Read request sizes (log2) +system.physmem.readPktSize::6 403822 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117554 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117557 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,202 +148,197 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads -system.physmem.totQLat 3803541750 # Total ticks spent queuing -system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads +system.physmem.totQLat 4201414500 # Total ticks spent queuing +system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 364213 # Number of row buffer hits during reads -system.physmem.writeRowHits 95338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes -system.physmem.avgGap 3569324.31 # Average gap between requests -system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.266370 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states -system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states +system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing +system.physmem.readRowHits 363834 # Number of row buffer hits during reads +system.physmem.writeRowHits 95259 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes +system.physmem.avgGap 3597651.45 # Average gap between requests +system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.587193 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.250855 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states +system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.577609 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17952495 # Number of BP lookups -system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits +system.cpu.branchPred.lookups 17977610 # Number of BP lookups +system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10266725 # DTB read hits -system.cpu.dtb.read_misses 41420 # DTB read misses -system.cpu.dtb.read_acv 529 # DTB read access violations -system.cpu.dtb.read_accesses 965767 # DTB read accesses -system.cpu.dtb.write_hits 6642195 # DTB write hits -system.cpu.dtb.write_misses 9809 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 342270 # DTB write accesses -system.cpu.dtb.data_hits 16908920 # DTB hits -system.cpu.dtb.data_misses 51229 # DTB misses -system.cpu.dtb.data_acv 934 # DTB access violations -system.cpu.dtb.data_accesses 1308037 # DTB accesses -system.cpu.itb.fetch_hits 1768997 # ITB hits -system.cpu.itb.fetch_misses 27603 # ITB misses +system.cpu.dtb.read_hits 10250294 # DTB read hits +system.cpu.dtb.read_misses 41452 # DTB read misses +system.cpu.dtb.read_acv 531 # DTB read access violations +system.cpu.dtb.read_accesses 965916 # DTB read accesses +system.cpu.dtb.write_hits 6642949 # DTB write hits +system.cpu.dtb.write_misses 9723 # DTB write misses +system.cpu.dtb.write_acv 398 # DTB write access violations +system.cpu.dtb.write_accesses 342082 # DTB write accesses +system.cpu.dtb.data_hits 16893243 # DTB hits +system.cpu.dtb.data_misses 51175 # DTB misses +system.cpu.dtb.data_acv 929 # DTB access violations +system.cpu.dtb.data_accesses 1307998 # DTB accesses +system.cpu.itb.fetch_hits 1771116 # ITB hits +system.cpu.itb.fetch_misses 27251 # ITB misses system.cpu.itb.fetch_acv 655 # ITB acv -system.cpu.itb.fetch_accesses 1796600 # ITB accesses +system.cpu.itb.fetch_accesses 1798367 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -356,692 +351,692 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122250725 # number of cpu cycles simulated +system.cpu.numCycles 153807945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued +system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued -system.cpu.iq.rate 0.470318 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued +system.cpu.iq.rate 0.373800 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3688541 # number of nop insts executed -system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed -system.cpu.iew.exec_branches 8971597 # Number of branches executed -system.cpu.iew.exec_stores 6667115 # Number of stores executed -system.cpu.iew.exec_rate 0.465530 # Inst execution rate -system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28741573 # num instructions producing a value -system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value +system.cpu.iew.exec_nop 3690659 # number of nop insts executed +system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed +system.cpu.iew.exec_branches 8973802 # Number of branches executed +system.cpu.iew.exec_stores 6667771 # Number of stores executed +system.cpu.iew.exec_rate 0.369993 # Inst execution rate +system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28757989 # num instructions producing a value +system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back +system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56171345 # Number of instructions committed -system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172516 # Number of instructions committed +system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15469955 # Number of memory references committed -system.cpu.commit.loads 9092138 # Number of loads committed -system.cpu.commit.membars 226307 # Number of memory barriers committed -system.cpu.commit.branches 8441356 # Number of branches committed +system.cpu.commit.refs 15471333 # Number of memory references committed +system.cpu.commit.loads 9093055 # Number of loads committed +system.cpu.commit.membars 226352 # Number of memory barriers committed +system.cpu.commit.branches 8440752 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021098 # Number of committed integer instructions. -system.cpu.commit.function_calls 740502 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52021823 # Number of committed integer instructions. +system.cpu.commit.function_calls 740586 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # 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The number of ROB writes -system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52980740 # Number of Instructions Simulated -system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74560962 # number of integer regfile reads -system.cpu.int_regfile_writes 40515010 # number of integer regfile writes -system.cpu.fp_regfile_reads 167029 # number of floating regfile reads -system.cpu.fp_regfile_writes 167528 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads -system.cpu.misc_regfile_writes 939256 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1402429 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction +system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207703277 # The number of ROB reads +system.cpu.rob.rob_writes 129775597 # The number of ROB writes +system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981683 # Number of Instructions Simulated +system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads +system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74566924 # number of integer regfile reads +system.cpu.int_regfile_writes 40527176 # number of integer regfile writes +system.cpu.fp_regfile_reads 167101 # number of floating regfile reads +system.cpu.fp_regfile_writes 167535 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads +system.cpu.misc_regfile_writes 939467 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1402095 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7233922 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses -system.cpu.dcache.overall_misses::total 3759455 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247345 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247345 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247345 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247345 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841625 # 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average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 7904301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1039458 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.604252 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42289841500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 507.834309 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.991864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.991864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits -system.cpu.icache.overall_hits::total 7895322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses -system.cpu.icache.overall_misses::total 1092746 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7904302 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16294267486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55446 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39757210 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39757210 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 841276 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 841276 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 30 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 19 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 19 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422216 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422209 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1200,9 +1201,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51148 # Transaction distribution -system.iobus.trans_dist::WriteResp 51148 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1214,11 +1215,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1230,11 +1231,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1256,23 +1257,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1286,14 +1287,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1310,19 +1311,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1336,14 +1337,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1352,64 +1353,64 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295925 # Transaction distribution -system.membus.trans_dist::WriteReq 9596 # Transaction distribution -system.membus.trans_dist::WriteResp 9596 # Transaction distribution -system.membus.trans_dist::Writeback 117554 # Transaction distribution -system.membus.trans_dist::CleanEvict 261799 # Transaction distribution -system.membus.trans_dist::UpgradeReq 335 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadResp 295909 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 117557 # Transaction distribution +system.membus.trans_dist::CleanEvict 261789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 334 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution system.membus.trans_dist::UpgradeResp 341 # Transaction distribution -system.membus.trans_dist::ReadExReq 115266 # Transaction distribution -system.membus.trans_dist::ReadExResp 115266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution -system.membus.trans_dist::BadAddressError 82 # Transaction distribution +system.membus.trans_dist::ReadExReq 115275 # Transaction distribution +system.membus.trans_dist::ReadExResp 115275 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution +system.membus.trans_dist::BadAddressError 83 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842297 # Request fanout histogram +system.membus.snoop_fanout::samples 842283 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842297 # Request fanout histogram -system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842283 # Request fanout histogram +system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1443,28 +1444,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1503,29 +1504,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191916 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.callpal::total 191979 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 296ab434c..8f58e32e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841535 # Number of seconds simulated -sim_ticks 1841535479500 # Number of ticks simulated -final_tick 1841535479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841615 # Number of seconds simulated +sim_ticks 1841615117500 # Number of ticks simulated +final_tick 1841615117500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156573 # Simulator instruction rate (inst/s) -host_op_rate 156573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3970842510 # Simulator tick rate (ticks/s) -host_mem_usage 369896 # Number of bytes of host memory used -host_seconds 463.76 # Real time elapsed on the host -sim_insts 72613172 # Number of instructions simulated -sim_ops 72613172 # Number of ops (including micro ops) simulated +host_inst_rate 220643 # Simulator instruction rate (inst/s) +host_op_rate 220643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5550131764 # Simulator tick rate (ticks/s) +host_mem_usage 377148 # Number of bytes of host memory used +host_seconds 331.81 # Real time elapsed on the host +sim_insts 73212541 # Number of instructions simulated +sim_ops 73212541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 466112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20058112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2156288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 305728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2656832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 495296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20794752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1560960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 279936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513472 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 466112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 305728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7482432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7482432 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41513 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25786880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 495296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 279936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 916736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7468864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7468864 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 324918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39273 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402985 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116913 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 253111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10892058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1170919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 166018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1442726 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 268947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11291584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 847604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 152006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1364819 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14005182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 253111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 166018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4063148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4063148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4063148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 253111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10892058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1170919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 166018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1442726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14002318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 268947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 152006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 497789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4055605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4055605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4055605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 268947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11291584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 847604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 152006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1364819 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18068331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 82294 # Number of read requests accepted -system.physmem.writeReqs 47398 # Number of write requests accepted -system.physmem.readBursts 82294 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 47398 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5265472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3032512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5266816 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3033472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18057923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 70263 # Number of read requests accepted +system.physmem.writeReqs 43985 # Number of write requests accepted +system.physmem.readBursts 70263 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 43985 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4495872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue +system.physmem.bytesWritten 2813888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4496832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2815040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17325 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5126 # Per bank write bursts -system.physmem.perBankRdBursts::1 5048 # Per bank write bursts -system.physmem.perBankRdBursts::2 4814 # Per bank write bursts -system.physmem.perBankRdBursts::3 4971 # Per bank write bursts -system.physmem.perBankRdBursts::4 5248 # Per bank write bursts -system.physmem.perBankRdBursts::5 5169 # Per bank write bursts -system.physmem.perBankRdBursts::6 5184 # Per bank write bursts -system.physmem.perBankRdBursts::7 5149 # Per bank write bursts -system.physmem.perBankRdBursts::8 5417 # Per bank write bursts -system.physmem.perBankRdBursts::9 4756 # Per bank write bursts -system.physmem.perBankRdBursts::10 5535 # Per bank write bursts -system.physmem.perBankRdBursts::11 5117 # Per bank write bursts -system.physmem.perBankRdBursts::12 4885 # Per bank write bursts -system.physmem.perBankRdBursts::13 5047 # Per bank write bursts -system.physmem.perBankRdBursts::14 5632 # Per bank write bursts -system.physmem.perBankRdBursts::15 5175 # Per bank write bursts -system.physmem.perBankWrBursts::0 2819 # Per bank write bursts -system.physmem.perBankWrBursts::1 2870 # Per bank write bursts -system.physmem.perBankWrBursts::2 2836 # Per bank write bursts -system.physmem.perBankWrBursts::3 2977 # Per bank write bursts -system.physmem.perBankWrBursts::4 3104 # Per bank write bursts -system.physmem.perBankWrBursts::5 2797 # Per bank write bursts -system.physmem.perBankWrBursts::6 3160 # Per bank write bursts -system.physmem.perBankWrBursts::7 2831 # Per bank write bursts -system.physmem.perBankWrBursts::8 3459 # Per bank write bursts -system.physmem.perBankWrBursts::9 2567 # Per bank write bursts -system.physmem.perBankWrBursts::10 3319 # Per bank write bursts -system.physmem.perBankWrBursts::11 2907 # Per bank write bursts -system.physmem.perBankWrBursts::12 2644 # Per bank write bursts -system.physmem.perBankWrBursts::13 2801 # Per bank write bursts -system.physmem.perBankWrBursts::14 3392 # Per bank write bursts -system.physmem.perBankWrBursts::15 2900 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 17213 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4359 # Per bank write bursts +system.physmem.perBankRdBursts::1 4121 # Per bank write bursts +system.physmem.perBankRdBursts::2 4307 # Per bank write bursts +system.physmem.perBankRdBursts::3 4650 # Per bank write bursts +system.physmem.perBankRdBursts::4 3946 # Per bank write bursts +system.physmem.perBankRdBursts::5 4779 # Per bank write bursts +system.physmem.perBankRdBursts::6 4258 # Per bank write bursts +system.physmem.perBankRdBursts::7 4152 # Per bank write bursts +system.physmem.perBankRdBursts::8 4721 # Per bank write bursts +system.physmem.perBankRdBursts::9 4422 # Per bank write bursts +system.physmem.perBankRdBursts::10 4675 # Per bank write bursts +system.physmem.perBankRdBursts::11 4103 # Per bank write bursts +system.physmem.perBankRdBursts::12 4083 # Per bank write bursts +system.physmem.perBankRdBursts::13 4580 # Per bank write bursts +system.physmem.perBankRdBursts::14 4738 # Per bank write bursts +system.physmem.perBankRdBursts::15 4354 # Per bank write bursts +system.physmem.perBankWrBursts::0 2794 # Per bank write bursts +system.physmem.perBankWrBursts::1 2415 # Per bank write bursts +system.physmem.perBankWrBursts::2 2758 # Per bank write bursts +system.physmem.perBankWrBursts::3 3153 # Per bank write bursts +system.physmem.perBankWrBursts::4 2458 # Per bank write bursts +system.physmem.perBankWrBursts::5 2922 # Per bank write bursts +system.physmem.perBankWrBursts::6 2626 # Per bank write bursts +system.physmem.perBankWrBursts::7 2424 # Per bank write bursts +system.physmem.perBankWrBursts::8 3273 # Per bank write bursts +system.physmem.perBankWrBursts::9 2590 # Per bank write bursts +system.physmem.perBankWrBursts::10 2930 # Per bank write bursts +system.physmem.perBankWrBursts::11 2458 # Per bank write bursts +system.physmem.perBankWrBursts::12 2433 # Per bank write bursts +system.physmem.perBankWrBursts::13 2833 # Per bank write bursts +system.physmem.perBankWrBursts::14 3042 # Per bank write bursts +system.physmem.perBankWrBursts::15 2858 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1840523607000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1840603135000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 82294 # Read request sizes (log2) +system.physmem.readPktSize::6 70263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 47398 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 43985 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,202 +153,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.991001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.949703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.684450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7216 33.13% 33.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4887 22.44% 55.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1962 9.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1034 4.75% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 848 3.89% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 523 2.40% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 452 2.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 368 1.69% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4490 20.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21780 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.592397 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 979.363215 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2076 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1682 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.690812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.028180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 371.433574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7252 35.78% 35.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4628 22.84% 58.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1637 8.08% 66.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 935 4.61% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 704 3.47% 74.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 532 2.63% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 447 2.21% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 402 1.98% 81.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3729 18.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20266 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.186342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 837.829732 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1887 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2078 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.802214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.584158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.825875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 29 1.40% 1.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.29% 1.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.29% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1724 82.96% 84.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 1.88% 86.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 4.38% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 19 0.91% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.43% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 19 0.91% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.19% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.10% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.14% 93.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.05% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.14% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.14% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.19% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 8 0.38% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.19% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 76 3.66% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.29% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.14% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.05% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.10% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2078 # Writes before turning the bus around for reads -system.physmem.totQLat 922774500 # Total ticks spent queuing -system.physmem.totMemAccLat 2465393250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 411365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11216.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1889 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.275278 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.746797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.833114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.80% 1.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.48% 2.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.11% 2.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.11% 2.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1521 80.52% 83.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51 2.70% 85.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.48% 86.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 92 4.87% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.11% 91.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 5 0.26% 91.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.90% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.64% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.42% 93.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.11% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.16% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.11% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.21% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.53% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 16 0.85% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 73 3.86% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 6 0.32% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1889 # Writes before turning the bus around for reads +system.physmem.totQLat 866118250 # Total ticks spent queuing +system.physmem.totMemAccLat 2183268250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 351240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12329.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29966.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31079.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.09 # Average write queue length when enqueuing -system.physmem.readRowHits 70442 # Number of row buffer hits during reads -system.physmem.writeRowHits 37434 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.98 # Row buffer hit rate for writes -system.physmem.avgGap 14191496.83 # Average gap between requests -system.physmem.pageHitRate 83.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81065880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44121000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 317530200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 151593120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35745647625 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800947233750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926343167415 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.792687 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308857547000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.98 # Average write queue length when enqueuing +system.physmem.readRowHits 59265 # Number of row buffer hits during reads +system.physmem.writeRowHits 34684 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes +system.physmem.avgGap 16110593.93 # Average gap between requests +system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75993120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41365500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 269661600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 139644000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36119290320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 800836482750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 926543498730 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.762999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308404512000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45532240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9287627500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9805597500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 83590920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 45449250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324199200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 155448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35447161140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801537520500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926649345570 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.749891 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309278655250 # Time in different power states -system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem_1.actEnergy 77217840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41955375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 278272800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 145262160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35704397295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801349556250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926657723160 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.725709 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1308993682000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45532240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8857363000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9217388750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4774172 # DTB read hits -system.cpu0.dtb.read_misses 5959 # DTB read misses -system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 427834 # DTB read accesses -system.cpu0.dtb.write_hits 3388527 # DTB write hits -system.cpu0.dtb.write_misses 664 # DTB write misses -system.cpu0.dtb.write_acv 80 # DTB write access violations -system.cpu0.dtb.write_accesses 164366 # DTB write accesses -system.cpu0.dtb.data_hits 8162699 # DTB hits -system.cpu0.dtb.data_misses 6623 # DTB misses -system.cpu0.dtb.data_acv 189 # DTB access violations -system.cpu0.dtb.data_accesses 592200 # DTB accesses -system.cpu0.itb.fetch_hits 2715643 # ITB hits -system.cpu0.itb.fetch_misses 3015 # ITB misses -system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2718658 # ITB accesses +system.cpu0.dtb.read_hits 4860395 # DTB read hits +system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 428546 # DTB read accesses +system.cpu0.dtb.write_hits 3431856 # DTB write hits +system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.write_acv 84 # DTB write access violations +system.cpu0.dtb.write_accesses 164529 # DTB write accesses +system.cpu0.dtb.data_hits 8292251 # DTB hits +system.cpu0.dtb.data_misses 6847 # DTB misses +system.cpu0.dtb.data_acv 210 # DTB access violations +system.cpu0.dtb.data_accesses 593075 # DTB accesses +system.cpu0.itb.fetch_hits 2736971 # ITB hits +system.cpu0.itb.fetch_misses 3081 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2740052 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -361,87 +354,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928469977 # number of cpu cycles simulated +system.cpu0.numCycles 927057463 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30414467 # Number of instructions committed -system.cpu0.committedOps 30414467 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28351523 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162419 # Number of float alu accesses -system.cpu0.num_func_calls 792250 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3751370 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28351523 # number of integer instructions -system.cpu0.num_fp_insts 162419 # number of float instructions -system.cpu0.num_int_register_reads 39201854 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20853832 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84043 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85470 # number of times the floating registers were written -system.cpu0.num_mem_refs 8191763 # number of memory refs -system.cpu0.num_load_insts 4794790 # Number of load instructions -system.cpu0.num_store_insts 3396973 # Number of store instructions -system.cpu0.num_idle_cycles 905786099.867998 # Number of idle cycles -system.cpu0.num_busy_cycles 22683877.132002 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024431 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975569 # Percentage of idle cycles -system.cpu0.Branches 4797930 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1559380 5.13% 5.13% # Class of executed instruction -system.cpu0.op_class::IntAlu 19980835 65.68% 70.81% # Class of executed instruction -system.cpu0.op_class::IntMult 31353 0.10% 70.91% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.91% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12822 0.04% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 70.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::MemRead 4924664 16.19% 87.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 3400050 11.18% 98.32% # Class of executed instruction -system.cpu0.op_class::IprAccess 510577 1.68% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31701170 # Number of instructions committed +system.cpu0.committedOps 31701170 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29591762 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163845 # Number of float alu accesses +system.cpu0.num_func_calls 797475 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4044448 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29591762 # number of integer instructions +system.cpu0.num_fp_insts 163845 # number of float instructions +system.cpu0.num_int_register_reads 41150829 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21753171 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84843 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86199 # number of times the floating registers were written +system.cpu0.num_mem_refs 8322031 # number of memory refs +system.cpu0.num_load_insts 4881580 # Number of load instructions +system.cpu0.num_store_insts 3440451 # Number of store instructions +system.cpu0.num_idle_cycles 904905994.152015 # Number of idle cycles +system.cpu0.num_busy_cycles 22151468.847985 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023894 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976106 # Percentage of idle cycles +system.cpu0.Branches 5099323 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1600258 5.05% 5.05% # Class of executed instruction +system.cpu0.op_class::IntAlu 21086062 66.50% 71.55% # Class of executed instruction +system.cpu0.op_class::IntMult 31841 0.10% 71.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12946 0.04% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1618 0.01% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 5012305 15.81% 87.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 3443548 10.86% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 519649 1.64% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30421279 # Class of executed instruction +system.cpu0.op_class::total 31708227 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211362 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211399 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818807757000 98.77% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38797500 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357175000 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22331016000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841534745500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818498105000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39129500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 356633500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22720515500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841614383500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -480,7 +473,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -489,440 +482,442 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192209 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.callpal::total 192207 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29743380000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2567925500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809223438000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29940410000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2625898500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809048073000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1392924 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13249026 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393436 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.508170 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1393243 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13232435 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393755 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.494090 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.335991 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 163.453449 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 171.208376 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.346359 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.319245 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.334391 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 242.565333 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 83.938780 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 185.493697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.473760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.163943 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.362292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63330121 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63330121 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3955641 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1077876 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2532941 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7566458 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3102475 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 828519 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1367883 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5298877 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113517 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19685 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51083 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122198 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21798 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55320 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199316 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7058116 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1906395 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3900824 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12865335 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7058116 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1906395 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3900824 # number of overall hits -system.cpu0.dcache.overall_hits::total 12865335 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 705857 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 97562 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 561486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1364905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162429 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43967 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 644644 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 851040 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9228 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2243 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7808 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19279 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 868286 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 141529 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1206130 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2215945 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101270 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.131021 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000072 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000025 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110500 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065521 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.239315 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.148709 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110500 # 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mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101270 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104338 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040484 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000072 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032226 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070422 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6004498488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1711275000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4293223488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6004498488 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011105 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011105 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011105 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16739 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16739 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16739 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16739 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16739 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16739 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123075 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329781 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452856 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 123075 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329781 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452856 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 123075 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329781 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452856 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1746541000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4501465478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6248006478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1746541000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4501465478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6248006478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1746541000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4501465478 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6248006478 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13796.894549 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1195033 # DTB read hits -system.cpu1.dtb.read_misses 1325 # DTB read misses -system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 141268 # DTB read accesses -system.cpu1.dtb.write_hits 894434 # DTB write hits -system.cpu1.dtb.write_misses 169 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 56923 # DTB write accesses -system.cpu1.dtb.data_hits 2089467 # DTB hits -system.cpu1.dtb.data_misses 1494 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 198191 # DTB accesses -system.cpu1.itb.fetch_hits 856224 # ITB hits -system.cpu1.itb.fetch_misses 659 # ITB misses -system.cpu1.itb.fetch_acv 35 # ITB acv -system.cpu1.itb.fetch_accesses 856883 # ITB accesses +system.cpu1.dtb.read_hits 1115382 # DTB read hits +system.cpu1.dtb.read_misses 1270 # DTB read misses +system.cpu1.dtb.read_acv 33 # DTB read access violations +system.cpu1.dtb.read_accesses 123322 # DTB read accesses +system.cpu1.dtb.write_hits 822469 # DTB write hits +system.cpu1.dtb.write_misses 154 # DTB write misses +system.cpu1.dtb.write_acv 18 # DTB write access violations +system.cpu1.dtb.write_accesses 50514 # DTB write accesses +system.cpu1.dtb.data_hits 1937851 # DTB hits +system.cpu1.dtb.data_misses 1424 # DTB misses +system.cpu1.dtb.data_acv 51 # DTB access violations +system.cpu1.dtb.data_accesses 173836 # DTB accesses +system.cpu1.itb.fetch_hits 768661 # ITB hits +system.cpu1.itb.fetch_misses 636 # ITB misses +system.cpu1.itb.fetch_acv 28 # ITB acv +system.cpu1.itb.fetch_accesses 769297 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -935,64 +930,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953248779 # number of cpu cycles simulated +system.cpu1.numCycles 953409174 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7920155 # Number of instructions committed -system.cpu1.committedOps 7920155 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7379126 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45865 # Number of float alu accesses -system.cpu1.num_func_calls 207333 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1021718 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7379126 # number of integer instructions -system.cpu1.num_fp_insts 45865 # number of float instructions -system.cpu1.num_int_register_reads 10346831 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5362502 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24725 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 25053 # number of times the floating registers were written -system.cpu1.num_mem_refs 2096589 # number of memory refs -system.cpu1.num_load_insts 1199833 # Number of load instructions -system.cpu1.num_store_insts 896756 # Number of store instructions -system.cpu1.num_idle_cycles 922000099.418594 # Number of idle cycles -system.cpu1.num_busy_cycles 31248679.581406 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032781 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967219 # Percentage of idle cycles -system.cpu1.Branches 1295631 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410705 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5234650 66.08% 71.26% # Class of executed instruction -system.cpu1.op_class::IntMult 8605 0.11% 71.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.37% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5163 0.07% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::MemRead 1228944 15.51% 86.96% # Class of executed instruction -system.cpu1.op_class::MemWrite 897985 11.34% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134844 1.70% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7126126 # Number of instructions committed +system.cpu1.committedOps 7126126 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6614481 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39892 # Number of float alu accesses +system.cpu1.num_func_calls 202987 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849967 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6614481 # number of integer instructions +system.cpu1.num_fp_insts 39892 # number of float instructions +system.cpu1.num_int_register_reads 9205425 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4843983 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 21026 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21409 # number of times the floating registers were written +system.cpu1.num_mem_refs 1944596 # number of memory refs +system.cpu1.num_load_insts 1119921 # Number of load instructions +system.cpu1.num_store_insts 824675 # Number of store instructions +system.cpu1.num_idle_cycles 926242764.786654 # Number of idle cycles +system.cpu1.num_busy_cycles 27166409.213346 # Number of busy cycles +system.cpu1.not_idle_fraction 0.028494 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.971506 # Percentage of idle cycles +system.cpu1.Branches 1116663 # Number of branches fetched +system.cpu1.op_class::No_OpClass 388723 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4626654 64.91% 70.37% # Class of executed instruction +system.cpu1.op_class::IntMult 7726 0.11% 70.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.47% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3756 0.05% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 538 0.01% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::MemRead 1147644 16.10% 86.64% # Class of executed instruction +system.cpu1.op_class::MemWrite 825879 11.59% 98.22% # Class of executed instruction +system.cpu1.op_class::IprAccess 126681 1.78% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7921706 # Class of executed instruction +system.cpu1.op_class::total 7127601 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1010,35 +1005,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 11475270 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10735483 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123474 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 9110272 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 7311084 # Number of BTB hits +system.cpu2.branchPred.lookups 11557403 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10821969 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 122344 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 9245404 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 7393469 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.250996 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 301261 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7742 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.969128 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299976 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7838 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3542926 # DTB read hits -system.cpu2.dtb.read_misses 12527 # DTB read misses -system.cpu2.dtb.read_acv 162 # DTB read access violations -system.cpu2.dtb.read_accesses 225242 # DTB read accesses -system.cpu2.dtb.write_hits 2156991 # DTB write hits -system.cpu2.dtb.write_misses 2860 # DTB write misses -system.cpu2.dtb.write_acv 147 # DTB write access violations -system.cpu2.dtb.write_accesses 84372 # DTB write accesses -system.cpu2.dtb.data_hits 5699917 # DTB hits -system.cpu2.dtb.data_misses 15387 # DTB misses -system.cpu2.dtb.data_acv 309 # DTB access violations -system.cpu2.dtb.data_accesses 309614 # DTB accesses -system.cpu2.itb.fetch_hits 534150 # ITB hits -system.cpu2.itb.fetch_misses 5562 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539712 # ITB accesses +system.cpu2.dtb.read_hits 3543723 # DTB read hits +system.cpu2.dtb.read_misses 12250 # DTB read misses +system.cpu2.dtb.read_acv 123 # DTB read access violations +system.cpu2.dtb.read_accesses 249931 # DTB read accesses +system.cpu2.dtb.write_hits 2185333 # DTB write hits +system.cpu2.dtb.write_misses 2753 # DTB write misses +system.cpu2.dtb.write_acv 125 # DTB write access violations +system.cpu2.dtb.write_accesses 92110 # DTB write accesses +system.cpu2.dtb.data_hits 5729056 # DTB hits +system.cpu2.dtb.data_misses 15003 # DTB misses +system.cpu2.dtb.data_acv 248 # DTB access violations +system.cpu2.dtb.data_accesses 342041 # DTB accesses +system.cpu2.itb.fetch_hits 552866 # ITB hits +system.cpu2.itb.fetch_misses 5354 # ITB misses +system.cpu2.itb.fetch_acv 182 # ITB acv +system.cpu2.itb.fetch_accesses 558220 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1051,304 +1046,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31796057 # number of cpu cycles simulated +system.cpu2.numCycles 33083271 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9294739 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42846452 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11475270 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7612345 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20400927 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 406592 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 934 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9632 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1958 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 201207 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 109893 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2820959 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 91095 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 30222906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.417681 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345063 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9301099 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 42932048 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 11557403 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 7693445 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 21583805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 404638 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 962 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10456 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1990 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 197395 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 92170 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2784665 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90858 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 31390787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367664 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.311444 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20065674 66.39% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 304778 1.01% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 474119 1.57% 68.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5709833 18.89% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 849889 2.81% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 195244 0.65% 91.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 232616 0.77% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433559 1.43% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1957194 6.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21183291 67.48% 67.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 297740 0.95% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 468841 1.49% 69.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5764163 18.36% 88.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 882544 2.81% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 193394 0.62% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 232558 0.74% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 434405 1.38% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1933851 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30222906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.360902 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.347540 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7641311 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13078900 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8781400 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530431 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 190274 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 176731 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13389 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 39469462 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42545 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 190274 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7916618 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4614900 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6334560 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 9009266 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2156706 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 38654408 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 61763 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 395728 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57668 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1091797 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25842385 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 48471958 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 48411597 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56430 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 23967156 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1875229 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535043 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63361 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828496 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3518120 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2250866 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 468779 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 334709 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 36116015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 683906 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35834403 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15167 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2521371 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1120007 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 489344 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30222906 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.185670 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.632890 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 31390787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.349343 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.297697 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7618981 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14231209 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8576643 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 528584 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 189420 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174742 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13252 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 39552027 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41601 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 189420 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7898470 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4727919 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6647041 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8797977 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2884017 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 38737545 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 58522 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 372966 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93481 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1809588 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 25849349 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 48570643 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 48506980 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 59488 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 23977354 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1871995 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535640 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63418 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3866497 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3518835 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2279192 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 461417 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 331685 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 36218811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 686292 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35933838 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15798 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2519858 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1130776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 490718 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 31390787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.144726 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.617565 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17428882 57.67% 57.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2748935 9.10% 66.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1369590 4.53% 71.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 6435558 21.29% 92.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1033977 3.42% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 595062 1.97% 97.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 394555 1.31% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169710 0.56% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 46637 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18577248 59.18% 59.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2723782 8.68% 67.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1358088 4.33% 72.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 6489843 20.67% 92.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1045865 3.33% 96.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 589790 1.88% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396015 1.26% 99.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 165397 0.53% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44759 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30222906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 31390787 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 86081 21.74% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 183352 46.31% 68.05% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126504 31.95% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81235 20.78% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 183347 46.90% 67.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126357 32.32% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 29630335 82.69% 82.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21208 0.06% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20533 0.06% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3671135 10.24% 93.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2181666 6.09% 99.15% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305842 0.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2960 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 29699192 82.65% 82.66% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21615 0.06% 82.72% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 21814 0.06% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1480 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3672081 10.22% 93.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2209398 6.15% 99.15% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305298 0.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35834403 # Type of FU issued -system.cpu2.iq.rate 1.127008 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 395937 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011049 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 102047941 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39206340 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 35210799 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 254875 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 120668 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117568 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36091226 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136658 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206130 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 35933838 # Type of FU issued +system.cpu2.iq.rate 1.086163 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 390939 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.010879 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 103401518 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39305388 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 35307106 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 263682 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125410 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122335 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36181025 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140792 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 202971 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 426126 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1149 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5847 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 179431 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 432355 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1077 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5954 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178558 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5057 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 224722 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4490 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 225000 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 190274 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4003128 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 196899 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 38192826 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 53825 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3518120 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2250866 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 608609 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12914 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 142416 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5847 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 60692 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135198 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195890 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 35634663 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3564372 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 199740 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 189420 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4054480 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 208473 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 38277538 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51152 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3518835 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2279192 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 610930 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12812 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 160010 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5954 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 60508 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134714 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 35737943 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3564708 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195895 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1392905 # number of nop insts executed -system.cpu2.iew.exec_refs 5729004 # number of memory reference insts executed -system.cpu2.iew.exec_branches 8402054 # Number of branches executed -system.cpu2.iew.exec_stores 2164632 # Number of stores executed -system.cpu2.iew.exec_rate 1.120726 # Inst execution rate -system.cpu2.iew.wb_sent 35371199 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 35328367 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 20848782 # num instructions producing a value -system.cpu2.iew.wb_consumers 24577214 # num instructions consuming a value +system.cpu2.iew.exec_nop 1372435 # number of nop insts executed +system.cpu2.iew.exec_refs 5757521 # number of memory reference insts executed +system.cpu2.iew.exec_branches 8471480 # Number of branches executed +system.cpu2.iew.exec_stores 2192813 # Number of stores executed +system.cpu2.iew.exec_rate 1.080242 # Inst execution rate +system.cpu2.iew.wb_sent 35472276 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 35429441 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 20887132 # num instructions producing a value +system.cpu2.iew.wb_consumers 24638595 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.111093 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.848297 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.070917 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.847740 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2641573 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194562 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 179155 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 29759977 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.193046 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.869762 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2638965 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 195574 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 178349 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30927462 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.150843 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846358 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18187552 61.11% 61.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2254342 7.58% 68.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1186941 3.99% 72.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6165862 20.72% 93.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562678 1.89% 95.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 198394 0.67% 95.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 165216 0.56% 96.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 166703 0.56% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 872289 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19331784 62.51% 62.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2240622 7.24% 69.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1164134 3.76% 73.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6211408 20.08% 93.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 591221 1.91% 95.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197085 0.64% 96.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 163594 0.53% 96.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163249 0.53% 97.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 864365 2.79% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 29759977 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 35505021 # Number of instructions committed -system.cpu2.commit.committedOps 35505021 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30927462 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 35592650 # Number of instructions committed +system.cpu2.commit.committedOps 35592650 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5163429 # Number of memory references committed -system.cpu2.commit.loads 3091994 # Number of loads committed -system.cpu2.commit.membars 68344 # Number of memory barriers committed -system.cpu2.commit.branches 8230032 # Number of branches committed -system.cpu2.commit.fp_insts 115972 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 33980571 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241816 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228927 3.46% 3.46% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 28694755 80.82% 84.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20756 0.06% 84.34% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20096 0.06% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3160338 8.90% 93.30% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2073079 5.84% 99.14% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305842 0.86% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5187114 # Number of memory references committed +system.cpu2.commit.loads 3086480 # Number of loads committed +system.cpu2.commit.membars 68869 # Number of memory barriers committed +system.cpu2.commit.branches 8299152 # Number of branches committed +system.cpu2.commit.fp_insts 120520 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 34085086 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241488 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1210365 3.40% 3.40% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 28775352 80.85% 84.25% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 21144 0.06% 84.31% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21379 0.06% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1480 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3155349 8.87% 93.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2102283 5.91% 99.14% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305298 0.86% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 35505021 # Class of committed instruction -system.cpu2.commit.bw_lim_events 872289 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 66956679 # The number of ROB reads -system.cpu2.rob.rob_writes 76754434 # The number of ROB writes -system.cpu2.timesIdled 177058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1573151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1744013124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 34278550 # Number of Instructions Simulated -system.cpu2.committedOps 34278550 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.927579 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.927579 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.078075 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.078075 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 46864030 # number of integer regfile reads -system.cpu2.int_regfile_writes 24760821 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71108 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71427 # number of floating regfile writes -system.cpu2.misc_regfile_reads 6062934 # number of misc regfile reads -system.cpu2.misc_regfile_writes 274246 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 35592650 # Class of committed instruction +system.cpu2.commit.bw_lim_events 864365 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 68219321 # The number of ROB reads +system.cpu2.rob.rob_writes 76925100 # The number of ROB writes +system.cpu2.timesIdled 177793 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1692484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1742724515 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 34385245 # Number of Instructions Simulated +system.cpu2.committedOps 34385245 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.962136 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.962136 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.039354 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.039354 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 46956630 # number of integer regfile reads +system.cpu2.int_regfile_writes 24762728 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74199 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74347 # number of floating regfile writes +system.cpu2.misc_regfile_reads 6109617 # number of misc regfile reads +system.cpu2.misc_regfile_writes 275370 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1397,37 +1392,33 @@ system.iobus.pkt_size_system.bridge.master::total 45568 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2206000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5366000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2084000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 89821669 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 88878376 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8844000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17358000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254132 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254039 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254132 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078383 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078383 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693946387000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254039 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078377 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078377 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1441,14 +1432,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040972707 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2040972707 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9722962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9722962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2243179414 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2243179414 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9722962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9722962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9722962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9722962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1465,14 +1456,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 56202.092486 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 56202.092486 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 56202.092486 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,245 +1474,248 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176972707 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1176972707 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 71 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17168 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17168 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 71 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 71 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 71 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 71 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6172962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6172962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1384779414 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1384779414 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6172962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6172962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6172962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6172962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.410405 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.413169 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.413169 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.410405 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.410405 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86943.126761 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80660.497088 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80660.497088 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337470 # number of replacements -system.l2c.tags.tagsinuse 65419.393999 # Cycle average of tags in use -system.l2c.tags.total_refs 4005329 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402632 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.947866 # Average number of references to valid blocks. +system.l2c.tags.replacements 337421 # number of replacements +system.l2c.tags.tagsinuse 65422.020035 # Cycle average of tags in use +system.l2c.tags.total_refs 4006967 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402583 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.953145 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54633.992785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2282.515139 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2705.284872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.585010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 602.481810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2408.251048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2250.283336 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.034828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041279 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.036747 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.034337 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998221 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54749.853403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2632.785518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2879.050483 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 437.699618 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 303562500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 567210000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 333601500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 379751500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 713353000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 597249000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683314000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1280563000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.523810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408930 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255830 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.140797 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007340 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157938 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061492 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030003 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.393939 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.367084 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.272781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.136459 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006824 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.117863 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.045985 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020829 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029944 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029944 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70961.538462 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117392.867322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125466.345449 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122724.652761 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122845.861807 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116726.778846 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117147.104153 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116954.769447 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196605.145414 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 192371.673004 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 194316.546763 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 205926.851852 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 199449.317227 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294907 # Transaction distribution +system.membus.trans_dist::ReadResp 294893 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116913 # Transaction distribution -system.membus.trans_dist::CleanEvict 262319 # Transaction distribution +system.membus.trans_dist::Writeback 116701 # Transaction distribution +system.membus.trans_dist::CleanEvict 261800 # Transaction distribution system.membus.trans_dist::UpgradeReq 141 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 143 # Transaction distribution -system.membus.trans_dist::ReadExReq 115651 # Transaction distribution -system.membus.trans_dist::ReadExResp 115651 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287769 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 115600 # Transaction distribution +system.membus.trans_dist::ReadExResp 115600 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288004 # Transaction distribution +system.membus.trans_dist::BadAddressError 255 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1178190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303213 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177927 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1302846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30626752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30672320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33336640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 841369 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30608832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30654400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33318656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 161 # Total snoops (count) +system.membus.snoop_fanout::samples 840917 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 841369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840917 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 841369 # Request fanout histogram -system.membus.reqLayer0.occupancy 11017000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840917 # Request fanout histogram +system.membus.reqLayer0.occupancy 11282500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 393892331 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 355534840 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 441141955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 377985955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 28782491 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4716700 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2358029 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1601 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2061814 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063159 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 883059 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1572257 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 879803 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1563697 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302698 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302698 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 963876 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1090815 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2890767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4213603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7104370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61685760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142710656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204396416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141516 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4871742 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029009 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.167832 # Request fanout histogram +system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 38 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302846 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302846 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 965048 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091237 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 255 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 17168 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2894139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7108173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61761536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142741760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204503296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421014 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5154488 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000869 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.029472 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4730418 97.10% 97.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141324 2.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5150007 99.91% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4481 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4871742 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1371248000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5154488 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1335525500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 102462 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 686121188 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 679735096 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 778360963 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 746367473 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 535c26a20..a32ac72f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,166 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846117 # Number of seconds simulated -sim_ticks 2846117015000 # Number of ticks simulated -final_tick 2846117015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848053 # Number of seconds simulated +sim_ticks 2848053071500 # Number of ticks simulated +final_tick 2848053071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113156 # Simulator instruction rate (inst/s) -host_op_rate 137057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2513496102 # Simulator tick rate (ticks/s) -host_mem_usage 647580 # Number of bytes of host memory used -host_seconds 1132.33 # Real time elapsed on the host -sim_insts 128130877 # Number of instructions simulated -sim_ops 155193960 # Number of ops (including micro ops) simulated +host_inst_rate 153295 # Simulator instruction rate (inst/s) +host_op_rate 185627 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3443122383 # Simulator tick rate (ticks/s) +host_mem_usage 659004 # Number of bytes of host memory used +host_seconds 827.17 # Real time elapsed on the host +sim_insts 126801159 # Number of instructions simulated +sim_ops 153545030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 7296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8768 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1474816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1242668 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8247680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 378112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 721620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 564672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1683840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1312624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8530944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 199296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 609360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 366080 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12640384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1474816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 378112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1852928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8933696 # Number of bytes written to this memory +system.physmem.bytes_read::total 12712960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1683840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 199296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1883136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8845504 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8951260 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 114 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8863068 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 137 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19938 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 38 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3114 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5720 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198048 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139589 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138211 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143980 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2563 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142602 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3079 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 518185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 436619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2897871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 132852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 253545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 198401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 591225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 460885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2995360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 213957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 128537 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4441273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 518185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 132852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3138907 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4463737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 591225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 661201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3105807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3145078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3138907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3111974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3105807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3079 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 518185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 442776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2897871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 132852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 253559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 198401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 591225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 467038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2995360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 213971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 128537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7586351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198048 # Number of read requests accepted -system.physmem.writeReqs 143980 # Number of write requests accepted -system.physmem.readBursts 198048 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12666176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 8963584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12640384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8951260 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51245 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12439 # Per bank write bursts -system.physmem.perBankRdBursts::1 12567 # Per bank write bursts -system.physmem.perBankRdBursts::2 12508 # Per bank write bursts -system.physmem.perBankRdBursts::3 12584 # Per bank write bursts -system.physmem.perBankRdBursts::4 14823 # Per bank write bursts -system.physmem.perBankRdBursts::5 11920 # Per bank write bursts -system.physmem.perBankRdBursts::6 13135 # Per bank write bursts -system.physmem.perBankRdBursts::7 13383 # Per bank write bursts -system.physmem.perBankRdBursts::8 12319 # Per bank write bursts -system.physmem.perBankRdBursts::9 12338 # Per bank write bursts -system.physmem.perBankRdBursts::10 11698 # Per bank write bursts -system.physmem.perBankRdBursts::11 11134 # Per bank write bursts -system.physmem.perBankRdBursts::12 11462 # Per bank write bursts -system.physmem.perBankRdBursts::13 11917 # Per bank write bursts -system.physmem.perBankRdBursts::14 11661 # Per bank write bursts -system.physmem.perBankRdBursts::15 12021 # Per bank write bursts -system.physmem.perBankWrBursts::0 8771 # Per bank write bursts -system.physmem.perBankWrBursts::1 9038 # Per bank write bursts -system.physmem.perBankWrBursts::2 9230 # Per bank write bursts -system.physmem.perBankWrBursts::3 8945 # Per bank write bursts -system.physmem.perBankWrBursts::4 8307 # Per bank write bursts -system.physmem.perBankWrBursts::5 8620 # Per bank write bursts -system.physmem.perBankWrBursts::6 9591 # Per bank write bursts -system.physmem.perBankWrBursts::7 9703 # Per bank write bursts -system.physmem.perBankWrBursts::8 8875 # Per bank write bursts -system.physmem.perBankWrBursts::9 8727 # Per bank write bursts -system.physmem.perBankWrBursts::10 8430 # Per bank write bursts -system.physmem.perBankWrBursts::11 8199 # Per bank write bursts -system.physmem.perBankWrBursts::12 8380 # Per bank write bursts -system.physmem.perBankWrBursts::13 8472 # Per bank write bursts -system.physmem.perBankWrBursts::14 8531 # Per bank write bursts -system.physmem.perBankWrBursts::15 8237 # Per bank write bursts +system.physmem.bw_total::total 7575711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199182 # Number of read requests accepted +system.physmem.writeReqs 142602 # Number of write requests accepted +system.physmem.readBursts 199182 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 142602 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12737472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.physmem.bytesWritten 8875904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12712960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8863068 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49648 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12703 # Per bank write bursts +system.physmem.perBankRdBursts::1 12645 # Per bank write bursts +system.physmem.perBankRdBursts::2 12416 # Per bank write bursts +system.physmem.perBankRdBursts::3 12383 # Per bank write bursts +system.physmem.perBankRdBursts::4 15579 # Per bank write bursts +system.physmem.perBankRdBursts::5 12155 # Per bank write bursts +system.physmem.perBankRdBursts::6 12470 # Per bank write bursts +system.physmem.perBankRdBursts::7 12693 # Per bank write bursts +system.physmem.perBankRdBursts::8 11969 # Per bank write bursts +system.physmem.perBankRdBursts::9 11857 # Per bank write bursts +system.physmem.perBankRdBursts::10 12504 # Per bank write bursts +system.physmem.perBankRdBursts::11 11838 # Per bank write bursts +system.physmem.perBankRdBursts::12 11708 # Per bank write bursts +system.physmem.perBankRdBursts::13 12391 # Per bank write bursts +system.physmem.perBankRdBursts::14 11950 # Per bank write bursts +system.physmem.perBankRdBursts::15 11762 # Per bank write bursts +system.physmem.perBankWrBursts::0 9214 # Per bank write bursts +system.physmem.perBankWrBursts::1 9232 # Per bank write bursts +system.physmem.perBankWrBursts::2 9104 # Per bank write bursts +system.physmem.perBankWrBursts::3 8883 # Per bank write bursts +system.physmem.perBankWrBursts::4 8269 # Per bank write bursts +system.physmem.perBankWrBursts::5 8437 # Per bank write bursts +system.physmem.perBankWrBursts::6 8818 # Per bank write bursts +system.physmem.perBankWrBursts::7 8777 # Per bank write bursts +system.physmem.perBankWrBursts::8 8437 # Per bank write bursts +system.physmem.perBankWrBursts::9 8418 # Per bank write bursts +system.physmem.perBankWrBursts::10 9013 # Per bank write bursts +system.physmem.perBankWrBursts::11 8780 # Per bank write bursts +system.physmem.perBankWrBursts::12 8383 # Per bank write bursts +system.physmem.perBankWrBursts::13 8480 # Per bank write bursts +system.physmem.perBankWrBursts::14 8424 # Per bank write bursts +system.physmem.perBankWrBursts::15 8017 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 2846116455500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 2848052462500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197468 # Read request sizes (log2) +system.physmem.readPktSize::6 198602 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139589 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138211 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,155 +184,157 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.329061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.886171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 298.768529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 49038 53.81% 53.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17709 19.43% 73.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6298 6.91% 80.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3704 4.06% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2913 3.20% 87.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1386 1.52% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 897 0.98% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1023 1.12% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8170 8.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91138 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.308683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.324450 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6990 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.033758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.625060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.557866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5837 83.49% 83.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 357 5.11% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 222 3.18% 91.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 60 0.86% 92.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 0.92% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 166 2.37% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 20 0.29% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.09% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.14% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.39% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.11% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.20% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6991 # Writes before turning the bus around for reads -system.physmem.totQLat 5451252873 # Total ticks spent queuing -system.physmem.totMemAccLat 9162046623 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27544.24 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.573648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.731983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.151175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46893 52.63% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17637 19.79% 72.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6363 7.14% 79.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3624 4.07% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2948 3.31% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1436 1.61% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 938 1.05% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 975 1.09% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8286 9.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89100 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6864 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.995047 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 543.916897 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6863 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6864 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6864 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.204837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.711823 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.958888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5637 82.12% 82.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 489 7.12% 89.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.19% 90.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 154 2.24% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 37 0.54% 93.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 124 1.81% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 47 0.68% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.23% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.31% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.28% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.15% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 153 2.23% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 30 0.44% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6864 # Writes before turning the bus around for reads +system.physmem.totQLat 5502163905 # Total ticks spent queuing +system.physmem.totMemAccLat 9233845155 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 995115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27645.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46294.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46395.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 164305 # Number of row buffer hits during reads -system.physmem.writeRowHits 82521 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.91 # Row buffer hit rate for writes -system.physmem.avgGap 8321296.66 # Average gap between requests -system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359440200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 196123125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 806200200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 467888400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83210904225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634677575750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905612577260 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.548459 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719308511052 # Time in different power states -system.physmem_0.memoryStateTime::REF 95038060000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 165564 # Number of row buffer hits during reads +system.physmem.writeRowHits 83044 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.87 # Row buffer hit rate for writes +system.physmem.avgGap 8332901.66 # Average gap between requests +system.physmem.pageHitRate 73.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 347056920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 189366375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 803743200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 458356320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84074155830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1635078931500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1906972178385 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.571882 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719967809945 # Time in different power states +system.physmem_0.memoryStateTime::REF 95102540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31769437698 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32976648805 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329563080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179821125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 737482200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 439674480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82251132525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635519480750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905351599520 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.456762 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720714979061 # Time in different power states -system.physmem_1.memoryStateTime::REF 95038060000 # Time in different power states +system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748628400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 440328960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83156024340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635884310000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1906754570145 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.495475 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721316836638 # Time in different power states +system.physmem_1.memoryStateTime::REF 95102540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30363879439 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31633548862 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -362,15 +360,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 34784409 # Number of BP lookups -system.cpu0.branchPred.condPredicted 16478031 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1480168 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 19725615 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14342133 # Number of BTB hits +system.cpu0.branchPred.lookups 36422708 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17757542 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1699668 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20591819 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 15078708 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.708167 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11162624 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 702720 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.226693 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11344544 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 821497 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -401,58 +399,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 65972 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65972 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 43486 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22486 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65972 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65972 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65972 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6612 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9312.931281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6218.139441 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6425 97.17% 97.17% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 170 2.57% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6612 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5105 77.21% 77.21% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1507 22.79% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6612 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 72997 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 72997 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47155 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25842 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 72997 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 72997 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 72997 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7509 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9271.690184 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8241.046102 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7465 99.41% 99.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 36 0.48% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7509 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 581566000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 581566000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 581566000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5843 77.81% 77.81% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1666 22.19% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7509 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72997 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65972 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6612 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72997 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6612 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72584 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 80506 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23562231 # DTB read hits -system.cpu0.dtb.read_misses 59962 # DTB read misses -system.cpu0.dtb.write_hits 17431474 # DTB write hits -system.cpu0.dtb.write_misses 6010 # DTB write misses +system.cpu0.dtb.read_hits 24918355 # DTB read hits +system.cpu0.dtb.read_misses 66392 # DTB read misses +system.cpu0.dtb.write_hits 18544526 # DTB write hits +system.cpu0.dtb.write_misses 6605 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3494 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1076 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1600 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3803 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1293 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2019 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23622193 # DTB read accesses -system.cpu0.dtb.write_accesses 17437484 # DTB write accesses +system.cpu0.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24984747 # DTB read accesses +system.cpu0.dtb.write_accesses 18551131 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40993705 # DTB hits -system.cpu0.dtb.misses 65972 # DTB misses -system.cpu0.dtb.accesses 41059677 # DTB accesses +system.cpu0.dtb.hits 43462881 # DTB hits +system.cpu0.dtb.misses 72997 # DTB misses +system.cpu0.dtb.accesses 43535878 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -482,36 +478,37 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3855 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3855 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3550 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3855 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3855 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3855 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2424 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9797.993767 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 8035.967164 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 2422 99.92% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2424 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2124 87.62% 87.62% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.38% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2424 # Table walker page sizes translated +system.cpu0.itb.walker.walks 4165 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4165 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3841 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4165 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4165 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4165 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2676 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9686.198014 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6109.891448 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2598 97.09% 97.09% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 50 1.87% 98.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 27 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2676 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 580856500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 580856500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 580856500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2357 88.08% 88.08% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 319 11.92% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2676 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3855 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3855 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4165 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4165 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2424 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2424 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6279 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 68397916 # ITB inst hits -system.cpu0.itb.inst_misses 3855 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2676 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2676 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 71531107 # ITB inst hits +system.cpu0.itb.inst_misses 4165 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -520,131 +517,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2226 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2451 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7522 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 8112 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 68401771 # ITB inst accesses -system.cpu0.itb.hits 68397916 # DTB hits -system.cpu0.itb.misses 3855 # DTB misses -system.cpu0.itb.accesses 68401771 # DTB accesses -system.cpu0.numCycles 225406925 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71535272 # ITB inst accesses +system.cpu0.itb.hits 71531107 # DTB hits +system.cpu0.itb.misses 4165 # DTB misses +system.cpu0.itb.accesses 71535272 # DTB accesses +system.cpu0.numCycles 246249018 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 107236402 # Number of instructions committed -system.cpu0.committedOps 129680129 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8567834 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2087 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5466862375 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.101963 # CPI: cycles per instruction -system.cpu0.ipc 0.475746 # IPC: instructions per cycle +system.cpu0.committedInsts 113090684 # Number of instructions committed +system.cpu0.committedOps 136745700 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8942808 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1853 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5449882320 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.177447 # CPI: cycles per instruction +system.cpu0.ipc 0.459253 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2088 # number of quiesce instructions executed -system.cpu0.tickCycles 187552407 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 37854518 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 678280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.010035 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39540240 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 678792 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 58.250893 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.010035 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947285 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947285 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.tickCycles 199226503 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 47022515 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 754267 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.799422 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41868735 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 754779 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.471516 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 600230000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.799422 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968358 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968358 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81933612 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81933612 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22071197 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22071197 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16340314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16340314 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307086 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307086 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357744 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 357744 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352756 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352756 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38411511 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38411511 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38718597 # number of overall hits -system.cpu0.dcache.overall_hits::total 38718597 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 442022 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 442022 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555005 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555005 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131972 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131972 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20768 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20768 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21303 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21303 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 997027 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 997027 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1128999 # number of overall misses -system.cpu0.dcache.overall_misses::total 1128999 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5846536500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5846536500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8888918500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8888918500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319234500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 319234500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481221000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 481221000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 684000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 684000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14735455000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14735455000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14735455000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14735455000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22513219 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22513219 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16895319 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16895319 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439058 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 439058 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378512 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378512 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39408538 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39408538 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39847596 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39847596 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019634 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019634 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032850 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032850 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054867 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054867 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025300 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025300 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028333 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028333 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13226.799797 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13226.799797 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16015.925082 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16015.925082 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15371.460901 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15371.460901 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22589.353612 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22589.353612 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 86874809 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 86874809 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23308542 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23308542 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17374131 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17374131 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329905 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 329905 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374910 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374910 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371257 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 371257 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40682673 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40682673 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 41012578 # number of overall hits +system.cpu0.dcache.overall_hits::total 41012578 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 490349 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 490349 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 600389 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 600389 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141605 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141605 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21484 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21484 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20155 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20155 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1090738 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1090738 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1232343 # number of overall misses +system.cpu0.dcache.overall_misses::total 1232343 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6919620500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6919620500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11358969500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11358969500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328836500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 328836500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472700000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 472700000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 403000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 403000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 18278590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18278590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 18278590000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18278590000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23798891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23798891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17974520 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17974520 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471510 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 471510 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391412 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391412 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41773411 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41773411 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 42244921 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 42244921 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020604 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033402 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033402 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300322 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300322 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054199 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054199 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026111 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026111 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029171 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029171 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16758.002380 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16758.002380 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14832.388385 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14832.388385 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,149 +650,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 490245 # number of writebacks -system.cpu0.dcache.writebacks::total 490245 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69954 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 69954 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243081 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 243081 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14749 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14749 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 313035 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 313035 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 313035 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 313035 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372068 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 372068 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016527 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226417 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226417 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015902 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015902 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056951 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056951 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017356 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017356 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019660 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019660 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21590.198564 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21590.198564 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 540480 # number of writebacks +system.cpu0.dcache.writebacks::total 540480 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 76076 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 76076 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 264589 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 264589 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14754 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14754 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 340665 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 340665 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 340665 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 340665 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414273 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 414273 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335800 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 335800 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107967 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 107967 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6730 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6730 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20155 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20155 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 750073 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 750073 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 858040 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 858040 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32040 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60762 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5238286000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5238286000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6456534000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6456534000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810830000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810830000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104761500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104761500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452552000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452552000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 396000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 396000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11694820000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11694820000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13505650000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13505650000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6348331500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6348331500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5156547500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5156547500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11504879000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11504879000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017407 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017407 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018682 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018682 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228981 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228981 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016978 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016978 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051493 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051493 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017956 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017956 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020311 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020311 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12644.526677 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12644.526677 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13999.016469 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193589.580643 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193589.580643 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164938.326581 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 164938.326581 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180105.121609 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 180105.121609 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15591.575753 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15591.575753 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15740.117011 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15740.117011 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198137.687266 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198137.687266 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1886353 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.780174 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 66503170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1886865 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.245325 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6541312000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780174 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 2044285 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.729271 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69477789 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2044797 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.977842 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6924011000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.729271 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999471 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999471 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 138666991 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 138666991 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 66503170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 66503170 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 66503170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 66503170 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 66503170 # number of overall hits -system.cpu0.icache.overall_hits::total 66503170 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1886884 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1886884 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1886884 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1886884 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1886884 # number of overall misses -system.cpu0.icache.overall_misses::total 1886884 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17552107500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17552107500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 17552107500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17552107500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 17552107500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17552107500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 68390054 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 68390054 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 68390054 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 68390054 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 68390054 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 68390054 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027590 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027590 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027590 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027590 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027590 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027590 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9302.165634 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9302.165634 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9302.165634 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9302.165634 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 145090031 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 145090031 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69477789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69477789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69477789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69477789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69477789 # number of overall hits +system.cpu0.icache.overall_hits::total 69477789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2044818 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2044818 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2044818 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2044818 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 2044818 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 71522607 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 71522607 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028590 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028590 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028590 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028590 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028590 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028590 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10033.781246 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10033.781246 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10033.781246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10033.781246 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,463 +801,469 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1886884 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1886884 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1886884 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1886884 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1886884 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1886884 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16608666000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16608666000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16608666000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16608666000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16608666000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16608666000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027590 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027590 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8802.165899 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2044818 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2044818 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2044818 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2044818 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 2044818 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 2044818 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3915 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3915 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19494848000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19494848000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19494848000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19494848000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19494848000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19494848000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557217500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557217500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557217500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 557217500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028590 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028590 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028590 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9533.781491 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1753692 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1753724 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1923323 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1923513 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 165 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 222140 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 284631 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16080.562269 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4811395 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 300867 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.991767 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8557.843574 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.688699 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065125 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4677.760567 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1660.845415 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1126.358889 # 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average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59632.538576 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19978.894616 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19978.894616 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15299.902729 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15299.902729 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 105899.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 105899.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105 # 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average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.159659 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 171249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 171249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 134550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2542059 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26162 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 862676 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2186135 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 279695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43745 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114531 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284097 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1886884 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603437 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5633887 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2503276 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167039 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8316030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120979776 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82538715 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17692 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314324 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 203850507 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1178802 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 6482684 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.179159 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.383485 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5752448 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2898331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 171817 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 171638 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 142841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2765458 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 746343 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2333999 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 319529 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85747 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112824 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299375 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 296092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2044818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602268 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3078 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6106044 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739032 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12492 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185819 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9043387 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 131118848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90716354 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 347920 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 222201066 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 910866 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 6693455 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.042507 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.201876 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 5321256 82.08% 82.08% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1161428 17.92% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 6409112 95.75% 95.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 284164 4.25% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 6482684 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3211889987 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 6693455 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3504755489 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113481999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115583734 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2835744437 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3073459276 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1181675942 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1298870694 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7408493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8011489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 88460994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 98861455 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 5445699 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3358034 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 328537 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3334781 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2260975 # Number of BTB hits +system.cpu1.branchPred.lookups 3534290 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1990183 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 201553 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2067319 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1417438 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.799805 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 969415 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 68088 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 68.564068 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 735878 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 53173 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1290,59 +1293,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 29420 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 29420 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21788 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7632 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 29420 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 29420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 29420 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9761.358244 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6619.660152 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2565 94.72% 94.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 128 4.73% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.30% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.04% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 4 0.15% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1720699264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1720699264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1720699264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2021 74.63% 74.63% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 687 25.37% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 29420 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 21952 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21952 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 17656 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4296 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 21952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 21952 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 21952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8000.267562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1715 92.30% 92.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 133 7.16% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 6 0.32% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2099073032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2099073032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2099073032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1319 70.99% 70.99% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 539 29.01% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1858 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21952 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 29420 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1858 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 32128 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1858 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 23810 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5163963 # DTB read hits -system.cpu1.dtb.read_misses 27269 # DTB read misses -system.cpu1.dtb.write_hits 4235498 # DTB write hits -system.cpu1.dtb.write_misses 2151 # DTB write misses +system.cpu1.dtb.read_hits 3504265 # DTB read hits +system.cpu1.dtb.read_misses 20273 # DTB read misses +system.cpu1.dtb.write_hits 2919622 # DTB write hits +system.cpu1.dtb.write_misses 1679 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2054 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 296 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 518 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1723 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 294 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5191232 # DTB read accesses -system.cpu1.dtb.write_accesses 4237649 # DTB write accesses +system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3524538 # DTB read accesses +system.cpu1.dtb.write_accesses 2921301 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9399461 # DTB hits -system.cpu1.dtb.misses 29420 # DTB misses -system.cpu1.dtb.accesses 9428881 # DTB accesses +system.cpu1.dtb.hits 6423887 # DTB hits +system.cpu1.dtb.misses 21952 # DTB misses +system.cpu1.dtb.accesses 6445839 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1372,39 +1375,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2244 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2244 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2063 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2244 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2244 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2244 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5627.290327 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 289 25.73% 25.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 792 70.53% 96.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 96.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 34 3.03% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1720133764 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1720133764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1720133764 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1951 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1951 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 155 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1796 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1951 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1951 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1951 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4130.106784 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 149 17.63% 17.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 569 67.34% 84.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 12.66% 97.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.47% 99.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.47% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2099960532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2099960532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2099960532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2244 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1951 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1951 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3367 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10150571 # ITB inst hits -system.cpu1.itb.inst_misses 2244 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2796 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 6761340 # ITB inst hits +system.cpu1.itb.inst_misses 1951 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1413,130 +1419,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1947 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10152815 # ITB inst accesses -system.cpu1.itb.hits 10150571 # DTB hits -system.cpu1.itb.misses 2244 # DTB misses -system.cpu1.itb.accesses 10152815 # DTB accesses -system.cpu1.numCycles 54273174 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6763291 # ITB inst accesses +system.cpu1.itb.hits 6761340 # DTB hits +system.cpu1.itb.misses 1951 # DTB misses +system.cpu1.itb.accesses 6763291 # DTB accesses +system.cpu1.numCycles 39381699 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20894475 # Number of instructions committed -system.cpu1.committedOps 25513831 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1850967 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2736 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5637336830 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.597489 # CPI: cycles per instruction -system.cpu1.ipc 0.384987 # IPC: instructions per cycle +system.cpu1.committedInsts 13710475 # Number of instructions committed +system.cpu1.committedOps 16799330 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1340837 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2719 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5656091241 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.872380 # CPI: cycles per instruction +system.cpu1.ipc 0.348143 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed -system.cpu1.tickCycles 38589177 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 15683997 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 232297 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.192292 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8906174 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 232671 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.277972 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90623150500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.192292 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941782 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.941782 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18859700 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18859700 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4719301 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4719301 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3908024 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3908024 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65371 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65371 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88156 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88156 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80067 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80067 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8627325 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8627325 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8692696 # number of overall hits -system.cpu1.dcache.overall_hits::total 8692696 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 183894 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 183894 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 168264 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 168264 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35705 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35705 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17716 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17716 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23526 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23526 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 352158 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 352158 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 387863 # number of overall misses -system.cpu1.dcache.overall_misses::total 387863 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2718275000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2718275000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4151672000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4151672000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326404500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 326404500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549519500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 549519500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 392000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 392000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6869947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6869947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6869947000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6869947000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4903195 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4903195 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4076288 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4076288 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101076 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 101076 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105872 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105872 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103593 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 103593 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8979483 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8979483 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9080559 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9080559 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037505 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041279 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.041279 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353249 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353249 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039218 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039218 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042714 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042714 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2719 # number of quiesce instructions executed +system.cpu1.tickCycles 26653258 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 12728441 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 152894 # number of replacements +system.cpu1.dcache.tags.tagsinuse 470.093140 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6072239 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 153243 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.624903 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 110033723500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.093140 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918151 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.918151 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12903758 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12903758 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3189039 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3189039 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2677291 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2677291 # 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number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6466111500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6466111500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6466111500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3319602 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3319602 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2797331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2797331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66232 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66232 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85939 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 85939 # 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miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366167 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.193998 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.193998 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.276916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.276916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040969 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.040969 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044452 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044452 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.081187 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16300.081187 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36137.320893 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36137.320893 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19299.004319 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19299.004319 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26423.959674 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26423.959674 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19508.138392 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19508.138392 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17712.303055 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17712.303055 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1545,148 +1551,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 139329 # number of writebacks -system.cpu1.dcache.writebacks::total 139329 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18066 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18066 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62670 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62670 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 80736 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 80736 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 80736 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 384000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4805955500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4805955500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5365906500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5365906500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 990469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 990469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857774500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857774500 # 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number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 432946000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92138000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92138000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592646500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592646500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1428500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1428500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4463316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4463316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4896262500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4896262500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 356276500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 356276500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224816500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224816500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 581093000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 581093000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035671 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035671 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028218 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028218 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358195 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358195 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059298 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059298 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.276916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.276916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032263 # 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average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171246.656019 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172234.088156 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 172234.088156 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 1036067 # 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Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.065591 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72771979500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.228366 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975055 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975055 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # 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average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8795.179616 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8795.179616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8795.179616 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1695,461 +1702,457 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1036579 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 1036579 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 1036579 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 1036579 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 1036579 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 1036579 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8661913000 # 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mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102142 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.102142 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.102142 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.249741 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89022.123894 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89022.123894 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 838149 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 838149 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 838149 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 838149 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 838149 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 838149 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6952596500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6952596500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6952596500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6952596500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6952596500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6952596500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15127000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15127000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15127000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15127000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.123983 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.123983 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.123983 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8295.179616 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135062.500000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135062.500000 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 272165 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 272190 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 119402 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 119476 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 68922 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 69326 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15661.573061 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2410564 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 84006 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 28.695141 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 48156 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 37250 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15275.676235 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1897057 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 52360 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 36.231035 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6188.157881 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.165341 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100614 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5579.436781 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2277.975966 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1563.736478 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.377695 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003184 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.340542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.139037 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.095443 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.955907 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1195 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13435 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 525 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5728 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7406 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072937 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820007 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 42699170 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 42699170 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32497 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2653 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 35150 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 139329 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 139329 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2011 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2011 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1071 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1071 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38166 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 38166 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1009291 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 1009291 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131481 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 131481 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 32497 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2653 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1009291 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 169647 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1214088 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 32497 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2653 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1009291 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 169647 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1214088 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 719 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 229 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29485 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29485 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22454 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22454 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35935 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35935 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27288 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 27288 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74058 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 74058 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 719 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 229 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 27288 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 109993 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 138229 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 719 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 229 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 27288 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 109993 # number of overall misses -system.cpu1.l2cache.overall_misses::total 138229 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17830000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4703000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 22533000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 557854000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 557854000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449261000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449261000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 372000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 372000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1407590499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1407590499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1060250500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1060250500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1775396994 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1775396994 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17830000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4703000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1060250500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3182987493 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4265770993 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17830000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4703000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1060250500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3182987493 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4265770993 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33216 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2882 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 36098 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 139329 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 139329 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31496 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31496 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74101 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 74101 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1036579 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 1036579 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205539 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 205539 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33216 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2882 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1036579 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 279640 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1352317 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33216 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2882 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1036579 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 279640 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1352317 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079459 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.026262 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936151 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936151 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.954474 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.954474 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484946 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484946 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026325 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026325 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360311 # 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miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20537.117904 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23768.987342 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18919.925386 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18919.925386 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20008.060925 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20008.060925 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39170.460526 # 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Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 856.871276 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.488165 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001971 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.257194 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132720 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052299 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.932353 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1099 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13920 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 56 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1042 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1993 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11603 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067078 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 33573934 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 33573934 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23345 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2401 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 25746 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 95329 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 95329 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1276 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1276 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 784 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 784 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17759 # 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average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20031.250000 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22447.614108 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19673.396846 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19673.396846 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21310.263695 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21310.263695 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52381.978316 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52381.978316 # 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mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.481060 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026306 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359693 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359693 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101895 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.955980 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.955980 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966366 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966366 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639285 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639285 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015656 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.447882 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.447882 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.105420 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.128088 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 324000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 324000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123009 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 80046 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1329975 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 511761 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1258534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 43565 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76909 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43045 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89356 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 97332 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80052 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1036579 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 560078 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3090316 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1000986 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7189 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70268 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4168759 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66348288 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29828599 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 132864 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 96321279 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1191896 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 3797471 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.302048 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.459146 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 2085429 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1050114 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 105283 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 105064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 32952 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1055933 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 125445 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 933113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 22957 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84915 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 54585 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 838149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 236592 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 39 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2498025 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 734861 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6388 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50317 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3289591 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 53648704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21442516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 96276 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 75198060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 344587 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2379730 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.062577 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.242581 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2650451 69.80% 69.80% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1147020 30.20% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 2231032 93.75% 93.75% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 148479 6.24% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 219 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 3797471 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1487742991 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87115499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2379730 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1153078495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79714518 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1555110854 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 456039835 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1257481819 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 326951344 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4307000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3747000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37064974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 26275944 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30994 # Transaction distribution -system.iobus.trans_dist::ReadResp 30994 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2165,16 +2168,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180832 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2190,11 +2193,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483914 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40103000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2204,7 +2207,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2234,52 +2237,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187482956 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186411762 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36744000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36426 # number of replacements -system.iocache.tags.tagsinuse 1.010803 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 14.472862 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36442 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270452648000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.010803 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.063175 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.063175 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271656669000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904554 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904554 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328140 # Number of tag accesses -system.iocache.tags.data_accesses 328140 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 236 # number of ReadReq misses -system.iocache.ReadReq_misses::total 236 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 236 # number of demand (read+write) misses -system.iocache.demand_misses::total 236 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 236 # number of overall misses -system.iocache.overall_misses::total 236 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30330877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30330877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4273955079 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4273955079 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30330877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30330877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30330877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30330877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 236 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 236 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31866877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31866877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715834885 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715834885 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31866877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31866877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31866877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31866877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 236 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 236 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 236 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 236 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2288,40 +2291,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128520.665254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128520.665254 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128520.665254 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 131139.411523 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131139.411523 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131139.411523 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 236 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 236 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 236 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 236 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 236 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 236 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18530877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18530877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462755079 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2462755079 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18530877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18530877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18530877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18530877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19716877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19716877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904634885 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904634885 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19716877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19716877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19716877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19716877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2330,603 +2333,580 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135428 # number of replacements -system.l2c.tags.tagsinuse 64138.208301 # Cycle average of tags in use -system.l2c.tags.total_refs 442739 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 199807 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.215833 # Average number of references to valid blocks. +system.l2c.tags.replacements 133318 # number of replacements +system.l2c.tags.tagsinuse 64014.997062 # Cycle average of tags in use +system.l2c.tags.total_refs 446453 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 198047 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.254278 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12941.285088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.276334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7274.373268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2166.846690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 24.318023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4022.114049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1496.265741 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4197.799819 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.197468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001057 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12007.955719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 82.059666 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9722.429733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3069.037039 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.516745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1816.838650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 555.114204 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2192.374249 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.183227 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001252 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.110998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.033063 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.487443 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022831 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978671 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29250 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35037 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 144 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23842 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.148353 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046830 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.527338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000145 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.027723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976791 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30866 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33781 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 78 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5648 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25140 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31679 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.446320 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.534622 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5824693 # Number of tag accesses -system.l2c.tags.data_accesses 5824693 # Number of data accesses -system.l2c.Writeback_hits::writebacks 232832 # number of Writeback hits -system.l2c.Writeback_hits::total 232832 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3079 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 930 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4009 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 233 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 92 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 325 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2114 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6136 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 393 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44006 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47229 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 166 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21446 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11079 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8110 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 178893 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51251 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 166 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21446 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8110 # number of demand (read+write) hits -system.l2c.demand_hits::total 185029 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 393 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44006 # number of overall hits -system.l2c.overall_hits::cpu0.data 51251 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46346 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 166 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21446 # number of overall hits -system.l2c.overall_hits::cpu1.data 13193 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 8110 # number of overall hits -system.l2c.overall_hits::total 185029 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8747 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4112 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12859 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 835 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1227 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2062 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10918 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8428 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19346 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 114 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2821 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30623 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.470978 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001251 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.515457 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5802831 # Number of tag accesses +system.l2c.tags.data_accesses 5802831 # Number of data accesses +system.l2c.Writeback_hits::writebacks 230256 # number of Writeback hits +system.l2c.Writeback_hits::total 230256 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3083 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 464 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3547 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 148 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 197 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4599 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 467 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 52086 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 51828 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 50532 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 70 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 10095 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 4893 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3282 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 173352 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 467 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 52086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 56427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 50532 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 70 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10095 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3282 # number of demand (read+write) hits +system.l2c.demand_hits::total 179330 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 467 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits +system.l2c.overall_hits::cpu0.inst 52086 # number of overall hits +system.l2c.overall_hits::cpu0.data 56427 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 50532 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 70 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10095 # number of overall hits +system.l2c.overall_hits::cpu1.data 6272 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3282 # number of overall hits +system.l2c.overall_hits::total 179330 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9481 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2162 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11643 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 497 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1197 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1694 # 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number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19630 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19636 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 129027 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 38 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5812 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 11317 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 8839 # number of demand (read+write) misses -system.l2c.demand_misses::total 194415 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 114 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22412 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20747 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83509.243227 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73328.488115 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823305 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.766491 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.770543 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.858680 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.830799 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.705343 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851991 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.760160 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158155 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245606 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.503900 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.520961 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.520961 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75388.092079 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 74924.144311 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75301.941166 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77293.762575 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76691.311612 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76868.063754 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139178.399491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122081.191736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 132015.385021 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38683 # Transaction distribution -system.membus.trans_dist::ReadResp 213983 # Transaction distribution -system.membus.trans_dist::WriteReq 31171 # Transaction distribution -system.membus.trans_dist::WriteResp 31171 # Transaction distribution -system.membus.trans_dist::Writeback 139589 # Transaction distribution -system.membus.trans_dist::CleanEvict 18226 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78324 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41642 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15039 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 39751 # Transaction distribution -system.membus.trans_dist::ReadExResp 19228 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175300 # Transaction distribution +system.membus.trans_dist::ReadReq 38908 # Transaction distribution +system.membus.trans_dist::ReadResp 215242 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::Writeback 138211 # Transaction distribution +system.membus.trans_dist::CleanEvict 17281 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73717 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40307 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13440 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 39445 # Transaction distribution +system.membus.trans_dist::ReadExResp 18844 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176334 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 805060 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 913962 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 674810 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 796498 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 905407 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19274524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19468214 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19258908 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19450490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21785334 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126049 # Total snoops (count) -system.membus.snoop_fanout::samples 599148 # Request fanout histogram +system.membus.pkt_size::total 21767610 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121785 # Total snoops (count) +system.membus.snoop_fanout::samples 591590 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 599148 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 591590 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 599148 # Request fanout histogram -system.membus.reqLayer0.occupancy 91414000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 591590 # Request fanout histogram +system.membus.reqLayer0.occupancy 91392000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12977999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11844500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1005422091 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1004304747 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1166590180 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1168943229 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64371509 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64602498 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2969,46 +2949,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 38687 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 518927 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372432 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 99547 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 82215 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41967 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 124182 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51561 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51561 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 480255 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 982687 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 493902 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 158313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 22110 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 21385 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 725 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 38912 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 507516 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 368484 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 106099 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77161 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40652 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 117813 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51062 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51062 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 468619 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1133004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 361504 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1494508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32818575 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6820071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39638646 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 465665 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1285667 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.162057 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.368503 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1216476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 257070 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1473546 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35115318 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4064004 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39179322 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 452154 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1258731 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.293892 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.456806 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1077316 83.79% 83.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 208351 16.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 889525 70.67% 70.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 368481 29.27% 99.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 725 0.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1285667 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 860205550 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1258731 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 836264644 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 331500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 646726661 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 685711951 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 269148617 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 211221475 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 954a8904e..481a34a0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852655 # Number of seconds simulated -sim_ticks 2852654988500 # Number of ticks simulated -final_tick 2852654988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858301 # Number of seconds simulated +sim_ticks 2858301146500 # Number of ticks simulated +final_tick 2858301146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116178 # Simulator instruction rate (inst/s) -host_op_rate 140471 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2957977243 # Simulator tick rate (ticks/s) -host_mem_usage 618900 # Number of bytes of host memory used -host_seconds 964.39 # Real time elapsed on the host -sim_insts 112040950 # Number of instructions simulated -sim_ops 135468925 # Number of ops (including micro ops) simulated +host_inst_rate 158663 # Simulator instruction rate (inst/s) +host_op_rate 191838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4049033168 # Simulator tick rate (ticks/s) +host_mem_usage 629392 # Number of bytes of host memory used +host_seconds 705.92 # Real time elapsed on the host +sim_insts 112003872 # Number of instructions simulated +sim_ops 135422492 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1669952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9187372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1692928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9156716 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10866412 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1669952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1669952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7981376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10858604 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1692928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1692928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7945984 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7998900 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7963508 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 124 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143595 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170309 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124709 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170187 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124156 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129090 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2827 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2776 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 585403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3220639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3809228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2797876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2804019 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2797876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 592285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3203552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3798971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 592285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 592285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2779967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6131 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2786098 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2779967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2776 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3226782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6613247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170309 # Number of read requests accepted -system.physmem.writeReqs 129090 # Number of write requests accepted -system.physmem.readBursts 170309 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129090 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10890880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 8010944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10866412 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7998900 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40828 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10905 # Per bank write bursts -system.physmem.perBankRdBursts::1 10842 # Per bank write bursts -system.physmem.perBankRdBursts::2 10713 # Per bank write bursts -system.physmem.perBankRdBursts::3 10735 # Per bank write bursts -system.physmem.perBankRdBursts::4 13349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10818 # Per bank write bursts -system.physmem.perBankRdBursts::6 11158 # Per bank write bursts -system.physmem.perBankRdBursts::7 10982 # Per bank write bursts -system.physmem.perBankRdBursts::8 10119 # Per bank write bursts -system.physmem.perBankRdBursts::9 10274 # Per bank write bursts -system.physmem.perBankRdBursts::10 10247 # Per bank write bursts -system.physmem.perBankRdBursts::11 9187 # Per bank write bursts -system.physmem.perBankRdBursts::12 10322 # Per bank write bursts -system.physmem.perBankRdBursts::13 10753 # Per bank write bursts -system.physmem.perBankRdBursts::14 10041 # Per bank write bursts -system.physmem.perBankRdBursts::15 9725 # Per bank write bursts -system.physmem.perBankWrBursts::0 8109 # Per bank write bursts -system.physmem.perBankWrBursts::1 8208 # Per bank write bursts -system.physmem.perBankWrBursts::2 8370 # Per bank write bursts -system.physmem.perBankWrBursts::3 8304 # Per bank write bursts -system.physmem.perBankWrBursts::4 7540 # Per bank write bursts -system.physmem.perBankWrBursts::5 7865 # Per bank write bursts -system.physmem.perBankWrBursts::6 8185 # Per bank write bursts -system.physmem.perBankWrBursts::7 8104 # Per bank write bursts -system.physmem.perBankWrBursts::8 7740 # Per bank write bursts -system.physmem.perBankWrBursts::9 7807 # Per bank write bursts -system.physmem.perBankWrBursts::10 7671 # Per bank write bursts -system.physmem.perBankWrBursts::11 7052 # Per bank write bursts -system.physmem.perBankWrBursts::12 7765 # Per bank write bursts -system.physmem.perBankWrBursts::13 7977 # Per bank write bursts -system.physmem.perBankWrBursts::14 7383 # Per bank write bursts -system.physmem.perBankWrBursts::15 7091 # Per bank write bursts +system.physmem.bw_total::cpu.inst 592285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3209683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6585070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170187 # Number of read requests accepted +system.physmem.writeReqs 128537 # Number of write requests accepted +system.physmem.readBursts 170187 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128537 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10884288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 7975936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10858604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7963508 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40806 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10600 # Per bank write bursts +system.physmem.perBankRdBursts::1 10887 # Per bank write bursts +system.physmem.perBankRdBursts::2 11108 # Per bank write bursts +system.physmem.perBankRdBursts::3 10980 # Per bank write bursts +system.physmem.perBankRdBursts::4 13553 # Per bank write bursts +system.physmem.perBankRdBursts::5 10410 # Per bank write bursts +system.physmem.perBankRdBursts::6 10585 # Per bank write bursts +system.physmem.perBankRdBursts::7 10816 # Per bank write bursts +system.physmem.perBankRdBursts::8 10327 # Per bank write bursts +system.physmem.perBankRdBursts::9 10604 # Per bank write bursts +system.physmem.perBankRdBursts::10 9912 # Per bank write bursts +system.physmem.perBankRdBursts::11 9123 # Per bank write bursts +system.physmem.perBankRdBursts::12 10363 # Per bank write bursts +system.physmem.perBankRdBursts::13 10770 # Per bank write bursts +system.physmem.perBankRdBursts::14 10067 # Per bank write bursts +system.physmem.perBankRdBursts::15 9962 # Per bank write bursts +system.physmem.perBankWrBursts::0 7842 # Per bank write bursts +system.physmem.perBankWrBursts::1 8249 # Per bank write bursts +system.physmem.perBankWrBursts::2 8721 # Per bank write bursts +system.physmem.perBankWrBursts::3 8464 # Per bank write bursts +system.physmem.perBankWrBursts::4 7420 # Per bank write bursts +system.physmem.perBankWrBursts::5 7583 # Per bank write bursts +system.physmem.perBankWrBursts::6 7625 # Per bank write bursts +system.physmem.perBankWrBursts::7 7909 # Per bank write bursts +system.physmem.perBankWrBursts::8 7872 # Per bank write bursts +system.physmem.perBankWrBursts::9 8104 # Per bank write bursts +system.physmem.perBankWrBursts::10 7451 # Per bank write bursts +system.physmem.perBankWrBursts::11 6976 # Per bank write bursts +system.physmem.perBankWrBursts::12 7788 # Per bank write bursts +system.physmem.perBankWrBursts::13 7975 # Per bank write bursts +system.physmem.perBankWrBursts::14 7387 # Per bank write bursts +system.physmem.perBankWrBursts::15 7258 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2852654585000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.totGap 2858300743000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169752 # Read request sizes (log2) +system.physmem.readPktSize::6 169630 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124709 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124156 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.442553 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.035683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.553660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22186 36.56% 36.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14675 24.18% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6464 10.65% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3592 5.92% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2485 4.09% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.75% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1111 1.83% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1120 1.85% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7387 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60691 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6290 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.051669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 539.627643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6288 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6290 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6290 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.900000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.361154 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.375647 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5497 87.39% 87.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 61 0.97% 88.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 183 2.91% 91.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.73% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 63 1.00% 93.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 171 2.72% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.30% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.13% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.16% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.16% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 171 2.72% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.24% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6290 # Writes before turning the bus around for reads -system.physmem.totQLat 1692148250 # Total ticks spent queuing -system.physmem.totMemAccLat 4882835750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850850000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9943.87 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.136640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.409953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.199512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22530 36.57% 36.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14842 24.09% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6878 11.16% 71.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3579 5.81% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2575 4.18% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2036 3.30% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1091 1.77% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1049 1.70% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7027 11.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61607 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.410058 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.248357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.087685 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.454852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.723718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5415 87.28% 87.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 82 1.32% 88.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 29 0.47% 89.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 170 2.74% 91.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 36 0.58% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 140 2.26% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.82% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.15% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.42% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.27% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.13% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 160 2.58% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.03% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.32% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.13% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads +system.physmem.totQLat 1827154250 # Total ticks spent queuing +system.physmem.totMemAccLat 5015910500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10743.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28693.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29493.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 140376 # Number of row buffer hits during reads -system.physmem.writeRowHits 94273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes -system.physmem.avgGap 9527936.25 # Average gap between requests -system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240143400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131030625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698115600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419158800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83459244105 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638379332000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909648151730 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.429846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725453951250 # Time in different power states -system.physmem_0.memoryStateTime::REF 95256200000 # Time in different power states +system.physmem.avgWrQLen 26.50 # Average write queue length when enqueuing +system.physmem.readRowHits 139389 # Number of row buffer hits during reads +system.physmem.writeRowHits 93694 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.17 # Row buffer hit rate for writes +system.physmem.avgGap 9568366.60 # Average gap between requests +system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240959880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131476125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 693724200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 413508240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86986692810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638672097500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913828291955 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.570205 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725916009250 # Time in different power states +system.physmem_0.memoryStateTime::REF 95444700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31938521250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36932994500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218680560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119319750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 629202600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 391949280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82079606700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639589540250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909349426340 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.325127 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727485699500 # Time in different power states -system.physmem_1.memoryStateTime::REF 95256200000 # Time in different power states +system.physmem_1.actEnergy 224789040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122652750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632790600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 394055280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85302372735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640149571250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913516064855 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.460970 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728391286000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95444700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29912992000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34465013500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -331,15 +331,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31017301 # Number of BP lookups -system.cpu.branchPred.condPredicted 16826801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2510748 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18518050 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13329905 # Number of BTB hits +system.cpu.branchPred.lookups 31040865 # Number of BP lookups +system.cpu.branchPred.condPredicted 16831531 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2506988 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18486474 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13317466 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.983308 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7858653 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1517345 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.038973 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7868005 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1514854 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -370,57 +370,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 65935 # Table walker walks requested -system.cpu.dtb.walker.walksShort 65935 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43131 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22804 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 65935 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 65935 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 65935 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7817 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11967.954458 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9949.329384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7404.205030 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6115 78.23% 78.23% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.70% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7817 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 260813000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 260813000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 260813000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6422 82.15% 82.15% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1395 17.85% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7817 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65935 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 66489 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66489 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43580 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22909 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66489 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66489 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66489 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7766 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8498.851872 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7759 99.91% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7766 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 513949000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 513949000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 513949000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6383 82.19% 82.19% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1383 17.81% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7766 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66489 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65935 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7817 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66489 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7766 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7817 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73752 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7766 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74255 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24760096 # DTB read hits -system.cpu.dtb.read_misses 58949 # DTB read misses -system.cpu.dtb.write_hits 19444061 # DTB write hits -system.cpu.dtb.write_misses 6986 # DTB write misses +system.cpu.dtb.read_hits 24754555 # DTB read hits +system.cpu.dtb.read_misses 59253 # DTB read misses +system.cpu.dtb.write_hits 19441053 # DTB write hits +system.cpu.dtb.write_misses 7236 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1337 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1780 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1795 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24819045 # DTB read accesses -system.cpu.dtb.write_accesses 19451047 # DTB write accesses +system.cpu.dtb.perms_faults 764 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24813808 # DTB read accesses +system.cpu.dtb.write_accesses 19448289 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44204157 # DTB hits -system.cpu.dtb.misses 65935 # DTB misses -system.cpu.dtb.accesses 44270092 # DTB accesses +system.cpu.dtb.hits 44195608 # DTB hits +system.cpu.dtb.misses 66489 # DTB misses +system.cpu.dtb.accesses 44262097 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,37 +448,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5452 # Table walker walks requested -system.cpu.itb.walker.walksShort 5452 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 318 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5134 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5452 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5452 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5452 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12119.032663 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10076.122020 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7085.501487 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1309 41.11% 41.11% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1160 36.43% 77.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 714 22.42% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 260408500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 260408500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 260408500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated +system.cpu.itb.walker.walks 5448 # Table walker walks requested +system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5128 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3191 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12717.173300 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7372.723577 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2455 76.94% 76.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 735 23.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3191 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 513294500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 513294500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 513294500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2881 90.29% 90.29% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3191 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5452 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5452 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8636 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57598025 # ITB inst hits -system.cpu.itb.inst_misses 5452 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3191 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3191 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8639 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57598121 # ITB inst hits +system.cpu.itb.inst_misses 5448 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -489,274 +486,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2979 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8499 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57603477 # ITB inst accesses -system.cpu.itb.hits 57598025 # DTB hits -system.cpu.itb.misses 5452 # DTB misses -system.cpu.itb.accesses 57603477 # DTB accesses -system.cpu.numCycles 315393196 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57603569 # ITB inst accesses +system.cpu.itb.hits 57598121 # DTB hits +system.cpu.itb.misses 5448 # DTB misses +system.cpu.itb.accesses 57603569 # DTB accesses +system.cpu.numCycles 332010047 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112040950 # Number of instructions committed -system.cpu.committedOps 135468925 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7774524 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5389977386 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.814981 # CPI: cycles per instruction -system.cpu.ipc 0.355242 # IPC: instructions per cycle +system.cpu.committedInsts 112003872 # Number of instructions committed +system.cpu.committedOps 135422492 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7777324 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5384653012 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.964273 # CPI: cycles per instruction +system.cpu.ipc 0.337351 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 227419103 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87974093 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 843754 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.948230 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42602633 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844266 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.461150 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 310642500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.948230 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999899 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999899 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed +system.cpu.tickCycles 227998615 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104011432 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 840949 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.900791 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42597434 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 841461 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.623183 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 590729500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.900791 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999806 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176183318 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176183318 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23061882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23061882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18277764 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18277764 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356325 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356325 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443565 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443565 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460145 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460145 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41339646 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41339646 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41695971 # number of overall hits -system.cpu.dcache.overall_hits::total 41695971 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41679.761909 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41679.761909 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13291.865105 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13291.865105 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13297.958936 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13297.958936 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016863 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016863 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019488 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60485733 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60485733 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54692690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54692690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54692690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54692690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54692690 # number of overall hits -system.cpu.icache.overall_hits::total 54692690 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771487500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9970657500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001704 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982099 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15499639000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15499639000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2776629500 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2776629500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17219713500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20012077500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 396548000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5548169500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5944717500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4470099000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4470099000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 396548000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10018268500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10414816500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983087 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983087 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007911 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025892 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025892 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044202 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044202 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79488.188976 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20759.649750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.649750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007928 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025735 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025735 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125876 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67456.611240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67456.611240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69598.153886 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69598.153886 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73111.690141 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73111.690141 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177330.088666 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166645.327661 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154136.841533 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154136.841533 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.675121 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.653581 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 133644 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578737 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 7509435 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770131 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 575 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 134592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3578420 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 823959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2990642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 822692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2989768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2779 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2851 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295864 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295864 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2896522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 548664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295719 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295719 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 545999 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8644384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2648037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158879 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11466298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185580160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98978397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284856765 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194832 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7814541 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.034451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.182385 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2639755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15227 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161605 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11465064 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185683904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98756893 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18604 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288828 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284748229 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192861 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7812074 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018867 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.136054 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7545321 96.55% 96.55% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 269220 3.45% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7664687 98.11% 98.11% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 147387 1.89% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7814541 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4535355500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7812074 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4533598000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 377377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4349852430 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4352382759 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312899273 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1308632806 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10586000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10576000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89410974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1250,7 +1253,7 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187477706 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186368011 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1259,14 +1262,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.030922 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036757 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270445541000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.030922 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064433 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064433 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274667845000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036757 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1280,14 +1283,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29161877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29161877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4273547829 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4273547829 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29161877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29161877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29161877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29161877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29104877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29104877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697807134 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697807134 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29104877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29104877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29104877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29104877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1304,19 +1307,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124623.405983 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117975.591569 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117975.591569 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124623.405983 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124623.405983 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124379.816239 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124379.816239 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124379.816239 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1330,14 +1333,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17461877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17461877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462347829 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2462347829 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17461877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17461877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17461877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17461877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17404877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17404877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886607134 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886607134 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17404877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17404877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17404877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17404877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1346,68 +1349,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67975.591569 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67975.591569 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34319 # Transaction distribution -system.membus.trans_dist::ReadResp 71793 # Transaction distribution +system.membus.trans_dist::ReadReq 34618 # Transaction distribution +system.membus.trans_dist::ReadResp 71995 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124709 # Transaction distribution -system.membus.trans_dist::CleanEvict 8498 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution +system.membus.trans_dist::Writeback 124156 # Transaction distribution +system.membus.trans_dist::CleanEvict 8653 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4582 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution -system.membus.trans_dist::ReadExReq 129599 # Transaction distribution -system.membus.trans_dist::ReadExResp 129599 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37474 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4584 # Transaction distribution +system.membus.trans_dist::ReadExReq 129275 # Transaction distribution +system.membus.trans_dist::ReadExResp 129275 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37377 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 563411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455163 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562725 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 672311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671625 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16548192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16711965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668765 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19029085 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18985885 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 403242 # Request fanout histogram +system.membus.snoop_fanout::samples 402707 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 403242 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402707 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 403242 # Request fanout histogram -system.membus.reqLayer0.occupancy 87534500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402707 # Request fanout histogram +system.membus.reqLayer0.occupancy 87547000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 881620222 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 878616291 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999181641 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 998538415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64440498 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64594078 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 7bba59de9..51e8b32a5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827546 # Number of seconds simulated -sim_ticks 2827546300000 # Number of ticks simulated -final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832619 # Number of seconds simulated +sim_ticks 2832618668500 # Number of ticks simulated +final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77731 # Simulator instruction rate (inst/s) -host_op_rate 94287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1943054038 # Simulator tick rate (ticks/s) -host_mem_usage 577104 # Number of bytes of host memory used -host_seconds 1455.21 # Real time elapsed on the host -sim_insts 113115023 # Number of instructions simulated -sim_ops 137206411 # Number of ops (including micro ops) simulated +host_inst_rate 65632 # Simulator instruction rate (inst/s) +host_op_rate 79607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1643300725 # Simulator tick rate (ticks/s) +host_mem_usage 630388 # Number of bytes of host memory used +host_seconds 1723.74 # Real time elapsed on the host +sim_insts 113133035 # Number of instructions simulated +sim_ops 137220830 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory +system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176040 # Number of read requests accepted -system.physmem.writeReqs 135452 # Number of write requests accepted -system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue -system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11283 # Per bank write bursts -system.physmem.perBankRdBursts::1 10909 # Per bank write bursts -system.physmem.perBankRdBursts::2 10879 # Per bank write bursts -system.physmem.perBankRdBursts::3 10544 # Per bank write bursts -system.physmem.perBankRdBursts::4 14049 # Per bank write bursts -system.physmem.perBankRdBursts::5 11359 # Per bank write bursts -system.physmem.perBankRdBursts::6 11255 # Per bank write bursts -system.physmem.perBankRdBursts::7 11497 # Per bank write bursts -system.physmem.perBankRdBursts::8 10572 # Per bank write bursts -system.physmem.perBankRdBursts::9 11295 # Per bank write bursts -system.physmem.perBankRdBursts::10 10218 # Per bank write bursts -system.physmem.perBankRdBursts::11 9589 # Per bank write bursts -system.physmem.perBankRdBursts::12 9979 # Per bank write bursts -system.physmem.perBankRdBursts::13 10701 # Per bank write bursts -system.physmem.perBankRdBursts::14 10842 # Per bank write bursts -system.physmem.perBankRdBursts::15 10903 # Per bank write bursts -system.physmem.perBankWrBursts::0 8346 # Per bank write bursts -system.physmem.perBankWrBursts::1 8306 # Per bank write bursts -system.physmem.perBankWrBursts::2 8514 # Per bank write bursts -system.physmem.perBankWrBursts::3 8219 # Per bank write bursts -system.physmem.perBankWrBursts::4 8602 # Per bank write bursts -system.physmem.perBankWrBursts::5 8561 # Per bank write bursts -system.physmem.perBankWrBursts::6 8053 # Per bank write bursts -system.physmem.perBankWrBursts::7 8529 # Per bank write bursts -system.physmem.perBankWrBursts::8 8073 # Per bank write bursts -system.physmem.perBankWrBursts::9 8804 # Per bank write bursts -system.physmem.perBankWrBursts::10 7852 # Per bank write bursts -system.physmem.perBankWrBursts::11 7407 # Per bank write bursts -system.physmem.perBankWrBursts::12 7747 # Per bank write bursts -system.physmem.perBankWrBursts::13 8181 # Per bank write bursts -system.physmem.perBankWrBursts::14 8268 # Per bank write bursts -system.physmem.perBankWrBursts::15 8079 # Per bank write bursts +system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170127 # Number of read requests accepted +system.physmem.writeReqs 129798 # Number of write requests accepted +system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11277 # Per bank write bursts +system.physmem.perBankRdBursts::1 10595 # Per bank write bursts +system.physmem.perBankRdBursts::2 11086 # Per bank write bursts +system.physmem.perBankRdBursts::3 11282 # Per bank write bursts +system.physmem.perBankRdBursts::4 12957 # Per bank write bursts +system.physmem.perBankRdBursts::5 9975 # Per bank write bursts +system.physmem.perBankRdBursts::6 10510 # Per bank write bursts +system.physmem.perBankRdBursts::7 10855 # Per bank write bursts +system.physmem.perBankRdBursts::8 10363 # Per bank write bursts +system.physmem.perBankRdBursts::9 10082 # Per bank write bursts +system.physmem.perBankRdBursts::10 10269 # Per bank write bursts +system.physmem.perBankRdBursts::11 9303 # Per bank write bursts +system.physmem.perBankRdBursts::12 9940 # Per bank write bursts +system.physmem.perBankRdBursts::13 11053 # Per bank write bursts +system.physmem.perBankRdBursts::14 10302 # Per bank write bursts +system.physmem.perBankRdBursts::15 10142 # Per bank write bursts +system.physmem.perBankWrBursts::0 8501 # Per bank write bursts +system.physmem.perBankWrBursts::1 7938 # Per bank write bursts +system.physmem.perBankWrBursts::2 8637 # Per bank write bursts +system.physmem.perBankWrBursts::3 8770 # Per bank write bursts +system.physmem.perBankWrBursts::4 7610 # Per bank write bursts +system.physmem.perBankWrBursts::5 7376 # Per bank write bursts +system.physmem.perBankWrBursts::6 7709 # Per bank write bursts +system.physmem.perBankWrBursts::7 8071 # Per bank write bursts +system.physmem.perBankWrBursts::8 7782 # Per bank write bursts +system.physmem.perBankWrBursts::9 7594 # Per bank write bursts +system.physmem.perBankWrBursts::10 7680 # Per bank write bursts +system.physmem.perBankWrBursts::11 6982 # Per bank write bursts +system.physmem.perBankWrBursts::12 7590 # Per bank write bursts +system.physmem.perBankWrBursts::13 8396 # Per bank write bursts +system.physmem.perBankWrBursts::14 7757 # Per bank write bursts +system.physmem.perBankWrBursts::15 7487 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2827546089000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2832618457500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2997 # Read request sizes (log2) +system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172487 # Read request sizes (log2) +system.physmem.readPktSize::6 166575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131071 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125417 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,156 +159,155 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads -system.physmem.totQLat 2123501000 # Total ticks spent queuing -system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads +system.physmem.totQLat 2109686750 # Total ticks spent queuing +system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 144861 # Number of row buffer hits during reads -system.physmem.writeRowHits 97354 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 9077427.64 # Average gap between requests -system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.382186 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states -system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing +system.physmem.readRowHits 139766 # Number of row buffer hits during reads +system.physmem.writeRowHits 93986 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes +system.physmem.avgGap 9444422.63 # Average gap between requests +system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.462100 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states +system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.301228 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states -system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states +system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.364017 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states +system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -328,15 +327,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46902830 # Number of BP lookups -system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits +system.cpu.branchPred.lookups 46909632 # Number of BP lookups +system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -367,45 +366,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9925 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9925 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9925 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9925 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9925 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 227240000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 227240000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 227240000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6352 81.85% 81.85% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1409 18.15% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7761 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9925 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9696 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9696 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9696 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9696 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9696 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6227 82.67% 82.67% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1305 17.33% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7532 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9696 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9925 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7761 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9696 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7532 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7761 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17686 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7532 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17228 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24580805 # DTB read hits -system.cpu.checker.dtb.read_misses 8471 # DTB read misses -system.cpu.checker.dtb.write_hits 19633932 # DTB write hits -system.cpu.checker.dtb.write_misses 1454 # DTB write misses +system.cpu.checker.dtb.read_hits 24584215 # DTB read hits +system.cpu.checker.dtb.read_misses 8281 # DTB read misses +system.cpu.checker.dtb.write_hits 19636610 # DTB write hits +system.cpu.checker.dtb.write_misses 1415 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1778 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24589276 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19635386 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24592496 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19638025 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44214737 # DTB hits -system.cpu.checker.dtb.misses 9925 # DTB misses -system.cpu.checker.dtb.accesses 44224662 # DTB accesses +system.cpu.checker.dtb.hits 44220825 # DTB hits +system.cpu.checker.dtb.misses 9696 # DTB misses +system.cpu.checker.dtb.accesses 44230521 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -435,26 +434,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 4826 # Table walker walks requested -system.cpu.checker.itb.walker.walksShort 4826 # Table walker walks initiated with short descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 226829000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 226829000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 226829000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested +system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4826 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4826 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115815180 # ITB inst hits -system.cpu.checker.itb.inst_misses 4826 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 115833137 # ITB inst hits +system.cpu.checker.itb.inst_misses 4825 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -463,18 +462,18 @@ system.cpu.checker.itb.flush_tlb 128 # Nu system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2977 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115820006 # ITB inst accesses -system.cpu.checker.itb.hits 115815180 # DTB hits -system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115820006 # DTB accesses -system.cpu.checker.numCycles 139058612 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 115837962 # ITB inst accesses +system.cpu.checker.itb.hits 115833137 # DTB hits +system.cpu.checker.itb.misses 4825 # DTB misses +system.cpu.checker.itb.accesses 115837962 # DTB accesses +system.cpu.checker.numCycles 139072975 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -506,86 +505,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 72877 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walks 71741 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25454298 # DTB read hits -system.cpu.dtb.read_misses 62609 # DTB read misses -system.cpu.dtb.write_hits 19910353 # DTB write hits -system.cpu.dtb.write_misses 10268 # DTB write misses +system.cpu.dtb.read_hits 25458814 # DTB read hits +system.cpu.dtb.read_misses 61805 # DTB read misses +system.cpu.dtb.write_hits 19912938 # DTB write hits +system.cpu.dtb.write_misses 9936 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25516907 # DTB read accesses -system.cpu.dtb.write_accesses 19920621 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25520619 # DTB read accesses +system.cpu.dtb.write_accesses 19922874 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45364651 # DTB hits -system.cpu.dtb.misses 72877 # DTB misses -system.cpu.dtb.accesses 45437528 # DTB accesses +system.cpu.dtb.hits 45371752 # DTB hits +system.cpu.dtb.misses 71741 # DTB misses +system.cpu.dtb.accesses 45443493 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -615,56 +607,54 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11947 # Table walker walks requested -system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walks 11944 # Table walker walks requested +system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66251443 # ITB inst hits -system.cpu.itb.inst_misses 11947 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66274552 # ITB inst hits +system.cpu.itb.inst_misses 11944 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -673,143 +663,143 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66263390 # ITB inst accesses -system.cpu.itb.hits 66251443 # DTB hits -system.cpu.itb.misses 11947 # DTB misses -system.cpu.itb.accesses 66263390 # DTB accesses -system.cpu.numCycles 263015768 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66286496 # ITB inst accesses +system.cpu.itb.hits 66274552 # DTB hits +system.cpu.itb.misses 11944 # DTB misses +system.cpu.itb.accesses 66286496 # DTB accesses +system.cpu.numCycles 277645869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -833,101 +823,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued -system.cpu.iq.rate 0.544767 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued +system.cpu.iq.rate 0.516124 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 201061 # number of nop insts executed -system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed -system.cpu.iew.exec_branches 26517785 # Number of branches executed -system.cpu.iew.exec_stores 20872797 # Number of stores executed -system.cpu.iew.exec_rate 0.541174 # Inst execution rate -system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63256602 # num instructions producing a value -system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value +system.cpu.iew.exec_nop 200573 # number of nop insts executed +system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed +system.cpu.iew.exec_branches 26519669 # Number of branches executed +system.cpu.iew.exec_stores 20875979 # Number of stores executed +system.cpu.iew.exec_rate 0.512728 # Inst execution rate +system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271886 # num instructions producing a value +system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113269928 # Number of instructions committed -system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113287940 # Number of instructions committed +system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45498874 # Number of memory references committed -system.cpu.commit.loads 24907631 # Number of loads committed -system.cpu.commit.membars 814016 # Number of memory barriers committed -system.cpu.commit.branches 26032948 # Number of branches committed -system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120189151 # Number of committed integer instructions. -system.cpu.commit.function_calls 4888294 # Number of function calls committed. +system.cpu.commit.refs 45505753 # Number of memory references committed +system.cpu.commit.loads 24911268 # Number of loads committed +system.cpu.commit.membars 814898 # Number of memory barriers committed +system.cpu.commit.branches 26034583 # Number of branches committed +system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. +system.cpu.commit.function_calls 4887749 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -951,501 +941,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction -system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 375595727 # The number of ROB reads -system.cpu.rob.rob_writes 292884314 # The number of ROB writes -system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113115023 # Number of Instructions Simulated -system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads -system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155781292 # number of integer regfile reads -system.cpu.int_regfile_writes 88602574 # number of integer regfile writes -system.cpu.fp_regfile_reads 9590 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction +system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 388465780 # The number of ROB reads +system.cpu.rob.rob_writes 292930075 # The number of ROB writes +system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113133035 # Number of Instructions Simulated +system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads +system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155797969 # number of integer regfile reads +system.cpu.int_regfile_writes 88612712 # number of integer regfile writes +system.cpu.fp_regfile_reads 9524 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502823667 # number of cc regfile reads -system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes -system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads -system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes -system.cpu.dcache.tags.replacements 839265 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502896978 # number of cc regfile reads +system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes +system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes +system.cpu.dcache.tags.replacements 840044 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # 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number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179336842 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179336842 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23308523 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23308523 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15546666 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15546666 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346021 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346021 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441431 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441431 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460353 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460353 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38855189 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19153654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19153654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523886 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523886 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468819 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468819 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460358 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460358 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43171002 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43171002 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43694888 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43694888 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029513 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029513 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188319 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188319 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339511 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339511 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058419 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058419 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.099970 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099970 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102842 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102842 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55600 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55600 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56560.132743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54321.416927 # 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number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414292 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 715207 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715207 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834878 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834878 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6403711500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19964415469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19964415469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1698297000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1698297000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126773500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126773500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 273000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 273000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26368126969 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26368126969 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019107 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1891955 # number of replacements -system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1889050 # number of replacements +system.cpu.icache.tags.tagsinuse 511.157898 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64290369 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1889562 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.023953 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16212707500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.157898 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998355 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998355 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits -system.cpu.icache.overall_hits::total 64263909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses -system.cpu.icache.overall_misses::total 1984699 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17897474000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20340953500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340103000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5546780500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5886883500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4471146500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4471146500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340103000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10017927000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10358030000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000465 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987277 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987277 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024466 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024466 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 201613 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194580 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::ReadReq 30172 # Transaction distribution +system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1657,9 +1653,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1682,9 +1678,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1725,52 +1721,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use +system.iocache.tags.replacements 36413 # number of replacements +system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses +system.iocache.tags.tag_accesses 328023 # Number of tag accesses +system.iocache.tags.data_accesses 328023 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses +system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses -system.iocache.demand_misses::total 233 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 233 # number of overall misses -system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses +system.iocache.demand_misses::total 223 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 223 # number of overall misses +system.iocache.overall_misses::total 223 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1779,14 +1775,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1797,22 +1793,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1821,68 +1817,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 68549 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131071 # Transaction distribution -system.membus.trans_dist::CleanEvict 8154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution -system.membus.trans_dist::ReadExReq 138564 # Transaction distribution -system.membus.trans_dist::ReadExResp 138564 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution +system.membus.trans_dist::ReadReq 34133 # Transaction distribution +system.membus.trans_dist::ReadResp 67584 # Transaction distribution +system.membus.trans_dist::WriteReq 27585 # Transaction distribution +system.membus.trans_dist::WriteResp 27585 # Transaction distribution +system.membus.trans_dist::Writeback 125417 # Transaction distribution +system.membus.trans_dist::CleanEvict 7628 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution +system.membus.trans_dist::ReadExReq 133608 # Transaction distribution +system.membus.trans_dist::ReadExResp 133608 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 414951 # Request fanout histogram +system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 487 # Total snoops (count) +system.membus.snoop_fanout::samples 402837 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 414951 # Request fanout histogram -system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402837 # Request fanout histogram +system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1915,17 +1911,17 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 923e006af..79173486d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825406 # Number of seconds simulated -sim_ticks 2825405893500 # Number of ticks simulated -final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.627261 # Number of seconds simulated +sim_ticks 2627260787000 # Number of ticks simulated +final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67919 # Simulator instruction rate (inst/s) -host_op_rate 82398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1596954995 # Simulator tick rate (ticks/s) -host_mem_usage 650656 # Number of bytes of host memory used -host_seconds 1769.25 # Real time elapsed on the host -sim_insts 120165205 # Number of instructions simulated -sim_ops 145782922 # Number of ops (including micro ops) simulated +host_inst_rate 87166 # Simulator instruction rate (inst/s) +host_op_rate 105753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1901847747 # Simulator tick rate (ticks/s) +host_mem_usage 660800 # Number of bytes of host memory used +host_seconds 1381.43 # Real time elapsed on the host +sim_insts 120413300 # Number of instructions simulated +sim_ops 146090184 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1275648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1290856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1139008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1190376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8167488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 182944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 606480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 427776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 326368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 665684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 594880 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12214872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1275648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 182944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1458592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8756928 # Number of bytes written to this memory +system.physmem.bytes_read::total 12087580 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1139008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 326368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1465376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8694784 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8774492 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20690 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8712348 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 127617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9496 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6684 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9295 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193712 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136827 # Number of write requests responded to by this memory +system.physmem.num_reads::total 191724 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135856 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141218 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 451492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 456875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2982855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 151403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4323227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 451492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3099352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3105569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3099352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 451492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 463077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2982855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 151403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7428796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193713 # Number of read requests accepted -system.physmem.writeReqs 141218 # Number of write requests accepted -system.physmem.readBursts 193713 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12387136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue -system.physmem.bytesWritten 8786752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12214936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8774492 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 140247 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 433534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 453086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3108747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 253376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 226426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4600830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 433534 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3309448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6670 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3316134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3309448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 433534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 459756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3108747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 253391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 226426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7916964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 191724 # Number of read requests accepted +system.physmem.writeReqs 140247 # Number of write requests accepted +system.physmem.readBursts 191724 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140247 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12260288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 8725248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12087580 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8712348 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49946 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12421 # Per bank write bursts -system.physmem.perBankRdBursts::1 11965 # Per bank write bursts -system.physmem.perBankRdBursts::2 12291 # Per bank write bursts -system.physmem.perBankRdBursts::3 13088 # Per bank write bursts -system.physmem.perBankRdBursts::4 14558 # Per bank write bursts -system.physmem.perBankRdBursts::5 12211 # Per bank write bursts -system.physmem.perBankRdBursts::6 11940 # Per bank write bursts -system.physmem.perBankRdBursts::7 12041 # Per bank write bursts -system.physmem.perBankRdBursts::8 12092 # Per bank write bursts -system.physmem.perBankRdBursts::9 12171 # Per bank write bursts -system.physmem.perBankRdBursts::10 11769 # Per bank write bursts -system.physmem.perBankRdBursts::11 10768 # Per bank write bursts -system.physmem.perBankRdBursts::12 11340 # Per bank write bursts -system.physmem.perBankRdBursts::13 12292 # Per bank write bursts -system.physmem.perBankRdBursts::14 11321 # Per bank write bursts -system.physmem.perBankRdBursts::15 11281 # Per bank write bursts -system.physmem.perBankWrBursts::0 9078 # Per bank write bursts -system.physmem.perBankWrBursts::1 8838 # Per bank write bursts -system.physmem.perBankWrBursts::2 9120 # Per bank write bursts -system.physmem.perBankWrBursts::3 9597 # Per bank write bursts -system.physmem.perBankWrBursts::4 8379 # Per bank write bursts -system.physmem.perBankWrBursts::5 8806 # Per bank write bursts -system.physmem.perBankWrBursts::6 8536 # Per bank write bursts -system.physmem.perBankWrBursts::7 8489 # Per bank write bursts -system.physmem.perBankWrBursts::8 8658 # Per bank write bursts -system.physmem.perBankWrBursts::9 8679 # Per bank write bursts -system.physmem.perBankWrBursts::10 8573 # Per bank write bursts -system.physmem.perBankWrBursts::11 8021 # Per bank write bursts -system.physmem.perBankWrBursts::12 8348 # Per bank write bursts -system.physmem.perBankWrBursts::13 8584 # Per bank write bursts -system.physmem.perBankWrBursts::14 7909 # Per bank write bursts -system.physmem.perBankWrBursts::15 7678 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 50731 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11367 # Per bank write bursts +system.physmem.perBankRdBursts::1 11306 # Per bank write bursts +system.physmem.perBankRdBursts::2 12534 # Per bank write bursts +system.physmem.perBankRdBursts::3 11925 # Per bank write bursts +system.physmem.perBankRdBursts::4 14392 # Per bank write bursts +system.physmem.perBankRdBursts::5 11995 # Per bank write bursts +system.physmem.perBankRdBursts::6 12528 # Per bank write bursts +system.physmem.perBankRdBursts::7 12413 # Per bank write bursts +system.physmem.perBankRdBursts::8 12465 # Per bank write bursts +system.physmem.perBankRdBursts::9 12343 # Per bank write bursts +system.physmem.perBankRdBursts::10 12048 # Per bank write bursts +system.physmem.perBankRdBursts::11 11291 # Per bank write bursts +system.physmem.perBankRdBursts::12 11598 # Per bank write bursts +system.physmem.perBankRdBursts::13 11714 # Per bank write bursts +system.physmem.perBankRdBursts::14 10851 # Per bank write bursts +system.physmem.perBankRdBursts::15 10797 # Per bank write bursts +system.physmem.perBankWrBursts::0 8020 # Per bank write bursts +system.physmem.perBankWrBursts::1 8176 # Per bank write bursts +system.physmem.perBankWrBursts::2 9316 # Per bank write bursts +system.physmem.perBankWrBursts::3 8567 # Per bank write bursts +system.physmem.perBankWrBursts::4 8317 # Per bank write bursts +system.physmem.perBankWrBursts::5 8617 # Per bank write bursts +system.physmem.perBankWrBursts::6 9080 # Per bank write bursts +system.physmem.perBankWrBursts::7 8981 # Per bank write bursts +system.physmem.perBankWrBursts::8 9059 # Per bank write bursts +system.physmem.perBankWrBursts::9 8883 # Per bank write bursts +system.physmem.perBankWrBursts::10 8732 # Per bank write bursts +system.physmem.perBankWrBursts::11 8494 # Per bank write bursts +system.physmem.perBankWrBursts::12 8573 # Per bank write bursts +system.physmem.perBankWrBursts::13 8275 # Per bank write bursts +system.physmem.perBankWrBursts::14 7766 # Per bank write bursts +system.physmem.perBankWrBursts::15 7476 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 2825405630500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2627260507500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 550 # Read request sizes (log2) +system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190049 # Read request sizes (log2) +system.physmem.readPktSize::6 188059 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136827 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 135856 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 73227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87370 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.346618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.604135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.406981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46631 53.37% 53.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17108 19.58% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5841 6.69% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3374 3.86% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2711 3.10% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1534 1.76% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 893 1.02% 89.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1014 1.16% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8264 9.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87370 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6825 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.358242 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.081040 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6823 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 86649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.189431 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.582911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.571271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46399 53.55% 53.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16583 19.14% 72.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5986 6.91% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3348 3.86% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2763 3.19% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1550 1.79% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1005 1.16% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 914 1.05% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8101 9.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86649 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.651211 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 549.102387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6684 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6825 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.116190 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.646323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.038338 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5646 82.73% 82.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 406 5.95% 88.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 199 2.92% 91.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 55 0.81% 92.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 78 1.14% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.21% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.37% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.16% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.22% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.39% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.12% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.23% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6686 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6686 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.390667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.828394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.276627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5432 81.24% 81.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 492 7.36% 88.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 97 1.45% 90.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 153 2.29% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 34 0.51% 92.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 125 1.87% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 42 0.63% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.30% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.36% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 25 0.37% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 159 2.38% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.36% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.12% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6825 # Writes before turning the bus around for reads -system.physmem.totQLat 6500326386 # Total ticks spent queuing -system.physmem.totMemAccLat 10129370136 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 967745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33584.91 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6686 # Writes before turning the bus around for reads +system.physmem.totQLat 6416960776 # Total ticks spent queuing +system.physmem.totMemAccLat 10008842026 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 957835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33497.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52334.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52247.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.47 # Average write queue length when enqueuing -system.physmem.readRowHits 161846 # Number of row buffer hits during reads -system.physmem.writeRowHits 81625 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.44 # Row buffer hit rate for writes -system.physmem.avgGap 8435784.18 # Average gap between requests -system.physmem.pageHitRate 73.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343821240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187600875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 784017000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 459062640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79593993450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625423449500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891333620465 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.402761 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703936458200 # Time in different power states -system.physmem_0.memoryStateTime::REF 94346460000 # Time in different power states +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 159898 # Number of row buffer hits during reads +system.physmem.writeRowHits 81351 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.66 # Row buffer hit rate for writes +system.physmem.avgGap 7914126.56 # Average gap between requests +system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 337168440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 183970875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 767988000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 447599520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75926466675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509753884250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1759016918640 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525234 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2511501025755 # Time in different power states +system.physmem_0.memoryStateTime::REF 87729980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27121665550 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28029087995 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 316695960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 172800375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 725657400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 430596000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78590048175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626304103250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891081576920 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.313555 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705408031049 # Time in different power states -system.physmem_1.memoryStateTime::REF 94346460000 # Time in different power states +system.physmem_1.actEnergy 317898000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 173456250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726226800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 435831840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 75533290650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1510098775500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1758885319920 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.475144 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2512077352355 # Time in different power states +system.physmem_1.memoryStateTime::REF 87729980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25651382451 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27453418145 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -352,30 +352,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 24021626 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15717395 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 977579 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14633586 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10784998 # Number of BTB hits +system.cpu0.branchPred.lookups 22632354 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14659623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 908184 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13749139 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10145845 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.700308 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3879887 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32532 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.792584 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3729563 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29268 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,78 +406,78 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 65547 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65547 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26411 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18806 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 20330 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 45217 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 420.151713 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2682.973536 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 44150 97.64% 97.64% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 821 1.82% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 92 0.20% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 122 0.27% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 7 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 22 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 45217 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9209.084471 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7773.401889 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5863.053322 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14685 94.55% 94.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 794 5.11% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.30% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 89510783948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.549501 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.505567 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 89461994948 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 35577000 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 6153500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3637000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1264000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 750500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 798000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 605000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 89510783948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5141 79.20% 79.20% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1350 20.80% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6491 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65547 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 62082 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 62082 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23874 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18654 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19554 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 42528 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 489.830229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2960.338749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 41379 97.30% 97.30% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 822 1.93% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.35% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 139 0.33% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 42528 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 15147 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9846.471248 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8208.075631 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8231.250252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 15054 99.39% 99.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 70 0.46% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.14% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 15147 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 97524095656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.460762 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.504971 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 97474132156 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 37222000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 6333500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3452500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1280500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 673000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 722500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 263000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 97524095656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5018 79.05% 79.05% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1330 20.95% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6348 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62082 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65547 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6491 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62082 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6348 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6491 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72038 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 68430 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17771522 # DTB read hits -system.cpu0.dtb.read_misses 55962 # DTB read misses -system.cpu0.dtb.write_hits 14661221 # DTB write hits -system.cpu0.dtb.write_misses 9585 # DTB write misses +system.cpu0.dtb.read_hits 16776749 # DTB read hits +system.cpu0.dtb.read_misses 53234 # DTB read misses +system.cpu0.dtb.write_hits 13912942 # DTB write hits +system.cpu0.dtb.write_misses 8848 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 322 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2338 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2058 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17827484 # DTB read accesses -system.cpu0.dtb.write_accesses 14670806 # DTB write accesses +system.cpu0.dtb.perms_faults 829 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16829983 # DTB read accesses +system.cpu0.dtb.write_accesses 13921790 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32432743 # DTB hits -system.cpu0.dtb.misses 65547 # DTB misses -system.cpu0.dtb.accesses 32498290 # DTB accesses +system.cpu0.dtb.hits 30689691 # DTB hits +system.cpu0.dtb.misses 62082 # DTB misses +system.cpu0.dtb.accesses 30751773 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,57 +507,53 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10460 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10460 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4240 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6125 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 95 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10365 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 435.745297 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2168.024140 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9957 96.06% 96.06% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.42% 97.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 193 1.86% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 32 0.31% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 17 0.16% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10365 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2678 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9582.239797 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5620.252827 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1037 38.72% 38.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1516 56.61% 95.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 52 1.94% 97.27% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 65 2.43% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2678 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20779406712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.976236 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.152563 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 494503000 2.38% 2.38% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 20284294712 97.62% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 517000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 92000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20779406712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2260 87.50% 87.50% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 323 12.50% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2583 # Table walker page sizes translated +system.cpu0.itb.walker.walks 10470 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10470 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4275 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6082 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 113 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10357 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 430.336970 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2100.288015 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9961 96.18% 96.18% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 126 1.22% 97.39% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 203 1.96% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.37% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 10 0.10% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10357 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6522.127356 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2498 92.79% 92.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 161 5.98% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 32 1.19% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 20202424328 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.966577 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.179934 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 675884500 3.35% 3.35% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 19525926328 96.65% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 564000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 49500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 20202424328 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2260 87.63% 87.63% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 319 12.37% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10460 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10470 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10470 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2583 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2583 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13043 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37759439 # ITB inst hits -system.cpu0.itb.inst_misses 10460 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13049 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 35710587 # ITB inst hits +system.cpu0.itb.inst_misses 10470 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,98 +562,98 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2357 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2356 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1940 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37769899 # ITB inst accesses -system.cpu0.itb.hits 37759439 # DTB hits -system.cpu0.itb.misses 10460 # DTB misses -system.cpu0.itb.accesses 37769899 # DTB accesses -system.cpu0.numCycles 130135672 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 35721057 # ITB inst accesses +system.cpu0.itb.hits 35710587 # DTB hits +system.cpu0.itb.misses 10470 # DTB misses +system.cpu0.itb.accesses 35721057 # DTB accesses +system.cpu0.numCycles 126659372 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18741348 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112674064 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 24021626 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14664885 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 105564363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2824766 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148935 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 59402 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 359448 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 427042 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 91226 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37760092 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 271445 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4846 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 126804147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.071967 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.260919 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 17871987 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 106431260 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 22632354 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 13875408 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 101673133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2651880 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 146874 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 68068 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 354842 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 428688 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 93530 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 35711195 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 256145 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4738 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 121963062 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.052824 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.258485 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64261882 50.68% 50.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21462384 16.93% 67.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8772204 6.92% 74.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32307677 25.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62962688 51.62% 51.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 20162814 16.53% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8269817 6.78% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 30567743 25.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 126804147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.184589 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.865820 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19721438 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 59617090 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41434685 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4962697 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3055964 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 348356 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110795648 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3978318 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25470078 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12211623 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36823403 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40512045 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10718761 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105720614 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1057290 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1452767 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 161700 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58122 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6514709 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109806374 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 482725120 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 121004760 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9383 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98259136 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11547235 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1229554 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1088238 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12335468 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18754417 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16214275 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1701393 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2256069 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102765106 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1695392 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100794287 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 484302 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9532947 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22407435 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 122350 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 126804147 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.794882 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.031887 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 121963062 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.178687 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.840295 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18684987 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58693341 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 38833256 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4747637 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1003841 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2912386 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 326313 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 104496141 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3704345 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1003841 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24126481 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12572099 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 34554184 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 38013567 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11692890 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 99684423 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 977099 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1404281 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 150386 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 54053 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7679999 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 103244507 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 455598825 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 114217475 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 92488092 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10756412 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1189033 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1051673 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11830745 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 17693579 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 15395073 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1633265 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2155883 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 96874005 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1635627 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 95096979 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 454397 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8909178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 20852751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116081 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 121963062 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.779720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.027198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 70515231 55.61% 55.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23338464 18.41% 74.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22507800 17.75% 91.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9330414 7.36% 99.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1112209 0.88% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 68765776 56.38% 56.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 22213388 18.21% 74.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 21122370 17.32% 91.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 8807290 7.22% 99.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1054209 0.86% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -665,930 +661,947 @@ system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 126804147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 121963062 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9354884 40.60% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 74 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5601126 24.31% 64.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8088042 35.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 8813581 40.35% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 132 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5351630 24.50% 64.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7678552 35.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66470143 65.95% 65.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93430 0.09% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8105 0.01% 66.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18478690 18.33% 84.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15741645 15.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 62602265 65.83% 65.83% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 87841 0.09% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7143 0.01% 65.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 17444547 18.34% 84.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 14952910 15.72% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100794287 # Type of FU issued -system.cpu0.iq.rate 0.774532 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23044126 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228625 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 351888789 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 114001116 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98678663 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32360 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9725 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123815106 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21034 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 363531 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 95096979 # Type of FU issued +system.cpu0.iq.rate 0.750809 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 21843895 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229701 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 334422549 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 107425966 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 93117016 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32763 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11378 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9790 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 116917216 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21386 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 346137 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1999131 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2544 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19035 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1014690 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1858057 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2517 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18608 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 952368 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 107294 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362990 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 100941 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 343903 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1634305 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 175316 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104635112 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1003841 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1765434 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 210085 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 98680740 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18754417 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16214275 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876681 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291768 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 691707 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 17693579 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 15395073 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 848677 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 265561 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 639508 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174614 # number of nop insts executed -system.cpu0.iew.exec_refs 33573838 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16859604 # Number of branches executed -system.cpu0.iew.exec_stores 15551159 # Number of stores executed -system.cpu0.iew.exec_rate 0.766106 # Inst execution rate -system.cpu0.iew.wb_sent 99140543 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98688388 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51348142 # num instructions producing a value -system.cpu0.iew.wb_consumers 84871692 # num instructions consuming a value +system.cpu0.iew.exec_nop 171108 # number of nop insts executed +system.cpu0.iew.exec_refs 31795600 # number of memory reference insts executed +system.cpu0.iew.exec_branches 15818182 # Number of branches executed +system.cpu0.iew.exec_stores 14774938 # Number of stores executed +system.cpu0.iew.exec_rate 0.742778 # Inst execution rate +system.cpu0.iew.wb_sent 93557624 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 93126806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 48392376 # num instructions producing a value +system.cpu0.iew.wb_consumers 80015738 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.758350 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605009 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.735254 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.604786 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8492759 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1573042 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 633433 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 125053157 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.760074 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.473514 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7942186 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1519546 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 586085 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 120319586 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.745699 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.465434 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 80626724 64.47% 64.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24772258 19.81% 84.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8266840 6.61% 90.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3238221 2.59% 93.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3432782 2.75% 96.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1539199 1.23% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1134355 0.91% 98.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 546479 0.44% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1496299 1.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 78400270 65.16% 65.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 23370127 19.42% 84.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 7855137 6.53% 91.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3041175 2.53% 93.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3186617 2.65% 96.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1413825 1.18% 97.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1097896 0.91% 98.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 521063 0.43% 98.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1433476 1.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 125053157 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78998098 # Number of instructions committed -system.cpu0.commit.committedOps 95049599 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 120319586 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 74552173 # Number of instructions committed +system.cpu0.commit.committedOps 89722144 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31954871 # Number of memory references committed -system.cpu0.commit.loads 16755286 # Number of loads committed -system.cpu0.commit.membars 647733 # Number of memory barriers committed -system.cpu0.commit.branches 16226575 # Number of branches committed -system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81983360 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1932291 # Number of function calls committed. +system.cpu0.commit.refs 30278227 # Number of memory references committed +system.cpu0.commit.loads 15835522 # Number of loads committed +system.cpu0.commit.membars 627502 # Number of memory barriers committed +system.cpu0.commit.branches 15222627 # Number of branches committed +system.cpu0.commit.fp_insts 9772 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 77510355 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1849810 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62995577 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 91046 0.10% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8105 0.01% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16755286 17.63% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15199585 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 59351234 66.15% 66.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 85540 0.10% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7143 0.01% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 15835522 17.65% 83.90% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 14442705 16.10% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 95049599 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1496299 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 222908078 # The number of ROB reads -system.cpu0.rob.rob_writes 208834787 # The number of ROB writes -system.cpu0.timesIdled 129596 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3331525 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5520676264 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78876046 # Number of Instructions Simulated -system.cpu0.committedOps 94927547 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.649876 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.649876 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.606106 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.606106 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110754452 # number of integer regfile reads -system.cpu0.int_regfile_writes 59798186 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8167 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 89722144 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1433476 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 212523033 # The number of ROB reads +system.cpu0.rob.rob_writes 196970686 # The number of ROB writes +system.cpu0.timesIdled 126988 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4696310 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5127862528 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 74430479 # Number of Instructions Simulated +system.cpu0.committedOps 89600450 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.701714 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.701714 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.587643 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.587643 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 104622739 # number of integer regfile reads +system.cpu0.int_regfile_writes 56501496 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8247 # number of floating regfile reads system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 351214590 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41113323 # number of cc regfile writes -system.cpu0.misc_regfile_reads 177297499 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1225193 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 713718 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.250179 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28854841 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 714230 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.399929 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 274766500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.250179 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965332 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965332 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 331476991 # number of cc regfile reads +system.cpu0.cc_regfile_writes 38443016 # number of cc regfile writes +system.cpu0.misc_regfile_reads 169856708 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1190913 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 672498 # number of replacements +system.cpu0.dcache.tags.tagsinuse 485.161129 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 27296512 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 673010 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.558851 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.161129 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947580 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947580 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63563549 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63563549 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15604955 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15604955 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12027073 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12027073 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310316 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 310316 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363058 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363058 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361354 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361354 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27632028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27632028 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27942344 # number of overall hits -system.cpu0.dcache.overall_hits::total 27942344 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 644494 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 644494 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1893203 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1893203 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147485 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147485 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25333 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25333 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20104 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20104 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2537697 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2537697 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2685182 # number of overall misses -system.cpu0.dcache.overall_misses::total 2685182 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8536879000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8536879000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27482436369 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 27482436369 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389618000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 389618000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 450883500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 450883500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 36019315369 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 36019315369 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 36019315369 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 36019315369 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16249449 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16249449 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13920276 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13920276 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457801 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 457801 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388391 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388391 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381458 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381458 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30169725 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30169725 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30627526 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30627526 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039663 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039663 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136003 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136003 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.322160 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.322160 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065226 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065226 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052703 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052703 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084114 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084114 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087672 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.087672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 60152551 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 60152551 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 14711290 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 14711290 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 11396766 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 11396766 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295733 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 295733 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354236 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354236 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350938 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 350938 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 26108056 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 26108056 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26403789 # number of overall hits +system.cpu0.dcache.overall_hits::total 26403789 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 611234 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 611234 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1805910 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1805910 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141308 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141308 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24174 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24174 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21176 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21176 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2417144 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2417144 # 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number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 728500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 41470141875 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 41470141875 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 41470141875 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 41470141875 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15322524 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 15322524 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13202676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13202676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437041 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 437041 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136784 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063883 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063883 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056907 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056907 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084737 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084737 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088338 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088338 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # 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average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17156.669969 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16209.075595 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16209.075595 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1312 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5225040 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 49 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 192315 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.775510 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.169176 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 517170 # number of writebacks -system.cpu0.dcache.writebacks::total 517170 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 254611 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 254611 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1567828 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1567828 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18755 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18755 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1822439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1822439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 389883 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10067947898 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10067947898 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11728713398 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11728713398 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4315293000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4315293000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3299266500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3299266500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7614559500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7614559500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023994 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023994 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023374 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023374 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222909 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222909 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052703 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052703 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023708 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023708 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026685 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026685 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 490431 # number of writebacks +system.cpu0.dcache.writebacks::total 490431 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 244715 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 244715 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493725 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1493725 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18048 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18048 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1738440 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1738440 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1738440 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1738440 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366519 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366519 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312185 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312185 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97992 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 97992 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6126 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6126 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21176 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21176 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 678704 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 678704 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 776696 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 776696 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17958 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34667 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4650113000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4650113000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6789940400 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6789940400 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1696741500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1696741500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97425500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97425500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513125500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513125500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 716500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 716500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11440053400 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11440053400 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13136794900 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13136794900 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3760775500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3760775500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2938081500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2938081500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6698857000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6698857000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023920 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023920 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023646 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023646 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224217 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224217 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056907 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056907 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023793 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023793 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026818 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026818 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16855.732985 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16855.732985 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16913.689397 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16913.689397 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209420.620336 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209420.620336 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175838.260818 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175838.260818 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193234.401592 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1264231 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.765651 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36438607 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1264743 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.811076 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6439669000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.765651 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999542 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999542 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1200820 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.709969 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 34456109 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1201332 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.681588 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8093069500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.709969 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999434 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76777836 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76777836 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36438607 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36438607 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36438607 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36438607 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36438607 # number of overall hits -system.cpu0.icache.overall_hits::total 36438607 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1317920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1317920 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1317920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1317920 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1317920 # number of overall misses -system.cpu0.icache.overall_misses::total 1317920 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13045197783 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13045197783 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13045197783 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13045197783 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13045197783 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13045197783 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37756527 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37756527 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37756527 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37756527 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37756527 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37756527 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034906 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034906 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034906 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034906 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034906 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034906 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.322951 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.322951 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9898.322951 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9898.322951 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1585730 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 630 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 117915 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.448077 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 57.272727 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 72616555 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 72616555 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 34456109 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34456109 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34456109 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34456109 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34456109 # number of overall hits +system.cpu0.icache.overall_hits::total 34456109 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1251492 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1251492 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1251492 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1251492 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1251492 # number of overall misses +system.cpu0.icache.overall_misses::total 1251492 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13477536890 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13477536890 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13477536890 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13477536890 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13477536890 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13477536890 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 35707601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 35707601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 35707601 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 35707601 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 35707601 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 35707601 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035048 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.035048 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035048 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.035048 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035048 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.035048 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10769.175424 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10769.175424 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10769.175424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10769.175424 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1798735 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 112593 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.975549 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53136 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53136 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53136 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53136 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53136 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53136 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264784 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1264784 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264784 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1264784 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264784 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1264784 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50137 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50137 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50137 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50137 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50137 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50137 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201355 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1201355 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201355 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1201355 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201355 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1201355 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11837775153 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837775153 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11837775153 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11837775153 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11837775153 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11837775153 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033498 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033498 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033498 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9359.523170 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12113813705 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12113813705 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12113813705 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12113813705 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12113813705 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12113813705 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420637998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420637998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420637998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 420637998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033644 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033644 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033644 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10083.458849 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140025.964714 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1848695 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1851312 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2366 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767941 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1770755 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2568 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 233112 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 279786 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16110.932478 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3625969 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 296031 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 12.248612 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2809841331000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7402.389300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.896732 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.359713 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5003.167978 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1996.783797 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1695.334959 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.451806 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000726 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.305369 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121874 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.103475 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983333 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1041 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 288 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 220461 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 267926 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16038.044511 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3405557 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284162 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.984562 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 9237.046322 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.824240 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.088026 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3962.897629 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1653.213235 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.975059 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.563785 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.241876 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100904 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071532 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.978885 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1081 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15141 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 306 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4805 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7004 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2900 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063538 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66593364 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66593364 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 52693 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12386 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 65079 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 517165 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 517165 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28793 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28793 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1744 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1744 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223098 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 223098 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1208893 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1208893 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400319 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 400319 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 52693 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12386 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1208893 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 623417 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1897389 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 52693 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12386 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1208893 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 623417 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1897389 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 398 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 555 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26381 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26381 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18360 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18360 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47293 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 47293 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55856 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 55856 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98075 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 98075 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 398 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 157 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 55856 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 145368 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 201779 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 398 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 157 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 55856 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 145368 # number of overall misses -system.cpu0.l2cache.overall_misses::total 201779 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10822500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3611000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 14433500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 484495000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 484495000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371083000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371083000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 421500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 421500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2673446497 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2673446497 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2697437499 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2697437499 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2928360998 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2928360998 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10822500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3611000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2697437499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5601807495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8313678494 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10822500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3611000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2697437499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5601807495 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8313678494 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 53091 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12543 # 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mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044138 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.195183 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.195183 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093119 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489763 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489763 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.922834 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.922834 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158543 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158543 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042497 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208708 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.208708 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.095702 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210162 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.213492 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23219.469027 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 89557.677124 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 625999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 625999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 118491 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1915950 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30902 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19086 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 881917 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1558941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 295049 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42808 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298585 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285519 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1264784 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 601994 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3774932 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2575467 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29033 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 117114 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6496546 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80991872 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86506920 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50172 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 212364 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 167761328 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1157195 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 5250259 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.213502 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.409779 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3900428 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1972103 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 30395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 166078 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 150 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 98608 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1819240 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 685334 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1450937 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 287419 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 90627 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114961 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 273601 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1201355 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 557036 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3216 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3585963 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2443651 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28820 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 110863 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6169297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76933952 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82016191 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49524 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 198724 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159198391 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 860528 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4738789 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.052471 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.223116 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 4129320 78.65% 78.65% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1120939 21.35% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4490292 94.76% 94.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 248347 5.24% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 150 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 5250259 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2631653442 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4738789 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2495889948 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114940499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112738429 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1900515323 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1805438687 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1221760496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1156413493 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16493992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16448481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 64044457 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 61214934 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 33870827 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11547618 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 303923 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18735544 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 14949091 # Number of BTB hits +system.cpu1.branchPred.lookups 35362528 # Number of BP lookups +system.cpu1.branchPred.condPredicted 12650645 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 376011 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 19640345 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 15643376 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.790002 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12480037 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7268 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.649191 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12652559 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10779 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1618,92 +1631,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 21101 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21101 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8660 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5796 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6645 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14456 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 508.058937 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2886.331667 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13910 96.22% 96.22% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 137 0.95% 97.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 242 1.67% 98.84% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 68 0.47% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.14% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 12 0.08% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 37 0.26% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 11 0.08% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 15 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 24283 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24283 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11247 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5966 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7070 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17213 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 473.798873 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2831.806000 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16574 96.29% 96.29% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 219 1.27% 97.56% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 229 1.33% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 75 0.44% 99.33% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.14% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.04% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.25% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 17 0.10% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14456 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5194 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9424.913362 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8003.762670 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6175.333367 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2569 49.46% 49.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2132 41.05% 90.51% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 361 6.95% 97.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 99 1.91% 99.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.06% 99.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 27 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5194 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72058045764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.162272 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.372420 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 60402096044 83.82% 83.82% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 11637981720 16.15% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 11426500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 2950500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 950000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 753000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 773000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 312500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 161500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 148500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 75000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 134500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 51500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 27000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 156500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72058045764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.91% 75.91% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 606 24.09% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2516 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21101 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 17213 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5394 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9365.976538 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8403.035892 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4813 89.23% 89.23% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 520 9.64% 98.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 49 0.91% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 4 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 4 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5394 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 75766592176 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.320474 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.469554 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 51526613188 68.01% 68.01% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 24219637488 31.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12480500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3766000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1197500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 815500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 985500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 293500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 146000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 224500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 83500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 76500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 137000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 95500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 75766592176 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1932 75.85% 75.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 615 24.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2547 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21101 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2516 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2547 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2516 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 23617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2547 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 26830 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10151644 # DTB read hits -system.cpu1.dtb.read_misses 18305 # DTB read misses -system.cpu1.dtb.write_hits 6523716 # DTB write hits -system.cpu1.dtb.write_misses 2796 # DTB write misses +system.cpu1.dtb.read_hits 11209013 # DTB read hits +system.cpu1.dtb.read_misses 21079 # DTB read misses +system.cpu1.dtb.write_hits 7325054 # DTB write hits +system.cpu1.dtb.write_misses 3204 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 50 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 456 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2001 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 612 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 384 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10169949 # DTB read accesses -system.cpu1.dtb.write_accesses 6526512 # DTB write accesses +system.cpu1.dtb.perms_faults 367 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11230092 # DTB read accesses +system.cpu1.dtb.write_accesses 7328258 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16675360 # DTB hits -system.cpu1.dtb.misses 21101 # DTB misses -system.cpu1.dtb.accesses 16696461 # DTB accesses +system.cpu1.dtb.hits 18534067 # DTB hits +system.cpu1.dtb.misses 24283 # DTB misses +system.cpu1.dtb.accesses 18558350 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1733,60 +1744,57 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6899 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6899 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4113 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2729 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 57 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6842 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 198.333821 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1594.183488 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6730 98.36% 98.36% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.86% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 21 0.31% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 14 0.20% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6842 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1221 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9530.760976 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5854.425690 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 35 2.87% 2.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 374 30.63% 33.50% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 40.70% 74.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 243 19.90% 94.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 3 0.25% 94.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 9 0.74% 95.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 37 3.03% 98.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.31% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.16% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.25% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1221 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 11897679120 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.980675 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.137806 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 230157764 1.93% 1.93% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 11667291856 98.06% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 229500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 11897679120 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 997 85.65% 85.65% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 167 14.35% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1164 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6861 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6861 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4105 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2676 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 80 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6781 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 216.855921 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1684.274104 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6669 98.35% 98.35% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 39 0.58% 98.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 44 0.65% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 12 0.18% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6781 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1249 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6381.189280 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 353 28.26% 28.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 65.17% 93.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 24 1.92% 95.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 32 2.56% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 17 1.36% 99.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.56% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1249 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 15604919032 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.958751 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.198933 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 643875264 4.13% 4.13% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14960875268 95.87% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 148500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 20000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 15604919032 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 997 85.29% 85.29% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 172 14.71% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1169 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6899 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6861 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6861 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1164 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1164 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8063 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43584522 # ITB inst hits -system.cpu1.itb.inst_misses 6899 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1169 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1169 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8030 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 45813094 # ITB inst hits +system.cpu1.itb.inst_misses 6861 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1795,1033 +1803,1043 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1193 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 547 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 526 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43591421 # ITB inst accesses -system.cpu1.itb.hits 43584522 # DTB hits -system.cpu1.itb.misses 6899 # DTB misses -system.cpu1.itb.accesses 43591421 # DTB accesses -system.cpu1.numCycles 105332010 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 45819955 # ITB inst accesses +system.cpu1.itb.hits 45813094 # DTB hits +system.cpu1.itb.misses 6861 # DTB misses +system.cpu1.itb.accesses 45819955 # DTB accesses +system.cpu1.numCycles 115872528 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10132151 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108981973 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33870827 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27429128 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 92017725 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3770452 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88186 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 36483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 195284 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 298638 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22598 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43583923 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 117443 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2417 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104676291 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.289820 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339564 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 11244647 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 115696053 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 35362528 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 28295935 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 100513645 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3955668 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 92958 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 43827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 218813 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 324785 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 35760 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 45812479 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 133633 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2410 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114452269 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.250587 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.333322 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 47827120 45.69% 45.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14002469 13.38% 59.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7529046 7.19% 66.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35317656 33.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 53787165 47.00% 47.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 15397458 13.45% 60.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8067873 7.05% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 37199773 32.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104676291 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.321563 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.034652 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13137871 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 61997568 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26684640 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1104927 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1751285 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 750757 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 136902 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 67935331 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1160131 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1751285 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17557644 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2234457 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57207184 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23346153 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2579568 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55040039 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 231549 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 250107 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36576 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14638 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1569614 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54888875 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 259969011 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58535420 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1673 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52136282 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2752593 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1876398 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1803595 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13068910 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10432997 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6892596 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 625658 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 847753 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54148527 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 587967 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53807238 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 110933 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3881118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5762517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 48708 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104676291 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.514035 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.850765 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114452269 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.305185 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.998477 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 14331089 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 67536075 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 29425449 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1338809 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1820847 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 912295 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 160061 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 74627346 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1451044 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1820847 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19084331 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2925531 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 61205079 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 25977648 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3438833 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 61437487 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 313811 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 329328 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 50880 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 21104 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2227690 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 61781071 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 288761968 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 65715217 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 58198437 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3582634 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1923301 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1845273 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13635165 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11552975 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7780383 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 701343 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 925146 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60392573 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 653667 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 59853310 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 146761 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4556505 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 7374621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 54925 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114452269 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.522954 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.862457 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71469096 68.28% 68.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16529250 15.79% 84.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13041841 12.46% 96.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3350126 3.20% 99.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 285962 0.27% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 77949624 68.11% 68.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 17744881 15.50% 83.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 14511556 12.68% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3899540 3.41% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 346643 0.30% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 25 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104676291 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114452269 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2912792 45.01% 45.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 674 0.01% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1671813 25.83% 70.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1886405 29.15% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3494882 44.84% 44.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 604 0.01% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1953801 25.07% 69.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2345303 30.09% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36660342 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45736 0.08% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3323 0.01% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10366546 19.27% 87.49% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6731225 12.51% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 40748712 68.08% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 52853 0.09% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4129 0.01% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11462159 19.15% 87.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7585390 12.67% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53807238 # Type of FU issued -system.cpu1.iq.rate 0.510835 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6471684 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120275 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 218867204 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58625584 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51813824 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6180 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2068 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60274803 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4053 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90118 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 59853310 # Type of FU issued +system.cpu1.iq.rate 0.516544 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7794590 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.130228 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 242094525 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 65611557 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 57714006 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5715 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67644200 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3633 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 110002 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 483730 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10069 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 351136 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 628284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 842 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10885 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 426405 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 51537 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 78201 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 57089 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 100676 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1751285 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 538520 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 104583 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54788620 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1820847 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 727831 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 179449 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61101449 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10432997 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6892596 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301008 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9394 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 87795 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10069 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 55171 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 126265 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 181436 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53538867 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10265396 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 247288 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 11552975 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7780383 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 331927 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 11154 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 159363 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10885 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 82141 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 153260 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 235401 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59500982 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 11329735 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 328066 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 52126 # number of nop insts executed -system.cpu1.iew.exec_refs 16932944 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11793778 # Number of branches executed -system.cpu1.iew.exec_stores 6667548 # Number of stores executed -system.cpu1.iew.exec_rate 0.508287 # Inst execution rate -system.cpu1.iew.wb_sent 53390597 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51815609 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25160275 # num instructions producing a value -system.cpu1.iew.wb_consumers 38370093 # num instructions consuming a value +system.cpu1.iew.exec_nop 55209 # number of nop insts executed +system.cpu1.iew.exec_refs 18836194 # number of memory reference insts executed +system.cpu1.iew.exec_branches 12894851 # Number of branches executed +system.cpu1.iew.exec_stores 7506459 # Number of stores executed +system.cpu1.iew.exec_rate 0.513504 # Inst execution rate +system.cpu1.iew.wb_sent 59314333 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 57715790 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 28288530 # num instructions producing a value +system.cpu1.iew.wb_consumers 43462608 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.491927 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655726 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.498097 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.650871 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3631838 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 539259 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169982 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102749355 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.495266 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.156980 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 4228906 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 598742 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 219024 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112407306 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.502841 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.169324 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77230128 75.16% 75.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14246960 13.87% 89.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6071957 5.91% 94.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 703815 0.68% 95.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1976351 1.92% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1539288 1.50% 99.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 468880 0.46% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 125021 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 386955 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 84196637 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 15782926 14.04% 88.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6506905 5.79% 94.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 899885 0.80% 95.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 2238894 1.99% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1696394 1.51% 99.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 469505 0.42% 99.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 157300 0.14% 99.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 458860 0.41% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102749355 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41322014 # Number of instructions committed -system.cpu1.commit.committedOps 50888230 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112407306 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 46016034 # Number of instructions committed +system.cpu1.commit.committedOps 56522947 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16490727 # Number of memory references committed -system.cpu1.commit.loads 9949267 # Number of loads committed -system.cpu1.commit.membars 209363 # Number of memory barriers committed -system.cpu1.commit.branches 11627773 # Number of branches committed +system.cpu1.commit.refs 18278669 # Number of memory references committed +system.cpu1.commit.loads 10924691 # Number of loads committed +system.cpu1.commit.membars 232005 # Number of memory barriers committed +system.cpu1.commit.branches 12685356 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45743033 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3362907 # Number of function calls committed. +system.cpu1.commit.int_insts 50487985 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3456157 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34349326 67.50% 67.50% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 44854 0.09% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3323 0.01% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9949267 19.55% 87.15% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6541460 12.85% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 38188356 67.56% 67.56% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 51793 0.09% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.65% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4129 0.01% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 10924691 19.33% 86.99% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7353978 13.01% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50888230 # Class of committed instruction -system.cpu1.commit.bw_lim_events 386955 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 136861200 # The number of ROB reads -system.cpu1.rob.rob_writes 110963404 # The number of ROB writes -system.cpu1.timesIdled 59136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 655719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5544933026 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41289159 # Number of Instructions Simulated -system.cpu1.committedOps 50855375 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.551082 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.551082 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.391991 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.391991 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56164709 # number of integer regfile reads -system.cpu1.int_regfile_writes 35664798 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1398 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 56522947 # Class of committed instruction +system.cpu1.commit.bw_lim_events 458860 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 152481338 # The number of ROB reads +system.cpu1.rob.rob_writes 123545319 # The number of ROB writes +system.cpu1.timesIdled 68699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1420259 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5138082707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 45982821 # Number of Instructions Simulated +system.cpu1.committedOps 56489734 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.519909 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.519909 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.396840 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.396840 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 62666330 # number of integer regfile reads +system.cpu1.int_regfile_writes 39173045 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 190801964 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15538939 # number of cc regfile writes -system.cpu1.misc_regfile_reads 145958777 # number of misc regfile reads -system.cpu1.misc_regfile_writes 388038 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 188683 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.137779 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15712566 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 189037 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 83.118998 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 93446032500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.137779 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916285 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.916285 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32914145 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32914145 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9558582 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9558582 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5897409 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5897409 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49196 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49196 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78850 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78850 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70461 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70461 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15455991 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15455991 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15505187 # number of overall hits -system.cpu1.dcache.overall_hits::total 15505187 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 218229 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 218229 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 396239 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 396239 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29850 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 29850 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18125 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18125 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23674 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23674 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 614468 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 614468 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 644318 # number of overall misses -system.cpu1.dcache.overall_misses::total 644318 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3487669000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3487669000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9663134455 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9663134455 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 358154500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 358154500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554726500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 554726500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 887500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 887500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13150803455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13150803455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13150803455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13150803455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9776811 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9776811 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6293648 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6293648 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79046 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79046 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96975 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96975 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94135 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94135 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16070459 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16070459 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16149505 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16149505 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022321 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022321 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062959 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.062959 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377628 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377628 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186904 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186904 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.251490 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.251490 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038236 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038236 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039897 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039897 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 211754483 # number of cc regfile reads +system.cpu1.cc_regfile_writes 18307351 # number of cc regfile writes +system.cpu1.misc_regfile_reads 158297998 # number of misc regfile reads +system.cpu1.misc_regfile_writes 426234 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 227119 # number of replacements +system.cpu1.dcache.tags.tagsinuse 480.780000 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17377933 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 227440 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 76.406670 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89481619000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 480.780000 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.939023 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.939023 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 24 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36531516 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36531516 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10502192 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10502192 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6578620 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6578620 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65191 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65191 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88541 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88541 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80577 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80577 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17080812 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17080812 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17146003 # number of overall hits +system.cpu1.dcache.overall_hits::total 17146003 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 257246 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 257246 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 477990 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 477990 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35676 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35676 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19120 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19120 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23513 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23513 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 735236 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 735236 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 770912 # number of overall misses +system.cpu1.dcache.overall_misses::total 770912 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4397234500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4397234500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13204055417 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13204055417 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 384125500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 384125500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615714500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 615714500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2019500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2019500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 17601289917 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 17601289917 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 17601289917 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 17601289917 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10759438 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10759438 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7056610 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7056610 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100867 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 100867 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107661 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 107661 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104090 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 104090 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17816048 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17816048 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17916915 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17916915 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023909 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023909 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067736 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.067736 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353693 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353693 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177594 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177594 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225891 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225891 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041268 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041268 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043027 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043027 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1417697 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39735 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35.678797 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1982545 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 49131 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.243243 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 40.352222 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116769 # number of writebacks -system.cpu1.dcache.writebacks::total 116769 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80049 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 80049 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306072 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306072 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13108 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13108 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 386121 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 386121 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 386121 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 386121 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 138180 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 138180 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90167 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90167 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28614 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28614 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5017 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5017 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 228347 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 228347 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256961 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256961 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14486 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1915104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1915104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2355138466 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2355138466 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 482351500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 482351500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90011000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90011000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531068500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531068500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 871500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 871500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4270242966 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4270242966 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4752594466 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4752594466 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2349248500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2349248500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1864740000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1864740000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4213988500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4213988500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014133 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014133 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014327 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014327 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361992 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361992 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051735 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051735 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.251490 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.251490 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014209 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015911 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015911 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 137800 # number of writebacks +system.cpu1.dcache.writebacks::total 137800 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 93990 # 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number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103670 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32269 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32269 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5513 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5513 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23513 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23513 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266926 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266926 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 299195 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 299195 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17062 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31403 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2326061500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2326061500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3203086933 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3203086933 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 553503000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 553503000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 109001000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 109001000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592222500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592222500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1998500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5529148433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5529148433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6082651433 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6082651433 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2940631000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2940631000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2452626000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2452626000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5393257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5393257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015173 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015173 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014691 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014691 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319916 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319916 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051207 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051207 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225891 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225891 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014982 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014982 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016699 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016699 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20714.162101 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20714.162101 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20330.057097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 603214 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.475238 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 42957427 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 603726 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 71.153846 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78885354000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.475238 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975538 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975538 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 672301 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.450521 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 45113050 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 672813 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 67.051395 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79271830500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.450521 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973536 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973536 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 87771063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 87771063 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 42957427 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42957427 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42957427 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42957427 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42957427 # number of overall hits -system.cpu1.icache.overall_hits::total 42957427 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 626240 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 626240 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 626240 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 626240 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 626240 # number of overall misses -system.cpu1.icache.overall_misses::total 626240 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5487739407 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5487739407 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5487739407 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5487739407 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5487739407 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5487739407 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43583667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43583667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43583667 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43583667 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43583667 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43583667 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014369 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014369 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014369 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014369 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014369 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014369 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8762.997265 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8762.997265 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8762.997265 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8762.997265 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 503899 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 46132 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.922982 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 26 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 92297132 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 92297132 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 45113050 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 45113050 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 45113050 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 45113050 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 45113050 # number of overall hits +system.cpu1.icache.overall_hits::total 45113050 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 699105 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 699105 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 699105 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 699105 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 699105 # number of overall misses +system.cpu1.icache.overall_misses::total 699105 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6808598319 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6808598319 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6808598319 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6808598319 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6808598319 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6808598319 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 45812155 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 45812155 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 45812155 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 45812155 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 45812155 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 45812155 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.015260 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.015260 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.015260 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9739.021061 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9739.021061 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9739.021061 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9739.021061 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 778427 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 223 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 55737 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.966073 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 111.500000 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22511 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22511 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22511 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22511 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22511 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22511 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 603729 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 603729 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 603729 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 603729 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 603729 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 603729 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 26283 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 26283 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 26283 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 26283 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 26283 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 26283 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672822 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 672822 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 672822 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 672822 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 672822 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 672822 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5031797233 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5031797233 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5031797233 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5031797233 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5031797233 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5031797233 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9110000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9110000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9110000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9110000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013852 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013852 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8334.529620 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6167077156 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6167077156 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6167077156 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6167077156 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6167077156 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6167077156 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13506000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13506000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13506000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13506000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014687 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014687 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014687 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9165.986184 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 189065 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 189671 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 541 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 262736 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 263407 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 604 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 56769 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48663 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15171.630527 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1474911 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63236 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 23.323914 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 68017 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 62303 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15536.648070 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1677232 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 76854 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 21.823614 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8232.224686 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.332834 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.684874 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3831.793838 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2451.411988 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 641.182307 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.502455 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000225 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233874 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.149622 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.039135 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.926003 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1118 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 35 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13420 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 930 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 167 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8633 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4319 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068237 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002136 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819092 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27275895 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27275895 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 15350 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7200 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 22550 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 116768 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 116768 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1559 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1559 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 954 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 954 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27353 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27353 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 586865 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 586865 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101704 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 101704 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 15350 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7200 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 586865 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 129057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 738472 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 15350 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7200 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 586865 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 129057 # number of overall hits -system.cpu1.l2cache.overall_hits::total 738472 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 400 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 678 # number of ReadReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 6569.267487 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.374590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.390464 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4943.655897 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2538.739672 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1470.219959 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.400956 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000877 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000024 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301737 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.154952 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.089735 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.948282 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1250 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 33 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13268 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 890 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8543 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4263 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076294 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002014 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.809814 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 30842090 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 30842090 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19102 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7340 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 26442 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 137798 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 137798 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1915 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1915 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1089 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1089 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37080 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 37080 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 650319 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 650319 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 128580 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 128580 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19102 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7340 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 650319 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 165660 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 842421 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19102 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7340 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 650319 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 165660 # number of overall hits +system.cpu1.l2cache.overall_hits::total 842421 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 434 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 283 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28175 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28175 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22720 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22720 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33751 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33751 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16862 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 16862 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70088 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 70088 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 400 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 16862 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103839 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 121379 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 400 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 16862 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103839 # 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number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1378926000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 607258000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 607258000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1556092998 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1556092998 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8778500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5791500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 607258000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2935018998 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3556846998 # 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mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959703 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.545480 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.545480 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027920 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407539 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407539 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140563 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.953685 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.953685 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.471080 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.471080 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359509 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359509 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133351 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168104 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170100 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912 # average overall mshr uncacheable latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 67801 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 858839 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11815 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 481520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 790490 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 28803 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75635 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42021 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86708 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 83417 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 65666 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 603729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 520017 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1799792 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 888351 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17049 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 36002 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2741194 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38640160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25264094 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 63000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 63997166 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1119232 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2773999 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.384160 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.486396 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1911239 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 964293 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 15206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115900 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 115705 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 49800 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 965132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 14341 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 177279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 810351 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 43777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73201 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89676 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 81502 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 78977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 672822 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 286780 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 213 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2005740 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1027154 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17080 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42715 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3092689 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43061536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29508655 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30492 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 72678827 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 390895 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2268265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.069071 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.253913 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1708339 61.58% 61.58% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1065660 38.42% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 2111789 93.10% 93.10% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 156281 6.89% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 195 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2773999 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 991762490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2268265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1127589981 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81878499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 88549490 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 905763364 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1009459749 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 398007900 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 464204253 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9580481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9470972 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20262978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23200956 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 59421 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31010 # Transaction distribution +system.iobus.trans_dist::ReadResp 31010 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2837,16 +2855,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2866,7 +2884,7 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2876,7 +2894,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2906,23 +2924,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186507978 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.557293 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.440882 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254755320000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.557293 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909831 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909831 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256003407000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.440882 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902555 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902555 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2936,14 +2954,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32401877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32401877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4274240561 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4274240561 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32401877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32401877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32401877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32401877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32773877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32773877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715888101 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715888101 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32773877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32773877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32773877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32773877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2960,19 +2978,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128578.876984 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128578.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128578.876984 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130055.067460 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130055.067460 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130055.067460 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.200000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2986,14 +3004,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19801877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19801877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463040561 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2463040561 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19801877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19801877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19801877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19801877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20173877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20173877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904688101 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904688101 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20173877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20173877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20173877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20173877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3002,601 +3020,603 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130408 # number of replacements -system.l2c.tags.tagsinuse 64065.129893 # Cycle average of tags in use -system.l2c.tags.total_refs 410009 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 194847 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.104261 # Average number of references to valid blocks. +system.l2c.tags.replacements 129384 # number of replacements +system.l2c.tags.tagsinuse 63948.068698 # Cycle average of tags in use +system.l2c.tags.total_refs 411864 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 193785 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.125366 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11642.697009 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.974901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.090106 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8094.672337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2978.207969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37076.471677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.445472 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909924 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1874.720720 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 683.354796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1693.584982 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.177653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000213 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.123515 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565742 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12531.983329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.494639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048364 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6442.782513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2029.980541 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.674973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.902888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3492.124605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1459.870620 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3683.572737 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.191223 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.098309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.030975 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.523066 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028606 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010427 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977556 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31097 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33320 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5745 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 26654 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.474503 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.508423 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5488101 # Number of tag accesses -system.l2c.tags.data_accesses 5488101 # Number of data accesses -system.l2c.Writeback_hits::writebacks 227912 # number of Writeback hits -system.l2c.Writeback_hits::total 227912 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2549 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 581 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3130 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 167 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 333 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3885 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1531 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5416 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 182 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # 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average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772079 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.831414 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.790268 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.776339 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.918836 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.851867 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733234 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.757702 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.148569 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.163348 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.512405 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.529772 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.529772 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75444.184652 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75349.496474 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75413.647522 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77427.701891 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76740 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77034.542163 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 142007.953389 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123717.238878 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 134080.220068 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128931.436450 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 37974 # Transaction distribution -system.membus.trans_dist::ReadResp 209076 # Transaction distribution -system.membus.trans_dist::WriteReq 30901 # Transaction distribution -system.membus.trans_dist::WriteResp 30901 # Transaction distribution -system.membus.trans_dist::Writeback 136827 # Transaction distribution -system.membus.trans_dist::CleanEvict 16300 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76178 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40718 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13724 # Transaction distribution -system.membus.trans_dist::ReadExReq 39427 # Transaction distribution -system.membus.trans_dist::ReadExResp 19516 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171103 # Transaction distribution +system.membus.trans_dist::ReadReq 38123 # Transaction distribution +system.membus.trans_dist::ReadResp 207766 # Transaction distribution +system.membus.trans_dist::WriteReq 31050 # Transaction distribution +system.membus.trans_dist::WriteResp 31050 # Transaction distribution +system.membus.trans_dist::Writeback 135856 # Transaction distribution +system.membus.trans_dist::CleanEvict 15674 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78082 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41568 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14509 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 38794 # Transaction distribution +system.membus.trans_dist::ReadExResp 18985 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169644 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663947 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 785587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661810 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 784044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 894521 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892978 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18671220 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18861706 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18481720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18673398 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21179850 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123655 # Total snoops (count) -system.membus.snoop_fanout::samples 585907 # Request fanout histogram +system.membus.pkt_size::total 20991542 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125523 # Total snoops (count) +system.membus.snoop_fanout::samples 585264 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 585907 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 585264 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 585907 # Request fanout histogram -system.membus.reqLayer0.occupancy 81623000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 585264 # Request fanout histogram +system.membus.reqLayer0.occupancy 81621000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11432490 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11798981 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 989982724 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 986725496 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1127040159 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1119474906 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64467297 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64610767 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3639,50 +3659,56 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 37978 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 489550 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30901 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 364752 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 88216 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79213 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41051 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 120264 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50507 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50507 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 451588 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 957960 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 483276 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 165836 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 22284 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 21444 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 38126 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 494242 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31050 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31050 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 364748 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 86802 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 81249 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41933 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 123182 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50538 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50538 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 456132 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1086474 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 331144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1417618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32384412 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5153902 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37538314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 454329 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1220605 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.166616 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.372633 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1043214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 384499 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1427713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31299443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6394691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37694134 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 458404 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1229453 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.314167 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.465653 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1017233 83.34% 83.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 203372 16.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 844039 68.65% 68.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 384574 31.28% 99.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 840 0.07% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1220605 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 824158889 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1229453 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 827244513 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 620803562 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 603608816 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 245897316 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 273833055 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 2086 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2769 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 0a443d2f1..886ff6be1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827546 # Number of seconds simulated -sim_ticks 2827546300000 # Number of ticks simulated -final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832619 # Number of seconds simulated +sim_ticks 2832618668500 # Number of ticks simulated +final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101558 # Simulator instruction rate (inst/s) -host_op_rate 123188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2538650252 # Simulator tick rate (ticks/s) -host_mem_usage 576848 # Number of bytes of host memory used -host_seconds 1113.80 # Real time elapsed on the host -sim_insts 113115023 # Number of instructions simulated -sim_ops 137206411 # Number of ops (including micro ops) simulated +host_inst_rate 90415 # Simulator instruction rate (inst/s) +host_op_rate 109666 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2263800643 # Simulator tick rate (ticks/s) +host_mem_usage 628336 # Number of bytes of host memory used +host_seconds 1251.27 # Real time elapsed on the host +sim_insts 113133035 # Number of instructions simulated +sim_ops 137220830 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory +system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176040 # Number of read requests accepted -system.physmem.writeReqs 135452 # Number of write requests accepted -system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue -system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11283 # Per bank write bursts -system.physmem.perBankRdBursts::1 10909 # Per bank write bursts -system.physmem.perBankRdBursts::2 10879 # Per bank write bursts -system.physmem.perBankRdBursts::3 10544 # Per bank write bursts -system.physmem.perBankRdBursts::4 14049 # Per bank write bursts -system.physmem.perBankRdBursts::5 11359 # Per bank write bursts -system.physmem.perBankRdBursts::6 11255 # Per bank write bursts -system.physmem.perBankRdBursts::7 11497 # Per bank write bursts -system.physmem.perBankRdBursts::8 10572 # Per bank write bursts -system.physmem.perBankRdBursts::9 11295 # Per bank write bursts -system.physmem.perBankRdBursts::10 10218 # Per bank write bursts -system.physmem.perBankRdBursts::11 9589 # Per bank write bursts -system.physmem.perBankRdBursts::12 9979 # Per bank write bursts -system.physmem.perBankRdBursts::13 10701 # Per bank write bursts -system.physmem.perBankRdBursts::14 10842 # Per bank write bursts -system.physmem.perBankRdBursts::15 10903 # Per bank write bursts -system.physmem.perBankWrBursts::0 8346 # Per bank write bursts -system.physmem.perBankWrBursts::1 8306 # Per bank write bursts -system.physmem.perBankWrBursts::2 8514 # Per bank write bursts -system.physmem.perBankWrBursts::3 8219 # Per bank write bursts -system.physmem.perBankWrBursts::4 8602 # Per bank write bursts -system.physmem.perBankWrBursts::5 8561 # Per bank write bursts -system.physmem.perBankWrBursts::6 8053 # Per bank write bursts -system.physmem.perBankWrBursts::7 8529 # Per bank write bursts -system.physmem.perBankWrBursts::8 8073 # Per bank write bursts -system.physmem.perBankWrBursts::9 8804 # Per bank write bursts -system.physmem.perBankWrBursts::10 7852 # Per bank write bursts -system.physmem.perBankWrBursts::11 7407 # Per bank write bursts -system.physmem.perBankWrBursts::12 7747 # Per bank write bursts -system.physmem.perBankWrBursts::13 8181 # Per bank write bursts -system.physmem.perBankWrBursts::14 8268 # Per bank write bursts -system.physmem.perBankWrBursts::15 8079 # Per bank write bursts +system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170127 # Number of read requests accepted +system.physmem.writeReqs 129798 # Number of write requests accepted +system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11277 # Per bank write bursts +system.physmem.perBankRdBursts::1 10595 # Per bank write bursts +system.physmem.perBankRdBursts::2 11086 # Per bank write bursts +system.physmem.perBankRdBursts::3 11282 # Per bank write bursts +system.physmem.perBankRdBursts::4 12957 # Per bank write bursts +system.physmem.perBankRdBursts::5 9975 # Per bank write bursts +system.physmem.perBankRdBursts::6 10510 # Per bank write bursts +system.physmem.perBankRdBursts::7 10855 # Per bank write bursts +system.physmem.perBankRdBursts::8 10363 # Per bank write bursts +system.physmem.perBankRdBursts::9 10082 # Per bank write bursts +system.physmem.perBankRdBursts::10 10269 # Per bank write bursts +system.physmem.perBankRdBursts::11 9303 # Per bank write bursts +system.physmem.perBankRdBursts::12 9940 # Per bank write bursts +system.physmem.perBankRdBursts::13 11053 # Per bank write bursts +system.physmem.perBankRdBursts::14 10302 # Per bank write bursts +system.physmem.perBankRdBursts::15 10142 # Per bank write bursts +system.physmem.perBankWrBursts::0 8501 # Per bank write bursts +system.physmem.perBankWrBursts::1 7938 # Per bank write bursts +system.physmem.perBankWrBursts::2 8637 # Per bank write bursts +system.physmem.perBankWrBursts::3 8770 # Per bank write bursts +system.physmem.perBankWrBursts::4 7610 # Per bank write bursts +system.physmem.perBankWrBursts::5 7376 # Per bank write bursts +system.physmem.perBankWrBursts::6 7709 # Per bank write bursts +system.physmem.perBankWrBursts::7 8071 # Per bank write bursts +system.physmem.perBankWrBursts::8 7782 # Per bank write bursts +system.physmem.perBankWrBursts::9 7594 # Per bank write bursts +system.physmem.perBankWrBursts::10 7680 # Per bank write bursts +system.physmem.perBankWrBursts::11 6982 # Per bank write bursts +system.physmem.perBankWrBursts::12 7590 # Per bank write bursts +system.physmem.perBankWrBursts::13 8396 # Per bank write bursts +system.physmem.perBankWrBursts::14 7757 # Per bank write bursts +system.physmem.perBankWrBursts::15 7487 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2827546089000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2832618457500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2997 # Read request sizes (log2) +system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172487 # Read request sizes (log2) +system.physmem.readPktSize::6 166575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131071 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125417 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,156 +159,155 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads -system.physmem.totQLat 2123501000 # Total ticks spent queuing -system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads +system.physmem.totQLat 2109686750 # Total ticks spent queuing +system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 144861 # Number of row buffer hits during reads -system.physmem.writeRowHits 97354 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 9077427.64 # Average gap between requests -system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.382186 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states -system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing +system.physmem.readRowHits 139766 # Number of row buffer hits during reads +system.physmem.writeRowHits 93986 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes +system.physmem.avgGap 9444422.63 # Average gap between requests +system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.462100 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states +system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.301228 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states -system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states +system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.364017 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states +system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -328,15 +327,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46902830 # Number of BP lookups -system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits +system.cpu.branchPred.lookups 46909632 # Number of BP lookups +system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -367,86 +366,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 72877 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walks 71741 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25454298 # DTB read hits -system.cpu.dtb.read_misses 62609 # DTB read misses -system.cpu.dtb.write_hits 19910353 # DTB write hits -system.cpu.dtb.write_misses 10268 # DTB write misses +system.cpu.dtb.read_hits 25458814 # DTB read hits +system.cpu.dtb.read_misses 61805 # DTB read misses +system.cpu.dtb.write_hits 19912938 # DTB write hits +system.cpu.dtb.write_misses 9936 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25516907 # DTB read accesses -system.cpu.dtb.write_accesses 19920621 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25520619 # DTB read accesses +system.cpu.dtb.write_accesses 19922874 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45364651 # DTB hits -system.cpu.dtb.misses 72877 # DTB misses -system.cpu.dtb.accesses 45437528 # DTB accesses +system.cpu.dtb.hits 45371752 # DTB hits +system.cpu.dtb.misses 71741 # DTB misses +system.cpu.dtb.accesses 45443493 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -476,56 +468,54 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11947 # Table walker walks requested -system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walks 11944 # Table walker walks requested +system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66251443 # ITB inst hits -system.cpu.itb.inst_misses 11947 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66274552 # ITB inst hits +system.cpu.itb.inst_misses 11944 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -534,143 +524,143 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66263390 # ITB inst accesses -system.cpu.itb.hits 66251443 # DTB hits -system.cpu.itb.misses 11947 # DTB misses -system.cpu.itb.accesses 66263390 # DTB accesses -system.cpu.numCycles 263015768 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66286496 # ITB inst accesses +system.cpu.itb.hits 66274552 # DTB hits +system.cpu.itb.misses 11944 # DTB misses +system.cpu.itb.accesses 66286496 # DTB accesses +system.cpu.numCycles 277645869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -694,101 +684,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued -system.cpu.iq.rate 0.544767 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued +system.cpu.iq.rate 0.516124 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 201061 # number of nop insts executed -system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed -system.cpu.iew.exec_branches 26517785 # Number of branches executed -system.cpu.iew.exec_stores 20872797 # Number of stores executed -system.cpu.iew.exec_rate 0.541174 # Inst execution rate -system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63256602 # num instructions producing a value -system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value +system.cpu.iew.exec_nop 200573 # number of nop insts executed +system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed +system.cpu.iew.exec_branches 26519669 # Number of branches executed +system.cpu.iew.exec_stores 20875979 # Number of stores executed +system.cpu.iew.exec_rate 0.512728 # Inst execution rate +system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271886 # num instructions producing a value +system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113269928 # Number of instructions committed -system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113287940 # Number of instructions committed +system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45498874 # Number of memory references committed -system.cpu.commit.loads 24907631 # Number of loads committed -system.cpu.commit.membars 814016 # Number of memory barriers committed -system.cpu.commit.branches 26032948 # Number of branches committed -system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120189151 # Number of committed integer instructions. -system.cpu.commit.function_calls 4888294 # Number of function calls committed. +system.cpu.commit.refs 45505753 # Number of memory references committed +system.cpu.commit.loads 24911268 # Number of loads committed +system.cpu.commit.membars 814898 # Number of memory barriers committed +system.cpu.commit.branches 26034583 # Number of branches committed +system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. +system.cpu.commit.function_calls 4887749 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -812,501 +802,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction -system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 375595727 # The number of ROB reads -system.cpu.rob.rob_writes 292884314 # The number of ROB writes -system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113115023 # Number of Instructions Simulated -system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads -system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155781292 # number of integer regfile reads -system.cpu.int_regfile_writes 88602572 # number of integer regfile writes -system.cpu.fp_regfile_reads 9590 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction +system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 388465780 # The number of ROB reads +system.cpu.rob.rob_writes 292930075 # The number of ROB writes +system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113133035 # Number of Instructions Simulated +system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads +system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155797969 # number of integer regfile reads +system.cpu.int_regfile_writes 88612711 # number of integer regfile writes +system.cpu.fp_regfile_reads 9524 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502823661 # number of cc regfile reads -system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes -system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads -system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes -system.cpu.dcache.tags.replacements 839265 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502896975 # number of cc regfile reads +system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes +system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes +system.cpu.dcache.tags.replacements 840044 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179307579 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 715207 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715207 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834878 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834878 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6403711500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019107 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 64290369 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1889562 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.023953 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16212707500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.157898 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998355 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998355 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits -system.cpu.icache.overall_hits::total 64263909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses -system.cpu.icache.overall_misses::total 1984699 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64290369 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64290369 # number of overall hits +system.cpu.icache.overall_hits::total 64290369 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981370 # number of overall misses +system.cpu.icache.overall_misses::total 1981370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28130756994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28130756994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28130756994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66271739 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029898 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029898 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029898 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029898 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029898 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029898 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14197.629415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14197.629415 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4834 # 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average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 201613 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194580 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::ReadReq 30172 # Transaction distribution +system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1518,9 +1514,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1543,9 +1539,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1586,52 +1582,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use +system.iocache.tags.replacements 36413 # number of replacements +system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses +system.iocache.tags.tag_accesses 328023 # Number of tag accesses +system.iocache.tags.data_accesses 328023 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses +system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses -system.iocache.demand_misses::total 233 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 233 # number of overall misses -system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses +system.iocache.demand_misses::total 223 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 223 # number of overall misses +system.iocache.overall_misses::total 223 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1640,14 +1636,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1658,22 +1654,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1682,68 +1678,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 68549 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131071 # Transaction distribution -system.membus.trans_dist::CleanEvict 8154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution -system.membus.trans_dist::ReadExReq 138564 # Transaction distribution -system.membus.trans_dist::ReadExResp 138564 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution +system.membus.trans_dist::ReadReq 34133 # Transaction distribution +system.membus.trans_dist::ReadResp 67584 # Transaction distribution +system.membus.trans_dist::WriteReq 27585 # Transaction distribution +system.membus.trans_dist::WriteResp 27585 # Transaction distribution +system.membus.trans_dist::Writeback 125417 # Transaction distribution +system.membus.trans_dist::CleanEvict 7628 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution +system.membus.trans_dist::ReadExReq 133608 # Transaction distribution +system.membus.trans_dist::ReadExResp 133608 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 414951 # Request fanout histogram +system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 487 # Total snoops (count) +system.membus.snoop_fanout::samples 402837 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 414951 # Request fanout histogram -system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402837 # Request fanout histogram +system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1776,17 +1772,17 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index b0310bea3..d7415aa23 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,160 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823417 # Number of seconds simulated -sim_ticks 2823417216000 # Number of ticks simulated -final_tick 2823417216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824718 # Number of seconds simulated +sim_ticks 2824717821500 # Number of ticks simulated +final_tick 2824717821500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190092 # Simulator instruction rate (inst/s) -host_op_rate 230584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4366555088 # Simulator tick rate (ticks/s) -host_mem_usage 623124 # Number of bytes of host memory used -host_seconds 646.60 # Real time elapsed on the host -sim_insts 122913537 # Number of instructions simulated -sim_ops 149095594 # Number of ops (including micro ops) simulated +host_inst_rate 249146 # Simulator instruction rate (inst/s) +host_op_rate 302232 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5724351305 # Simulator tick rate (ticks/s) +host_mem_usage 631692 # Number of bytes of host memory used +host_seconds 493.46 # Real time elapsed on the host +sim_insts 122942928 # Number of instructions simulated +sim_ops 149138280 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 532260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3026788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 894784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 379328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2028160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 356352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3635968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 536420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4179876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 910464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 318592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1655680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 408768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3010752 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10983560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 532260 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 379328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 356352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1390052 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8264064 # Number of bytes written to this memory +system.physmem.bytes_read::total 11149640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 536420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 318592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 408768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1385572 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8394624 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8281588 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8412148 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 47813 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31690 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 75 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 56812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65830 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1903 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 25870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 63 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 47043 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129126 # Number of write requests responded to by this memory +system.physmem.num_reads::total 183186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131166 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133507 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135547 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 188516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1072030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 316915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 134351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 718335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 126213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1287790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 189902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1479750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 322320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 112787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 586140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 144711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1065859 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3890165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 188516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 134351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 126213 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2926972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2933179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2926972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3947169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189902 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 112787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 144711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2971845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2978049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2971845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 188516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1078237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 316915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 134351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 718335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 126213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1287790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 189902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1485954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 322320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 112787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 586140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 144711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1065859 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6823344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 115987 # Number of read requests accepted -system.physmem.writeReqs 70622 # Number of write requests accepted -system.physmem.readBursts 115987 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 70622 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7416384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 4519488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7423168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4519808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6925218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 100502 # Number of read requests accepted +system.physmem.writeReqs 68912 # Number of write requests accepted +system.physmem.readBursts 100502 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 68912 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6426176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 4409728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6432128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4410368 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16716 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7738 # Per bank write bursts -system.physmem.perBankRdBursts::1 7157 # Per bank write bursts -system.physmem.perBankRdBursts::2 7568 # Per bank write bursts -system.physmem.perBankRdBursts::3 7635 # Per bank write bursts -system.physmem.perBankRdBursts::4 7727 # Per bank write bursts -system.physmem.perBankRdBursts::5 7298 # Per bank write bursts -system.physmem.perBankRdBursts::6 7875 # Per bank write bursts -system.physmem.perBankRdBursts::7 7810 # Per bank write bursts -system.physmem.perBankRdBursts::8 7237 # Per bank write bursts -system.physmem.perBankRdBursts::9 7597 # Per bank write bursts -system.physmem.perBankRdBursts::10 7159 # Per bank write bursts -system.physmem.perBankRdBursts::11 6221 # Per bank write bursts -system.physmem.perBankRdBursts::12 6467 # Per bank write bursts -system.physmem.perBankRdBursts::13 7007 # Per bank write bursts -system.physmem.perBankRdBursts::14 6960 # Per bank write bursts -system.physmem.perBankRdBursts::15 6425 # Per bank write bursts -system.physmem.perBankWrBursts::0 4628 # Per bank write bursts -system.physmem.perBankWrBursts::1 4274 # Per bank write bursts -system.physmem.perBankWrBursts::2 4625 # Per bank write bursts -system.physmem.perBankWrBursts::3 4563 # Per bank write bursts -system.physmem.perBankWrBursts::4 4564 # Per bank write bursts -system.physmem.perBankWrBursts::5 4431 # Per bank write bursts -system.physmem.perBankWrBursts::6 4784 # Per bank write bursts -system.physmem.perBankWrBursts::7 4577 # Per bank write bursts -system.physmem.perBankWrBursts::8 4485 # Per bank write bursts -system.physmem.perBankWrBursts::9 4954 # Per bank write bursts -system.physmem.perBankWrBursts::10 4488 # Per bank write bursts -system.physmem.perBankWrBursts::11 3709 # Per bank write bursts -system.physmem.perBankWrBursts::12 3882 # Per bank write bursts -system.physmem.perBankWrBursts::13 4478 # Per bank write bursts -system.physmem.perBankWrBursts::14 4241 # Per bank write bursts -system.physmem.perBankWrBursts::15 3934 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 17980 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6920 # Per bank write bursts +system.physmem.perBankRdBursts::1 6286 # Per bank write bursts +system.physmem.perBankRdBursts::2 6764 # Per bank write bursts +system.physmem.perBankRdBursts::3 6403 # Per bank write bursts +system.physmem.perBankRdBursts::4 6105 # Per bank write bursts +system.physmem.perBankRdBursts::5 5950 # Per bank write bursts +system.physmem.perBankRdBursts::6 6704 # Per bank write bursts +system.physmem.perBankRdBursts::7 6701 # Per bank write bursts +system.physmem.perBankRdBursts::8 6487 # Per bank write bursts +system.physmem.perBankRdBursts::9 6589 # Per bank write bursts +system.physmem.perBankRdBursts::10 6182 # Per bank write bursts +system.physmem.perBankRdBursts::11 5526 # Per bank write bursts +system.physmem.perBankRdBursts::12 5641 # Per bank write bursts +system.physmem.perBankRdBursts::13 6650 # Per bank write bursts +system.physmem.perBankRdBursts::14 6151 # Per bank write bursts +system.physmem.perBankRdBursts::15 5350 # Per bank write bursts +system.physmem.perBankWrBursts::0 4550 # Per bank write bursts +system.physmem.perBankWrBursts::1 4246 # Per bank write bursts +system.physmem.perBankWrBursts::2 4783 # Per bank write bursts +system.physmem.perBankWrBursts::3 4329 # Per bank write bursts +system.physmem.perBankWrBursts::4 4133 # Per bank write bursts +system.physmem.perBankWrBursts::5 4124 # Per bank write bursts +system.physmem.perBankWrBursts::6 4743 # Per bank write bursts +system.physmem.perBankWrBursts::7 4271 # Per bank write bursts +system.physmem.perBankWrBursts::8 4451 # Per bank write bursts +system.physmem.perBankWrBursts::9 4796 # Per bank write bursts +system.physmem.perBankWrBursts::10 4218 # Per bank write bursts +system.physmem.perBankWrBursts::11 3947 # Per bank write bursts +system.physmem.perBankWrBursts::12 3851 # Per bank write bursts +system.physmem.perBankWrBursts::13 4779 # Per bank write bursts +system.physmem.perBankWrBursts::14 4130 # Per bank write bursts +system.physmem.perBankWrBursts::15 3551 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2821846409500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2823151552500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 115987 # Read request sizes (log2) +system.physmem.readPktSize::6 100502 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 70622 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 25234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68912 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 76732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -182,173 +186,170 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 75 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.076368 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.108717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.784807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15715 39.25% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9618 24.02% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3841 9.59% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2194 5.48% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1638 4.09% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 995 2.48% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 706 1.76% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 639 1.60% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4697 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40043 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3750 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.898667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 620.943727 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3749 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3750 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3750 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.831200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.732451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.879160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 7 0.19% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 3 0.08% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.05% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.08% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3363 89.68% 90.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 40 1.07% 91.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 85 2.27% 93.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 44 1.17% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 28 0.75% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 63 1.68% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.51% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.03% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.24% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.03% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.13% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.05% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 56 1.49% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.13% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3750 # Writes before turning the bus around for reads -system.physmem.totQLat 1369225250 # Total ticks spent queuing -system.physmem.totMemAccLat 3541994000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 579405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11815.79 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::39 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 275.584628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.263333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.433492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16168 41.12% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9688 24.64% 65.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3830 9.74% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2076 5.28% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1590 4.04% 84.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 981 2.49% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 594 1.51% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 552 1.40% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3840 9.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3599 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.894137 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 471.050714 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3597 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3599 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3599 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.144762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.954400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.164866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 6 0.17% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.14% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3182 88.41% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 82 2.28% 91.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 48 1.33% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 63 1.75% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 10 0.28% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 1.50% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 28 0.78% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.14% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.25% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.47% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.11% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.08% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 52 1.44% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.14% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 13 0.36% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3599 # Writes before turning the bus around for reads +system.physmem.totQLat 1312823000 # Total ticks spent queuing +system.physmem.totMemAccLat 3195491750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 502045000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13074.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30565.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31824.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.05 # Average write queue length when enqueuing -system.physmem.readRowHits 95975 # Number of row buffer hits during reads -system.physmem.writeRowHits 50480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.48 # Row buffer hit rate for writes -system.physmem.avgGap 15121705.86 # Average gap between requests -system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 160793640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 87577875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 474302400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 236170080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72061472520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621212124500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1873921437255 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.499929 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640719336250 # Time in different power states -system.physmem_0.memoryStateTime::REF 91865540000 # Time in different power states +system.physmem.avgWrQLen 20.91 # Average write queue length when enqueuing +system.physmem.readRowHits 80981 # Number of row buffer hits during reads +system.physmem.writeRowHits 49010 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.12 # Row buffer hit rate for writes +system.physmem.avgGap 16664216.37 # Average gap between requests +system.physmem.pageHitRate 76.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85152375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 404274000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 227959920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73215548100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1622782125750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876644765225 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.446746 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640312790250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91908700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18574630750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20242228250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 141931440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 77281875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 429569400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 221428080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71292253815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1621879121250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1873730582100 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.435019 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641834859500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91865540000 # Time in different power states +system.physmem_1.actEnergy 140963760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76741500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 378892800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 218525040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72451612440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1618075692000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1871115844740 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.608024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641479820250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91908700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17456789000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19062807500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -398,47 +399,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5058 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5058 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5058 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5058 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5058 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.269517 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15284046374 -26.95% -26.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993146250 126.95% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56709099876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2875 68.18% 68.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1342 31.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4217 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5058 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4993 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4993 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4993 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4993 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4993 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.255415 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -14647046374 -25.54% -25.54% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993140750 125.54% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 57346094376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2743 66.90% 66.90% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.10% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4100 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4993 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5058 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4217 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4993 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4100 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4217 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9275 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4100 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9093 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12051362 # DTB read hits -system.cpu0.dtb.read_misses 4340 # DTB read misses -system.cpu0.dtb.write_hits 9035813 # DTB write hits -system.cpu0.dtb.write_misses 718 # DTB write misses -system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12030030 # DTB read hits +system.cpu0.dtb.read_misses 4190 # DTB read misses +system.cpu0.dtb.write_hits 9398007 # DTB write hits +system.cpu0.dtb.write_misses 803 # DTB write misses +system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2913 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2915 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 825 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 721 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 186 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12055702 # DTB read accesses -system.cpu0.dtb.write_accesses 9036531 # DTB write accesses +system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12034220 # DTB read accesses +system.cpu0.dtb.write_accesses 9398810 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21087175 # DTB hits -system.cpu0.dtb.misses 5058 # DTB misses -system.cpu0.dtb.accesses 21092233 # DTB accesses +system.cpu0.dtb.hits 21428037 # DTB hits +system.cpu0.dtb.misses 4993 # DTB misses +system.cpu0.dtb.accesses 21433030 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,75 +469,75 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2491 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2491 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2491 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2491 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2491 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.269519 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15284164374 -26.95% -26.95% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993264250 126.95% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56709099876 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1355 75.15% 75.15% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 448 24.85% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1803 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2307 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2307 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2307 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2307 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2307 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.255417 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -14647174874 -25.54% -25.54% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993269250 125.54% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 57346094376 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1275 74.08% 74.08% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 446 25.92% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1721 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2491 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2307 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2307 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1803 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1803 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4294 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56612424 # ITB inst hits -system.cpu0.itb.inst_misses 2491 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1721 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1721 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4028 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57257258 # ITB inst hits +system.cpu0.itb.inst_misses 2307 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1798 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1727 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56614915 # ITB inst accesses -system.cpu0.itb.hits 56612424 # DTB hits -system.cpu0.itb.misses 2491 # DTB misses -system.cpu0.itb.accesses 56614915 # DTB accesses -system.cpu0.numCycles 68338048 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57259565 # ITB inst accesses +system.cpu0.itb.hits 57257258 # DTB hits +system.cpu0.itb.misses 2307 # DTB misses +system.cpu0.itb.accesses 57259565 # DTB accesses +system.cpu0.numCycles 69320920 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55154455 # Number of instructions committed -system.cpu0.committedOps 66797328 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58626360 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4657 # Number of float alu accesses -system.cpu0.num_func_calls 5768343 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7305007 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58626360 # number of integer instructions -system.cpu0.num_fp_insts 4657 # number of float instructions -system.cpu0.num_int_register_reads 108074182 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40930233 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1110 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 203289315 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24533313 # number of times the CC registers were written -system.cpu0.num_mem_refs 21670788 # number of memory refs -system.cpu0.num_load_insts 12200183 # Number of load instructions -system.cpu0.num_store_insts 9470605 # Number of store instructions -system.cpu0.num_idle_cycles 64551377.953400 # Number of idle cycles -system.cpu0.num_busy_cycles 3786670.046600 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055411 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944589 # Percentage of idle cycles -system.cpu0.Branches 13387911 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46158472 67.99% 68.00% # Class of executed instruction -system.cpu0.op_class::IntMult 50521 0.07% 68.07% # Class of executed instruction +system.cpu0.committedInsts 55846469 # Number of instructions committed +system.cpu0.committedOps 67799019 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59476753 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4636 # Number of float alu accesses +system.cpu0.num_func_calls 5739649 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7404981 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59476753 # number of integer instructions +system.cpu0.num_fp_insts 4636 # number of float instructions +system.cpu0.num_int_register_reads 109855675 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41239490 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3530 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 206363052 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25211275 # number of times the CC registers were written +system.cpu0.num_mem_refs 21994746 # number of memory refs +system.cpu0.num_load_insts 12174830 # Number of load instructions +system.cpu0.num_store_insts 9819916 # Number of store instructions +system.cpu0.num_idle_cycles 65448484.972740 # Number of idle cycles +system.cpu0.num_busy_cycles 3872435.027260 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055862 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944138 # Percentage of idle cycles +system.cpu0.Branches 13529823 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2175 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46835768 67.99% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 49875 0.07% 68.07% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction @@ -560,556 +561,556 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3911 0.01% 68.08% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.08% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.08% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.08% # Class of executed instruction -system.cpu0.op_class::MemRead 12200183 17.97% 86.05% # Class of executed instruction -system.cpu0.op_class::MemWrite 9470605 13.95% 100.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3855 0.01% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::MemRead 12174830 17.67% 85.74% # Class of executed instruction +system.cpu0.op_class::MemWrite 9819916 14.26% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 67885870 # Class of executed instruction +system.cpu0.op_class::total 68886419 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 832545 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996677 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45907523 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833057 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.107301 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 833472 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996601 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 46054787 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833984 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.222627 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.190626 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.229209 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.101691 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.475151 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937872 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021932 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009964 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.030225 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.685791 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.479753 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.026378 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.804679 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936886 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022421 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011770 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028915 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193172668 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193172668 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11421172 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3580628 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4071004 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6755438 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25828242 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8699311 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2636349 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3181823 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4260254 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18777737 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177063 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53114 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68363 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 88668 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 387208 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215845 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 73517 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70445 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 91068 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450875 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216890 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75092 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73078 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95506 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460566 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20120483 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6216977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7252827 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 11015692 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44605979 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20297546 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6270091 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7321190 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 11104360 # number of overall hits -system.cpu0.dcache.overall_hits::total 44993187 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170716 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51301 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83273 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 224187 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 529477 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 111265 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 33298 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 105855 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1244902 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1495320 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54398 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16590 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18761 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 47749 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 137498 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3722 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2258 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3555 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8411 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17946 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 281981 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 84599 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 189128 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1469089 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2024797 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336379 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 101189 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 207889 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1516838 # number of overall misses -system.cpu0.dcache.overall_misses::total 2162295 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 822368000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1195559500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3372103500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5390031000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1232764000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5110938996 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 62452939134 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68796642130 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47148760 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014108 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015196 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021620 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.030723 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019710 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013998 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011449 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028172 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.217336 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.066560 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3568395000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 558890500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 964426500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1217476000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2740793000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1287958000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2255199500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2766030500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6309188000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014099 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018100 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016112 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009062 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012473 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017379 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009272 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233315 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.174292 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238592 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121965 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008934 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015027 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031836 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010571 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000283 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013410 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017781 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016821 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009154 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015816 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019592 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019218 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010409 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15036.167637 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13436.290612 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14434.717270 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14249.346887 # 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mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012984 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012984 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012984 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12783.074616 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43415 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43415 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 43415 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43415 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 43415 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43415 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 203961 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 495572 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544166 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1243699 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 203961 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 495572 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 544166 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1243699 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 203961 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 495572 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 544166 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1243699 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2681572500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6562452000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7336863488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16580887988 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2681572500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6562452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7336863488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16580887988 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2681572500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6562452000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7336863488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16580887988 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012951 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012951 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13331.913902 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1140,58 +1141,55 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1838 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1838 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 545 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1293 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1838 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1838 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1838 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10921.336935 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9355.199997 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6102.562917 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 1.01% 1.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 577 38.96% 39.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 520 35.11% 75.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 129 8.71% 83.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.22% 85.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 222 14.99% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1988 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1988 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 507 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1481 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1988 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1988 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1988 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1694 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13442.148760 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11640.659125 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7340.460279 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1298 76.62% 76.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 23.32% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1694 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 946 63.88% 63.88% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 535 36.12% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1481 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1838 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1189 70.19% 70.19% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 505 29.81% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1694 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1988 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1838 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1481 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1988 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1694 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1481 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3319 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1694 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3682 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3781599 # DTB read hits -system.cpu1.dtb.read_misses 1598 # DTB read misses -system.cpu1.dtb.write_hits 2748070 # DTB write hits -system.cpu1.dtb.write_misses 240 # DTB write misses -system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3877487 # DTB read hits +system.cpu1.dtb.read_misses 1782 # DTB read misses +system.cpu1.dtb.write_hits 2737174 # DTB write hits +system.cpu1.dtb.write_misses 206 # DTB write misses +system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1169 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1170 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 242 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 67 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3783197 # DTB read accesses -system.cpu1.dtb.write_accesses 2748310 # DTB write accesses +system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3879269 # DTB read accesses +system.cpu1.dtb.write_accesses 2737380 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6529669 # DTB hits -system.cpu1.dtb.misses 1838 # DTB misses -system.cpu1.dtb.accesses 6531507 # DTB accesses +system.cpu1.dtb.hits 6614661 # DTB hits +system.cpu1.dtb.misses 1988 # DTB misses +system.cpu1.dtb.accesses 6616649 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1221,128 +1219,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 906 # Table walker walks requested -system.cpu1.itb.walker.walksShort 906 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 709 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 906 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 906 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 906 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 660 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11564.393939 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9819.657022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6526.531967 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 251 38.03% 38.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 29.55% 67.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 88 13.33% 80.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.45% 81.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 123 18.64% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 1030 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1030 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 846 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1030 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1030 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1030 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 746 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12997.319035 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11244.232149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6525.015841 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 210 28.15% 28.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.13% 28.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 183 24.53% 52.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 68 9.12% 61.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 130 17.43% 79.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 152 20.38% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 2 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 746 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 463 70.15% 70.15% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 197 29.85% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 660 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 562 75.34% 75.34% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 184 24.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 746 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 906 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 906 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1030 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1030 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 660 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 660 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1566 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17710907 # ITB inst hits -system.cpu1.itb.inst_misses 906 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1776 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 18130522 # ITB inst hits +system.cpu1.itb.inst_misses 1030 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 687 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 779 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17711813 # ITB inst accesses -system.cpu1.itb.hits 17710907 # DTB hits -system.cpu1.itb.misses 906 # DTB misses -system.cpu1.itb.accesses 17711813 # DTB accesses -system.cpu1.numCycles 143508927 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 18131552 # ITB inst accesses +system.cpu1.itb.hits 18130522 # DTB hits +system.cpu1.itb.misses 1030 # DTB misses +system.cpu1.itb.accesses 18131552 # DTB accesses +system.cpu1.numCycles 144010279 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 17104818 # Number of instructions committed -system.cpu1.committedOps 20623291 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18381943 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1289 # Number of float alu accesses -system.cpu1.num_func_calls 1997851 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2177891 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18381943 # number of integer instructions -system.cpu1.num_fp_insts 1289 # number of float instructions -system.cpu1.num_int_register_reads 34111926 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12889581 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 904 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 386 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75094286 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7377149 # number of times the CC registers were written -system.cpu1.num_mem_refs 6727087 # number of memory refs -system.cpu1.num_load_insts 3824966 # Number of load instructions -system.cpu1.num_store_insts 2902121 # Number of store instructions -system.cpu1.num_idle_cycles 136535289.121910 # Number of idle cycles -system.cpu1.num_busy_cycles 6973637.878090 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048594 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951406 # Percentage of idle cycles -system.cpu1.Branches 4285863 # Number of branches fetched -system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14489486 68.24% 68.24% # Class of executed instruction -system.cpu1.op_class::IntMult 16051 0.08% 68.31% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 956 0.00% 68.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.32% # Class of executed instruction -system.cpu1.op_class::MemRead 3824966 18.01% 86.33% # Class of executed instruction -system.cpu1.op_class::MemWrite 2902121 13.67% 100.00% # Class of executed instruction +system.cpu1.committedInsts 17464166 # Number of instructions committed +system.cpu1.committedOps 20951836 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18623353 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1244 # Number of float alu accesses +system.cpu1.num_func_calls 2002453 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2238605 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18623353 # number of integer instructions +system.cpu1.num_fp_insts 1244 # number of float instructions +system.cpu1.num_int_register_reads 34462753 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13064497 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 984 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 76266638 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7592351 # number of times the CC registers were written +system.cpu1.num_mem_refs 6809095 # number of memory refs +system.cpu1.num_load_insts 3920028 # Number of load instructions +system.cpu1.num_store_insts 2889067 # Number of store instructions +system.cpu1.num_idle_cycles 136641410.332873 # Number of idle cycles +system.cpu1.num_busy_cycles 7368868.667127 # Number of busy cycles +system.cpu1.not_idle_fraction 0.051169 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.948831 # Percentage of idle cycles +system.cpu1.Branches 4354761 # Number of branches fetched +system.cpu1.op_class::No_OpClass 27 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14731476 68.33% 68.33% # Class of executed instruction +system.cpu1.op_class::IntMult 16530 0.08% 68.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 936 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::MemRead 3920028 18.18% 86.60% # Class of executed instruction +system.cpu1.op_class::MemWrite 2889067 13.40% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21233627 # Class of executed instruction +system.cpu1.op_class::total 21558064 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5616381 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2865516 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 500930 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3264186 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2338379 # Number of BTB hits +system.cpu2.branchPred.lookups 5764695 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2966106 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 506808 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3301109 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2388086 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.637431 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1579826 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 329229 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 72.341931 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1613052 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 330539 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1372,56 +1372,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12496 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12496 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7848 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4648 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12496 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12496 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12496 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2107 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12567.631704 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10798.757465 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6853.701577 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 615 29.19% 29.19% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1022 48.50% 77.69% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 468 22.21% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2107 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000070000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000070000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000070000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1329 63.08% 63.08% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 778 36.92% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2107 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12496 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 12898 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12898 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8122 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4776 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12898 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12898 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12898 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2175 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12233.103448 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10576.406558 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6350.387588 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::2048-4095 16 0.74% 0.74% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::4096-6143 627 28.83% 29.56% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::6144-8191 3 0.14% 29.70% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::10240-12287 777 35.72% 65.43% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::12288-14335 187 8.60% 74.02% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::14336-16383 174 8.00% 82.02% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::22528-24575 386 17.75% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-26623 5 0.23% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2175 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1361 62.57% 62.57% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 814 37.43% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2175 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12898 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12496 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2107 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12898 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2175 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2107 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14603 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2175 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 15073 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4358544 # DTB read hits -system.cpu2.dtb.read_misses 11242 # DTB read misses -system.cpu2.dtb.write_hits 3388369 # DTB write hits -system.cpu2.dtb.write_misses 1254 # DTB write misses -system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4607133 # DTB read hits +system.cpu2.dtb.read_misses 11539 # DTB read misses +system.cpu2.dtb.write_hits 3514721 # DTB write hits +system.cpu2.dtb.write_misses 1359 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1540 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_entries 1512 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch +system.cpu2.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 126 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4369786 # DTB read accesses -system.cpu2.dtb.write_accesses 3389623 # DTB write accesses +system.cpu2.dtb.perms_faults 112 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4618672 # DTB read accesses +system.cpu2.dtb.write_accesses 3516080 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7746913 # DTB hits -system.cpu2.dtb.misses 12496 # DTB misses -system.cpu2.dtb.accesses 7759409 # DTB accesses +system.cpu2.dtb.hits 8121854 # DTB hits +system.cpu2.dtb.misses 12898 # DTB misses +system.cpu2.dtb.accesses 8134752 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1451,80 +1455,81 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1368 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 246 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1122 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 900 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12559.444444 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10783.610995 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6567.445052 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 280 31.11% 31.11% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 242 26.89% 58.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 171 19.00% 77.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.56% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 202 22.44% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 900 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000055500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000055500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000055500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 655 72.78% 72.78% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 245 27.22% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 900 # Table walker page sizes translated +system.cpu2.itb.walker.walks 1355 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1355 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1103 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1355 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1355 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1355 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 885 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12701.694915 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10970.308006 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6476.484391 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 261 29.49% 29.49% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 244 27.57% 57.06% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 68 7.68% 64.75% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 134 15.14% 79.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 177 20.00% 99.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 885 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 640 72.32% 72.32% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 245 27.68% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 885 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1355 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1355 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 900 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 900 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2268 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10566039 # ITB inst hits -system.cpu2.itb.inst_misses 1368 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 885 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 885 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2240 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10827992 # ITB inst hits +system.cpu2.itb.inst_misses 1355 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 943 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 895 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1761 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1816 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10567407 # ITB inst accesses -system.cpu2.itb.hits 10566039 # DTB hits -system.cpu2.itb.misses 1368 # DTB misses -system.cpu2.itb.accesses 10567407 # DTB accesses -system.cpu2.numCycles 1381994110 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10829347 # ITB inst accesses +system.cpu2.itb.hits 10827992 # DTB hits +system.cpu2.itb.misses 1355 # DTB misses +system.cpu2.itb.accesses 10829347 # DTB accesses +system.cpu2.numCycles 1394813628 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19454188 # Number of instructions committed -system.cpu2.committedOps 23590012 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1394518 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 553 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4259350283 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 71.038386 # CPI: cycles per instruction -system.cpu2.ipc 0.014077 # IPC: instructions per cycle +system.cpu2.committedInsts 20299204 # Number of instructions committed +system.cpu2.committedOps 24561296 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1454329 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 560 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4254632682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 68.712725 # CPI: cycles per instruction +system.cpu2.ipc 0.014553 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41318295 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1340675815 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13596196 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7509425 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 305533 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8486163 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6439399 # Number of BTB hits +system.cpu2.tickCycles 42192180 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1352621448 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13267477 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7218148 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 306932 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 7331192 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6244117 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.881161 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3090908 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 15400 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 85.171920 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3106613 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16022 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1554,90 +1559,89 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 33126 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 33126 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11032 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7972 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 14122 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19004 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 831.246053 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 4468.197044 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 18648 98.13% 98.13% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 304 1.60% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 32 0.17% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 8 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19004 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6133 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11867.275395 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9714.087610 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7406.609922 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2110 34.40% 34.40% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2847 46.42% 80.83% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1040 16.96% 97.78% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 49 0.80% 98.58% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 40 0.65% 99.23% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.64% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 3 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6133 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8716832064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.261873 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.297258 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8763394564 100.53% 100.53% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 31995000 -0.37% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7342000 -0.08% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 3254000 -0.04% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1291000 -0.01% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 970500 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 493000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 640500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 281000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 70500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 112500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 18500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 49000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 6500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 10500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 28000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8716832064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1783 70.92% 70.92% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 731 29.08% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2514 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33126 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 32594 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 32594 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11131 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7720 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 13743 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 18851 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 550.607395 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 4115.669871 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 18669 99.03% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 132 0.70% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 28 0.15% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-65535 10 0.05% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 5 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 18851 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6073 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 12561.337066 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10324.019552 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7892.573788 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-16383 4743 78.10% 78.10% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1245 20.50% 98.60% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-49151 80 1.32% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6073 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8078927064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.145347 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.140537 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8125083564 100.57% 100.57% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 32811500 -0.41% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7062500 -0.09% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2662500 -0.03% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1263000 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 812000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 353000 -0.00% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 734000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 142000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 166000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 33500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 14500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 66000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 5000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 27500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8078927064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1773 69.37% 69.37% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 783 30.63% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2556 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32594 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33126 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2514 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32594 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2556 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2514 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 35640 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2556 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35150 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7551044 # DTB read hits -system.cpu3.dtb.read_misses 27915 # DTB read misses -system.cpu3.dtb.write_hits 5856516 # DTB write hits -system.cpu3.dtb.write_misses 5211 # DTB write misses -system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.dtb.read_hits 7207975 # DTB read hits +system.cpu3.dtb.read_misses 28184 # DTB read misses +system.cpu3.dtb.write_hits 5370312 # DTB write hits +system.cpu3.dtb.write_misses 4410 # DTB write misses +system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 394 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 742 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1876 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 480 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 811 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7578959 # DTB read accesses -system.cpu3.dtb.write_accesses 5861727 # DTB write accesses +system.cpu3.dtb.perms_faults 348 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7236159 # DTB read accesses +system.cpu3.dtb.write_accesses 5374722 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13407560 # DTB hits -system.cpu3.dtb.misses 33126 # DTB misses -system.cpu3.dtb.accesses 13440686 # DTB accesses +system.cpu3.dtb.hits 12578287 # DTB hits +system.cpu3.dtb.misses 32594 # DTB misses +system.cpu3.dtb.accesses 12610881 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1667,387 +1671,389 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4167 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4167 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1453 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2641 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 73 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4094 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1495.114802 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5985.882126 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3827 93.48% 93.48% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 124 3.03% 96.51% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 85 2.08% 98.58% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 26 0.64% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.29% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.15% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 5 0.12% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4094 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13262.450593 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 11104.068636 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7912.964367 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 17 1.34% 1.34% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 362 28.62% 29.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 345 27.27% 57.23% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 231 18.26% 75.49% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 10 0.79% 76.28% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 96.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 10 0.79% 97.71% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.47% 98.18% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.34% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.40% 98.74% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.45% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.32% 99.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -4725503768 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.775529 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.415678 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1058328796 22.40% 22.40% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -3669011472 77.64% 100.04% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1338500 -0.03% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 422000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 76000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -4725503768 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 861 72.23% 72.23% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 331 27.77% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1192 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4409 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4409 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1513 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2804 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 92 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4317 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1474.635163 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 6438.514221 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 4058 94.00% 94.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.59% 96.59% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 78 1.81% 98.40% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 36 0.83% 99.24% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.28% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.14% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 4 0.09% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.09% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4317 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1329 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13040.632054 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 10790.250081 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7776.712895 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.81% 1.81% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 30.32% 32.13% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 359 27.01% 59.14% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 209 15.73% 74.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 19 1.43% 76.30% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 282 21.22% 97.52% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 11 0.83% 98.34% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 1 0.08% 98.42% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 9 0.68% 99.17% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 7 0.53% 99.70% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.23% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1329 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8082078064 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 1.066049 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 536728704 -6.64% -6.64% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -8620989268 106.67% 100.03% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1669000 -0.02% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 344000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 120000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 49500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8082078064 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 894 72.27% 72.27% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 343 27.73% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1237 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4167 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4167 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4409 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4409 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1192 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1192 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5359 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9936571 # ITB inst hits -system.cpu3.itb.inst_misses 4167 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1237 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1237 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5646 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9814748 # ITB inst hits +system.cpu3.itb.inst_misses 4409 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1221 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1248 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 718 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 724 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9940738 # ITB inst accesses -system.cpu3.itb.hits 9936571 # DTB hits -system.cpu3.itb.misses 4167 # DTB misses -system.cpu3.itb.accesses 9940738 # DTB accesses -system.cpu3.numCycles 55573485 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9819157 # ITB inst accesses +system.cpu3.itb.hits 9814748 # DTB hits +system.cpu3.itb.misses 4409 # DTB misses +system.cpu3.itb.accesses 9819157 # DTB accesses +system.cpu3.numCycles 57366661 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20863261 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 54294907 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13596196 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9530307 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32292568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1579965 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 69120 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 268 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 137847 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 66642 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 261 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9935560 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 207453 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2022 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54221093 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.209618 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.343030 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20761268 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52178877 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13267477 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9350730 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 33698249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1591212 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 69410 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 1107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 256 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 135306 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 74302 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 555 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9813722 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 210476 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2135 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 55536037 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.135538 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.278414 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39652063 73.13% 73.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1860834 3.43% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1199577 2.21% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3689809 6.81% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 944481 1.74% 87.32% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 637799 1.18% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2980778 5.50% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 640190 1.18% 95.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2615562 4.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 41384973 74.52% 74.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1837710 3.31% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1169547 2.11% 79.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3702482 6.67% 86.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 911101 1.64% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 554699 1.00% 89.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2918405 5.25% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 606250 1.09% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2450870 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54221093 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.244653 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.976993 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14541124 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29923428 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 8020267 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1031030 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 705051 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1065595 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 86058 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 47410230 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276975 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 705051 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15074857 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 2997482 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21287118 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8510425 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5645953 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45500627 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1126128 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 117998 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4001017 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 47247848 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 209204758 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 51266498 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3571 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39476281 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7771567 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 731786 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 677453 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5778610 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 8053628 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6456539 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1175060 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1664059 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43783527 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 535809 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41699371 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 53091 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6234373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14300280 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 56558 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54221093 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.769062 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.467188 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 55536037 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.231275 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.909568 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14514304 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31619877 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7786036 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 908366 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 707244 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 976635 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 89470 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 44785495 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 293014 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 707244 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15002070 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3712166 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21623767 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8198323 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6292235 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 42920389 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 988 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 999285 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 100726 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4827959 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44612381 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 197148279 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 47945794 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3725 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 37230904 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7381477 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 716136 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 666620 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5136604 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7692057 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 5940620 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1092936 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1536247 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41290259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 501894 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39299013 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 52056 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 5966024 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13660779 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 53087 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 55536037 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.707631 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.411142 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 37844395 69.80% 69.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5386682 9.93% 79.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4110296 7.58% 87.31% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3372256 6.22% 93.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1382084 2.55% 96.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 838917 1.55% 97.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 889664 1.64% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 259968 0.48% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 136831 0.25% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 39933168 71.90% 71.90% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5154759 9.28% 81.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3998218 7.20% 88.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3241689 5.84% 94.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1260306 2.27% 96.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 769738 1.39% 97.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 826217 1.49% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 240001 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 111941 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54221093 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 55536037 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 63437 9.96% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 290906 45.69% 55.65% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 282359 44.35% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 56634 9.59% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 279182 47.28% 56.87% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 254722 43.13% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27741162 66.53% 66.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 30355 0.07% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7771642 18.64% 85.24% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 6153835 14.76% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 79 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26205156 66.68% 66.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 29936 0.08% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2339 0.01% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7421328 18.88% 85.65% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5640175 14.35% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41699371 # Type of FU issued -system.cpu3.iq.rate 0.750347 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 636702 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015269 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 138301991 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 50577353 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40524265 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 7637 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4163 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3346 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 42331916 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4092 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 178799 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 39299013 # Type of FU issued +system.cpu3.iq.rate 0.685050 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 590538 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015027 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 134768668 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 47782568 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 38141743 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 7989 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4328 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3477 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 39885201 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4271 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 170012 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1221804 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1431 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28394 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 619889 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1165546 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1325 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29357 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 600603 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 105799 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 48648 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 108801 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 44606 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 705051 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2546149 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 337754 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 44384176 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 73225 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 8053628 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6456539 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 278302 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 24620 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 307122 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28394 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 141723 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 123945 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 265668 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 41365560 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7637563 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 300776 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 707244 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3069413 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 520763 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 41839488 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 76423 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7692057 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 5940620 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 259410 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22603 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 492210 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29357 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 139025 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 123161 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 262186 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 38971879 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7290710 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 294612 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 64840 # number of nop insts executed -system.cpu3.iew.exec_refs 13731746 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7566030 # Number of branches executed -system.cpu3.iew.exec_stores 6094183 # Number of stores executed -system.cpu3.iew.exec_rate 0.744340 # Inst execution rate -system.cpu3.iew.wb_sent 41063512 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40527611 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21306307 # num instructions producing a value -system.cpu3.iew.wb_consumers 37726918 # num instructions consuming a value +system.cpu3.iew.exec_nop 47335 # number of nop insts executed +system.cpu3.iew.exec_refs 12872001 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7242885 # Number of branches executed +system.cpu3.iew.exec_stores 5581291 # Number of stores executed +system.cpu3.iew.exec_rate 0.679347 # Inst execution rate +system.cpu3.iew.wb_sent 38686705 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 38145220 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 19984457 # num instructions producing a value +system.cpu3.iew.wb_consumers 34832102 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.729262 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.564751 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.664937 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.573737 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 6255806 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 479251 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 220583 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 52905057 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.720581 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.620547 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 5981270 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 448807 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 218548 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 54250638 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.660854 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.552983 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38385903 72.56% 72.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6395220 12.09% 84.64% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3197776 6.04% 90.69% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1426680 2.70% 93.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 782047 1.48% 94.86% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 543081 1.03% 95.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 967847 1.83% 97.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 251119 0.47% 98.19% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 955384 1.81% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 40430906 74.53% 74.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6113695 11.27% 85.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3127574 5.77% 91.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1326177 2.44% 94.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 716812 1.32% 95.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 505346 0.93% 96.26% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 950559 1.75% 98.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 229517 0.42% 98.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 850052 1.57% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 52905057 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31237505 # Number of instructions committed -system.cpu3.commit.committedOps 38122392 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 54250638 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29358701 # Number of instructions committed +system.cpu3.commit.committedOps 35851741 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12668474 # Number of memory references committed -system.cpu3.commit.loads 6831824 # Number of loads committed -system.cpu3.commit.membars 186001 # Number of memory barriers committed -system.cpu3.commit.branches 7139918 # Number of branches committed -system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 33267854 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1244626 # Number of function calls committed. +system.cpu3.commit.refs 11866528 # Number of memory references committed +system.cpu3.commit.loads 6526511 # Number of loads committed +system.cpu3.commit.membars 173804 # Number of memory barriers committed +system.cpu3.commit.branches 6837387 # Number of branches committed +system.cpu3.commit.fp_insts 3456 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 31324780 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1241793 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25422255 66.69% 66.69% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 29353 0.08% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2310 0.01% 66.77% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6831824 17.92% 84.69% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5836650 15.31% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23953965 66.81% 66.81% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 28909 0.08% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2339 0.01% 66.90% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.90% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.90% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.90% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6526511 18.20% 85.11% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5340017 14.89% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 38122392 # Class of committed instruction -system.cpu3.commit.bw_lim_events 955384 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90746167 # The number of ROB reads -system.cpu3.rob.rob_writes 90074886 # The number of ROB writes -system.cpu3.timesIdled 219461 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1352392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161729815 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31200076 # Number of Instructions Simulated -system.cpu3.committedOps 38084963 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.781197 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.781197 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.561420 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.561420 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 45423777 # number of integer regfile reads -system.cpu3.int_regfile_writes 25365434 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14212 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12005 # number of floating regfile writes -system.cpu3.cc_regfile_reads 145868338 # number of cc regfile reads -system.cpu3.cc_regfile_writes 16008509 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75068874 # number of misc regfile reads -system.cpu3.misc_regfile_writes 356547 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30152 # Transaction distribution -system.iobus.trans_dist::ReadResp 30152 # Transaction distribution +system.cpu3.commit.op_class_0::total 35851741 # Class of committed instruction +system.cpu3.commit.bw_lim_events 850052 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 89574127 # The number of ROB reads +system.cpu3.rob.rob_writes 84953819 # The number of ROB writes +system.cpu3.timesIdled 222816 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1830624 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161214707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 29333089 # Number of Instructions Simulated +system.cpu3.committedOps 35826129 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.955698 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.955698 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.511326 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.511326 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42472744 # number of integer regfile reads +system.cpu3.int_regfile_writes 24152717 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14290 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12064 # number of floating regfile writes +system.cpu3.cc_regfile_reads 137731283 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14845540 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75477983 # number of misc regfile reads +system.cpu3.misc_regfile_writes 336291 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution system.iobus.trans_dist::WriteResp 59010 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) @@ -2072,9 +2078,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2097,18 +2103,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 24223000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 22360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2116,76 +2122,76 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3278000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18813000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 19060000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 72446830 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 78461015 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50749000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 48730000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001763 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248545825009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001763 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062610 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062610 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 1.005075 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 249186259009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005075 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062817 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062817 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1650232916 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1650232916 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles -system.iocache.overall_miss_latency::total 16046914 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 17563919 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17563919 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1966288096 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1966288096 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 17563919 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 17563919 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 17563919 # number of overall miss cycles +system.iocache.overall_miss_latency::total 17563919 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45556.341542 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 45556.341542 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 72940.518182 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 70537.827309 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 70537.827309 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54324.854151 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 54324.854151 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 70537.827309 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 70537.827309 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2194,404 +2200,418 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 135 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 135 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951032916 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 951032916 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9296914 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.613636 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68008.646739 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68008.646739 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 10163919 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10163919 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1206938096 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1206938096 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 10163919 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10163919 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 10163919 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10163919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68675.128378 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68675.128378 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79471.791401 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79471.791401 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 101351 # number of replacements -system.l2c.tags.tagsinuse 65107.437503 # Cycle average of tags in use -system.l2c.tags.total_refs 5159062 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166512 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.983124 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79184308500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48838.010407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902867 # Average occupied blocks per requestor +system.l2c.tags.replacements 103711 # number of replacements +system.l2c.tags.tagsinuse 65095.024716 # Cycle average of tags in use +system.l2c.tags.total_refs 5145934 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168963 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.455981 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 80077044000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48951.707616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971864 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4685.718264 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1889.035593 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 795.990767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 850.885557 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 18.207428 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2675.377352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 739.764762 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 57.652959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2556.556001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1997.335453 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.745209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4249.334624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2262.984305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 905.000363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 870.835112 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.993332 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2120.702185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 746.628994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 47.189745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3231.570243 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1686.139222 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.746944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071498 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.012146 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012983 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000278 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.040823 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.011288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000880 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.039010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.030477 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993461 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65101 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2291 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8090 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54680 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993362 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45578118 # Number of tag accesses -system.l2c.tags.data_accesses 45578118 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4244 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 674 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13130 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1192 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4312 # number of ReadReq hits -system.l2c.ReadReq_hits::total 47143 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 690898 # number of Writeback hits -system.l2c.Writeback_hits::total 690898 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 6 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 27 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 51 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 67048 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 26358 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44381 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158764 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 736580 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 206983 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 474034 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 536634 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1954231 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 223898 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 65729 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 89672 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 143158 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 522457 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4244 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 736580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 290946 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 674 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 206983 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 86706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 13130 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 1192 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 474034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 116030 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 20158 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 4312 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 536634 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 187539 # number of demand (read+write) hits -system.l2c.demand_hits::total 2682595 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4244 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2185 # number of overall hits -system.l2c.overall_hits::cpu0.inst 736580 # number of overall hits -system.l2c.overall_hits::cpu0.data 290946 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1248 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 674 # number of overall hits -system.l2c.overall_hits::cpu1.inst 206983 # number of overall hits -system.l2c.overall_hits::cpu1.data 86706 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 13130 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 1192 # number of overall hits -system.l2c.overall_hits::cpu2.inst 474034 # number of overall hits -system.l2c.overall_hits::cpu2.data 116030 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 20158 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 4312 # number of overall hits -system.l2c.overall_hits::cpu3.inst 536634 # number of overall hits -system.l2c.overall_hits::cpu3.data 187539 # number of overall hits -system.l2c.overall_hits::total 2682595 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.064840 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.034530 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013809 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000320 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032359 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.011393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000720 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.049310 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.025728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993271 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 64 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55295 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45476650 # Number of tag accesses +system.l2c.tags.data_accesses 45476650 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4171 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2069 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1847 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 966 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 13780 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1202 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 4342 # number of ReadReq hits +system.l2c.ReadReq_hits::total 48567 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 692075 # number of Writeback hits +system.l2c.Writeback_hits::total 692075 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.950318 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.589744 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.304348 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.304348 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.398967 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.470387 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.496166 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.268654 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006716 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034206 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019155 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029880 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016304 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.138574 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002245 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.170190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003111 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.207689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035595 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.138574 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002245 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.170190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003111 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.207689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035595 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 127536.842105 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70780.303030 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70757.914339 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70764.075067 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70765.932102 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 70928.571429 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70928.571429 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118895.508057 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117375.797227 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122572.194672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120433.389841 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122882.195600 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121438.719750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122331.723437 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127784.584514 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124705.989732 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119343.661875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117746.878569 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123036.141287 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121127.374296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119343.661875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117746.878569 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123036.141287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121127.374296 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154026.872737 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 176544.019054 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191384.875445 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 179045.536774 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154747.096995 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 174221.257143 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188574.021299 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 176989.298497 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154350.360485 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175532.161705 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 190143.571571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 178138.191352 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75713 # Transaction distribution +system.membus.trans_dist::ReadResp 76298 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::Writeback 129126 # Transaction distribution -system.membus.trans_dist::CleanEvict 8500 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4529 # Transaction distribution +system.membus.trans_dist::Writeback 131166 # Transaction distribution +system.membus.trans_dist::CleanEvict 8718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4536 # Transaction distribution -system.membus.trans_dist::ReadExReq 135907 # Transaction distribution -system.membus.trans_dist::ReadExResp 135907 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35599 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4555 # Transaction distribution +system.membus.trans_dist::ReadExReq 137947 # Transaction distribution +system.membus.trans_dist::ReadExResp 137947 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36184 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 588153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 488332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 595784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 704697 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16953404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17116529 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19438129 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 335 # Total snoops (count) -system.membus.snoop_fanout::samples 417709 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17254780 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17417905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19738609 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 305 # Total snoops (count) +system.membus.snoop_fanout::samples 422679 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 417709 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 422679 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 417709 # Request fanout histogram -system.membus.reqLayer0.occupancy 57005500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 422679 # Request fanout histogram +system.membus.reqLayer0.occupancy 54961500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 697500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 673000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 504943941 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 481696064 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 667734518 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 584907455 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 25122086 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 27319765 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2904,53 +2936,59 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 111495 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2623751 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5650262 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2839838 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 45471 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 619 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 619 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 112063 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2626235 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 761523 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2094648 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2804 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296447 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296447 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1975500 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 536772 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5920920 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617534 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26086 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99400 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8663940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126461880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97725369 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 173572 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224403669 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 129912 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5870347 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.031302 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.174132 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 760987 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2076983 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2848 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2870 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296422 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296422 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1976439 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537735 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5908570 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617393 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8653114 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126520888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861689 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 178096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224603385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 193657 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5938870 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.020066 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.140226 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5686595 96.87% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 183752 3.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5819701 97.99% 97.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 119169 2.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5870347 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2188688500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5938870 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2186534999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1847107273 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1866037017 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767774788 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 758288292 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10846487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11457495 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47373752 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47843740 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8b2102f6a..b05a1c47b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804117 # Number of seconds simulated -sim_ticks 2804116777000 # Number of ticks simulated -final_tick 2804116777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823216 # Number of seconds simulated +sim_ticks 2823215630500 # Number of ticks simulated +final_tick 2823215630500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79056 # Simulator instruction rate (inst/s) -host_op_rate 95953 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1895501031 # Simulator tick rate (ticks/s) -host_mem_usage 624156 # Number of bytes of host memory used -host_seconds 1479.35 # Real time elapsed on the host -sim_insts 116952036 # Number of instructions simulated -sim_ops 141948815 # Number of ops (including micro ops) simulated +host_inst_rate 103983 # Simulator instruction rate (inst/s) +host_op_rate 126208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2510129357 # Simulator tick rate (ticks/s) +host_mem_usage 634500 # Number of bytes of host memory used +host_seconds 1124.73 # Real time elapsed on the host +sim_insts 116952239 # Number of instructions simulated +sim_ops 141949733 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 4480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 3840 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 698944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4896096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 676224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4916296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 675712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5138656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 695680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4658888 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11197544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 698944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 676224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1375168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8445824 # Number of bytes written to this memory +system.physmem.bytes_read::total 11177960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 675712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 695680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1371392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8449664 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8463348 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 70 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8467188 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 60 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 70 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76819 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 72797 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175482 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131966 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175176 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132026 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136347 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136407 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 249256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1746039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 241154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1753242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3993252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 249256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 241154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3011937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6247 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 239341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1820143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 246414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1650206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3959301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 239341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 246414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 485755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2992922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3018187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3011937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2992922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 249256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1752285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 241154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1753245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7011438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175483 # Number of read requests accepted -system.physmem.writeReqs 136347 # Number of write requests accepted -system.physmem.readBursts 175483 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136347 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11221120 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue -system.physmem.bytesWritten 8475904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11197608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8463348 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3889 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40841 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11242 # Per bank write bursts -system.physmem.perBankRdBursts::1 11247 # Per bank write bursts -system.physmem.perBankRdBursts::2 11589 # Per bank write bursts -system.physmem.perBankRdBursts::3 11122 # Per bank write bursts -system.physmem.perBankRdBursts::4 11335 # Per bank write bursts -system.physmem.perBankRdBursts::5 11409 # Per bank write bursts -system.physmem.perBankRdBursts::6 11590 # Per bank write bursts -system.physmem.perBankRdBursts::7 11844 # Per bank write bursts -system.physmem.perBankRdBursts::8 10538 # Per bank write bursts -system.physmem.perBankRdBursts::9 10661 # Per bank write bursts -system.physmem.perBankRdBursts::10 10504 # Per bank write bursts -system.physmem.perBankRdBursts::11 9563 # Per bank write bursts -system.physmem.perBankRdBursts::12 10483 # Per bank write bursts -system.physmem.perBankRdBursts::13 10932 # Per bank write bursts -system.physmem.perBankRdBursts::14 10755 # Per bank write bursts -system.physmem.perBankRdBursts::15 10516 # Per bank write bursts -system.physmem.perBankWrBursts::0 8424 # Per bank write bursts -system.physmem.perBankWrBursts::1 8579 # Per bank write bursts -system.physmem.perBankWrBursts::2 8987 # Per bank write bursts -system.physmem.perBankWrBursts::3 8481 # Per bank write bursts -system.physmem.perBankWrBursts::4 8341 # Per bank write bursts -system.physmem.perBankWrBursts::5 8592 # Per bank write bursts -system.physmem.perBankWrBursts::6 8708 # Per bank write bursts -system.physmem.perBankWrBursts::7 8869 # Per bank write bursts -system.physmem.perBankWrBursts::8 8028 # Per bank write bursts -system.physmem.perBankWrBursts::9 8030 # Per bank write bursts -system.physmem.perBankWrBursts::10 7878 # Per bank write bursts -system.physmem.perBankWrBursts::11 7235 # Per bank write bursts -system.physmem.perBankWrBursts::12 7993 # Per bank write bursts -system.physmem.perBankWrBursts::13 8331 # Per bank write bursts -system.physmem.perBankWrBursts::14 8147 # Per bank write bursts -system.physmem.perBankWrBursts::15 7813 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 239341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1826347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 246414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1650209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6958430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175177 # Number of read requests accepted +system.physmem.writeReqs 136407 # Number of write requests accepted +system.physmem.readBursts 175177 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136407 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11201984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8480320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11178024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8467188 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40863 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11773 # Per bank write bursts +system.physmem.perBankRdBursts::1 10998 # Per bank write bursts +system.physmem.perBankRdBursts::2 11169 # Per bank write bursts +system.physmem.perBankRdBursts::3 10855 # Per bank write bursts +system.physmem.perBankRdBursts::4 11706 # Per bank write bursts +system.physmem.perBankRdBursts::5 11087 # Per bank write bursts +system.physmem.perBankRdBursts::6 11923 # Per bank write bursts +system.physmem.perBankRdBursts::7 11611 # Per bank write bursts +system.physmem.perBankRdBursts::8 10970 # Per bank write bursts +system.physmem.perBankRdBursts::9 11831 # Per bank write bursts +system.physmem.perBankRdBursts::10 10190 # Per bank write bursts +system.physmem.perBankRdBursts::11 9677 # Per bank write bursts +system.physmem.perBankRdBursts::12 10224 # Per bank write bursts +system.physmem.perBankRdBursts::13 10941 # Per bank write bursts +system.physmem.perBankRdBursts::14 10213 # Per bank write bursts +system.physmem.perBankRdBursts::15 9863 # Per bank write bursts +system.physmem.perBankWrBursts::0 8674 # Per bank write bursts +system.physmem.perBankWrBursts::1 8377 # Per bank write bursts +system.physmem.perBankWrBursts::2 8725 # Per bank write bursts +system.physmem.perBankWrBursts::3 8463 # Per bank write bursts +system.physmem.perBankWrBursts::4 8546 # Per bank write bursts +system.physmem.perBankWrBursts::5 8273 # Per bank write bursts +system.physmem.perBankWrBursts::6 8696 # Per bank write bursts +system.physmem.perBankWrBursts::7 8627 # Per bank write bursts +system.physmem.perBankWrBursts::8 8420 # Per bank write bursts +system.physmem.perBankWrBursts::9 9181 # Per bank write bursts +system.physmem.perBankWrBursts::10 7887 # Per bank write bursts +system.physmem.perBankWrBursts::11 7530 # Per bank write bursts +system.physmem.perBankWrBursts::12 7884 # Per bank write bursts +system.physmem.perBankWrBursts::13 8402 # Per bank write bursts +system.physmem.perBankWrBursts::14 7675 # Per bank write bursts +system.physmem.perBankWrBursts::15 7145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2804116613000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2823215466500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174927 # Read request sizes (log2) +system.physmem.readPktSize::6 174621 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131966 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 132026 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -161,175 +161,176 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.152399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.671137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.237503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24321 37.43% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15991 24.61% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6608 10.17% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3730 5.74% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2732 4.20% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1666 2.56% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1104 1.70% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1133 1.74% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7689 11.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64974 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6726 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.057835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 476.710834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6724 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 95 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 23 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.586729 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.315744 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.746281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25059 38.02% 38.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16073 24.38% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6703 10.17% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3821 5.80% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2972 4.51% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 2.43% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1035 1.57% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1073 1.63% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7583 11.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65918 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6682 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.191410 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 482.907115 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6680 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6726 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6726 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.690158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.212427 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.515810 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6682 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.830141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.245831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.832578 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 4 0.06% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.10% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.15% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5748 85.46% 86.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 2.26% 88.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 195 2.90% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 73 1.09% 92.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 81 1.20% 93.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 162 2.41% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.42% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.16% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.25% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 154 2.29% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6726 # Writes before turning the bus around for reads -system.physmem.totQLat 2656155250 # Total ticks spent queuing -system.physmem.totMemAccLat 5943592750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 876650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15149.38 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33899.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::4-7 5 0.07% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 6 0.09% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5722 85.63% 86.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 190 2.84% 89.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 49 0.73% 89.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 177 2.65% 92.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 24 0.36% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 142 2.13% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 60 0.90% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.12% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.28% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.33% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 156 2.33% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6682 # Writes before turning the bus around for reads +system.physmem.totQLat 2754544250 # Total ticks spent queuing +system.physmem.totMemAccLat 6036375500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 875155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15737.47 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 34487.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.62 # Average write queue length when enqueuing -system.physmem.readRowHits 144959 # Number of row buffer hits during reads -system.physmem.writeRowHits 97833 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes -system.physmem.avgGap 8992452.98 # Average gap between requests -system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 259035840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 141339000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 712748400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 446996880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77780216115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614241917750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876733526705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.277905 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685339699500 # Time in different power states -system.physmem_0.memoryStateTime::REF 93635360000 # Time in different power states +system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.48 # Average write queue length when enqueuing +system.physmem.readRowHits 143966 # Number of row buffer hits during reads +system.physmem.writeRowHits 97651 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.69 # Row buffer hit rate for writes +system.physmem.avgGap 9060848.65 # Average gap between requests +system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 261734760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142811625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 710751600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 443108880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184398261840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80170181370 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1623600588000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1889727438075 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.354462 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2700891551000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94273140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25141656750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28044170250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 232167600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126678750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654825600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 411188400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76668937560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615216723500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876461794130 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.181000 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2686967028000 # Time in different power states -system.physmem_1.memoryStateTime::REF 93635360000 # Time in different power states +system.physmem_1.actEnergy 236605320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129100125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654482400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415523520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184398261840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79085731860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1624551859500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1889471564565 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.263829 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2702486818500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94273140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23514328250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26455661500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory @@ -337,27 +338,27 @@ system.realview.nvmem.bytes_inst_read::cpu0.inst 704 system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 249 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 249 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 249 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 249 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 249 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 249 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26869227 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13991642 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 524467 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16420293 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12603750 # Number of BTB hits +system.cpu0.branchPred.lookups 26494710 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13632658 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 507079 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16292260 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12421928 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.757157 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6640393 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 27621 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.244352 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6636932 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 27006 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -388,87 +389,92 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 57399 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 57399 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17473 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14797 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 25129 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 687.186241 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 4502.840845 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 31894 98.83% 98.83% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 274 0.85% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 54 0.17% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 17 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-147455 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12902 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12660.750271 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10400.452854 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8033.389954 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 9915 76.85% 76.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 2761 21.40% 98.25% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 203 1.57% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 14 0.11% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12902 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 76391677040 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.743538 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.460978 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 76311291040 99.89% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 56342500 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 12108500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4568500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2307500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1375000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 973000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1821000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 435000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 132000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 55000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 49500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 144000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 51500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 76391677040 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3747 70.16% 70.16% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1594 29.84% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5341 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 57399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 55575 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 55575 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17227 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13739 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24609 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 30966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 596.880450 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3694.116884 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 30106 97.22% 97.22% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 526 1.70% 98.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 216 0.70% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 59 0.19% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.06% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 8 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::73728-81919 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::90112-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 30966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 13159 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13974.808116 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11468.359848 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9225.442290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9399 71.43% 71.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3482 26.46% 97.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 252 1.92% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 15 0.11% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 13159 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 78337685356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.743824 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.461899 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 78259560856 99.90% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 54393500 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 11721500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4062000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2302000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1574000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 883500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 2122500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 542000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 148500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 83000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 91000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 86000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 78500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 78337685356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3804 69.37% 69.37% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1680 30.63% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5484 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 55575 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 57399 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5341 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 55575 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5484 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5341 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 62740 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 61059 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14047287 # DTB read hits -system.cpu0.dtb.read_misses 49327 # DTB read misses -system.cpu0.dtb.write_hits 10317828 # DTB write hits -system.cpu0.dtb.write_misses 8072 # DTB write misses -system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 13854800 # DTB read hits +system.cpu0.dtb.read_misses 47874 # DTB read misses +system.cpu0.dtb.write_hits 10355704 # DTB write hits +system.cpu0.dtb.write_misses 7701 # DTB write misses +system.cpu0.dtb.flush_tlb 184 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 458 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 817 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1439 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3595 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 904 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1404 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14096614 # DTB read accesses -system.cpu0.dtb.write_accesses 10325900 # DTB write accesses +system.cpu0.dtb.perms_faults 604 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13902674 # DTB read accesses +system.cpu0.dtb.write_accesses 10363405 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24365115 # DTB hits -system.cpu0.dtb.misses 57399 # DTB misses -system.cpu0.dtb.accesses 24422514 # DTB accesses +system.cpu0.dtb.hits 24210504 # DTB hits +system.cpu0.dtb.misses 55575 # DTB misses +system.cpu0.dtb.accesses 24266079 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,804 +504,802 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 7905 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7905 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2649 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5113 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 143 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 7762 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1462.316413 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6006.318105 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 7298 94.02% 94.02% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 191 2.46% 96.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 163 2.10% 98.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 55 0.71% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 14 0.18% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.21% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 3 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 7762 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2523 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13374.950456 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11026.619167 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 8136.408829 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 825 32.70% 32.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 999 39.60% 72.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 627 24.85% 97.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 0.99% 98.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 16 0.63% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 27 1.07% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2523 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 33438392080 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.922681 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.267784 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 2590170000 7.75% 7.75% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 30844665580 92.24% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2600500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 732500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 223500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 33438392080 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1818 76.39% 76.39% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 562 23.61% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2380 # Table walker page sizes translated +system.cpu0.itb.walker.walks 7385 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7385 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2112 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5086 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 187 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 7198 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1405.946096 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 5932.758848 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6773 94.10% 94.10% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 190 2.64% 96.74% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 140 1.94% 98.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 47 0.65% 99.33% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 11 0.15% 99.49% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.22% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 7 0.10% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 4 0.06% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 7198 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 14423.425123 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12051.974959 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 8640.644527 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1863 70.28% 70.28% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 733 27.65% 97.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 46 1.74% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 4 0.15% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-81919 4 0.15% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 35368734396 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.609046 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.488267 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 13831462500 39.11% 39.11% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 21534286896 60.89% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2356000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 358500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 226000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 35368734396 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1897 76.99% 76.99% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 567 23.01% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2464 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7905 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7905 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7385 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7385 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2380 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2380 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10285 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20120654 # ITB inst hits -system.cpu0.itb.inst_misses 7905 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2464 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2464 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 9849 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20114587 # ITB inst hits +system.cpu0.itb.inst_misses 7385 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 184 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 458 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2326 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2409 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20128559 # ITB inst accesses -system.cpu0.itb.hits 20120654 # DTB hits -system.cpu0.itb.misses 7905 # DTB misses -system.cpu0.itb.accesses 20128559 # DTB accesses -system.cpu0.numCycles 106084335 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20121972 # ITB inst accesses +system.cpu0.itb.hits 20114587 # DTB hits +system.cpu0.itb.misses 7385 # DTB misses +system.cpu0.itb.accesses 20121972 # DTB accesses +system.cpu0.numCycles 110325192 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39806494 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 103893687 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26869227 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19244143 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61681241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3154924 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 126092 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 416 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 201724 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 122006 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20119405 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 359114 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3525 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103520405 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.205881 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.305845 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39212585 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103212139 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26494710 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19058860 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 65985336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3113233 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 120421 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 6405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 451 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 171105 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 126190 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 599 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20113194 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 349758 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3372 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 107179671 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.158056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.272689 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 74908218 72.36% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3833241 3.70% 76.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2379626 2.30% 78.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8018936 7.75% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1633248 1.58% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1022119 0.99% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6115753 5.91% 94.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1028201 0.99% 95.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4581063 4.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 78729483 73.46% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3807123 3.55% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2383498 2.22% 79.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8002443 7.47% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1574194 1.47% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1068807 1.00% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 5993116 5.59% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1028903 0.96% 95.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4592104 4.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103520405 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253282 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.979350 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27459073 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 57640843 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15538578 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1452555 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1429102 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1871474 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 150372 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 86076544 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 485871 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1429102 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28294007 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6612104 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43619414 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16146294 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7419215 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 82346799 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3179 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1065744 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 299526 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5341738 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 84890721 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 379205899 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 91831678 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6335 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 71376559 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13514162 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1526597 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1432651 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8443957 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14885891 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11404400 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1982860 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2750757 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 79215613 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1056336 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 75904646 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90770 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11089379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24203913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112312 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103520405 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.733234 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.426738 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 107179671 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.240151 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.935526 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26754853 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 62165032 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15379945 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1465673 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1413940 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1877729 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 144724 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 85569568 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 471665 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1413940 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27587165 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6832428 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44962784 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16009333 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10373762 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 81846595 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 4353 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1036687 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 217532 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8369836 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84011397 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 377628674 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 91338127 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6488 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 71240050 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12771347 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1555221 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1457428 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8538957 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14623040 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11507305 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1985956 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2777400 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 78787811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1106001 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 75754836 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10581035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23286965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 104667 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 107179671 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.706802 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.408587 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73282727 70.79% 70.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10008412 9.67% 80.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7714570 7.45% 87.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6465771 6.25% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2339617 2.26% 96.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1485866 1.44% 97.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1511901 1.46% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 481751 0.47% 99.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 229790 0.22% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 76952421 71.80% 71.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10093269 9.42% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7647177 7.13% 88.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6479607 6.05% 94.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2319282 2.16% 96.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1495618 1.40% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1437164 1.34% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 490874 0.46% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 264259 0.25% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103520405 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 107179671 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 105175 9.45% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 531702 47.76% 57.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 476475 42.80% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 115831 10.14% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 518494 45.41% 55.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 507518 44.45% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2185 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50511411 66.55% 66.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57825 0.08% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 5 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4290 0.01% 66.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14447360 19.03% 85.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10881568 14.34% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 661 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50460858 66.61% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56393 0.07% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4124 0.01% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14247837 18.81% 85.50% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10984955 14.50% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 75904646 # Type of FU issued -system.cpu0.iq.rate 0.715512 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1113353 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014668 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 256519810 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91406915 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 73615254 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14010 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7412 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6126 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 77008290 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7524 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 368125 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 75754836 # Type of FU issued +system.cpu0.iq.rate 0.686650 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1141845 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.015073 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 259903837 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 90518348 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 73472782 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14532 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7678 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6317 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 76888224 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7796 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 347025 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2165393 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54160 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1099887 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2039138 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2398 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52342 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1081901 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 208534 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 95734 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 214750 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 120180 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1429102 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5759594 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 639314 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80435080 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 122511 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14885891 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11404400 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 549713 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 48457 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 578413 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54160 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 234602 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 214611 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 449213 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75318249 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14211760 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 529106 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1413940 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5391499 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1208860 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80024251 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 117807 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14623040 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11507305 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 566411 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44037 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1152589 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52342 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 226715 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 204902 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 431617 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75186689 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14022863 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 512703 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 163131 # number of nop insts executed -system.cpu0.iew.exec_refs 24990941 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14215836 # Number of branches executed -system.cpu0.iew.exec_stores 10779181 # Number of stores executed -system.cpu0.iew.exec_rate 0.709985 # Inst execution rate -system.cpu0.iew.wb_sent 74778323 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 73621380 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38389560 # num instructions producing a value -system.cpu0.iew.wb_consumers 66627447 # num instructions consuming a value +system.cpu0.iew.exec_nop 130439 # number of nop insts executed +system.cpu0.iew.exec_refs 24907066 # number of memory reference insts executed +system.cpu0.iew.exec_branches 13969302 # Number of branches executed +system.cpu0.iew.exec_stores 10884203 # Number of stores executed +system.cpu0.iew.exec_rate 0.681501 # Inst execution rate +system.cpu0.iew.wb_sent 74615293 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 73479099 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38405173 # num instructions producing a value +system.cpu0.iew.wb_consumers 66942375 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.693989 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576182 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.666023 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.573705 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11066735 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 944024 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 376070 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101026787 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685770 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.579563 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10599640 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1001334 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 364365 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 104754954 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.662419 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.562446 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74129277 73.38% 73.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12088684 11.97% 85.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6100635 6.04% 91.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2597407 2.57% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1266923 1.25% 95.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 835295 0.83% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1855576 1.84% 97.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 402562 0.40% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1750428 1.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 77896212 74.36% 74.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12060503 11.51% 85.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6064743 5.79% 91.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2632493 2.51% 94.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1283946 1.23% 95.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 809122 0.77% 96.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1758606 1.68% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 423456 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1825873 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101026787 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57027520 # Number of instructions committed -system.cpu0.commit.committedOps 69281156 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 104754954 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57128680 # Number of instructions committed +system.cpu0.commit.committedOps 69391674 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23025011 # Number of memory references committed -system.cpu0.commit.loads 12720498 # Number of loads committed -system.cpu0.commit.membars 379883 # Number of memory barriers committed -system.cpu0.commit.branches 13454174 # Number of branches committed -system.cpu0.commit.fp_insts 6046 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 60620890 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2622879 # Number of function calls committed. +system.cpu0.commit.refs 23009306 # Number of memory references committed +system.cpu0.commit.loads 12583902 # Number of loads committed +system.cpu0.commit.membars 411216 # Number of memory barriers committed +system.cpu0.commit.branches 13247589 # Number of branches committed +system.cpu0.commit.fp_insts 6270 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 60931939 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2625183 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46195742 66.68% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56117 0.08% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4286 0.01% 66.77% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12720498 18.36% 85.13% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10304513 14.87% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46323475 66.76% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54770 0.08% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4123 0.01% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12583902 18.13% 84.98% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10425404 15.02% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 69281156 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1750428 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 167227208 # The number of ROB reads -system.cpu0.rob.rob_writes 163193530 # The number of ROB writes -system.cpu0.timesIdled 392212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2563930 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956294180 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56928934 # Number of Instructions Simulated -system.cpu0.committedOps 69182570 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.863452 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.863452 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.536638 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.536638 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 81967291 # number of integer regfile reads -system.cpu0.int_regfile_writes 46848639 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16893 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13046 # number of floating regfile writes -system.cpu0.cc_regfile_reads 266506484 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27807772 # number of cc regfile writes -system.cpu0.misc_regfile_reads 144531551 # number of misc regfile reads -system.cpu0.misc_regfile_writes 724861 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 854304 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.982090 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42365382 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 854816 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.560820 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105251500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.651423 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 325.330668 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.364554 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.635411 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 69391674 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1825873 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 170570043 # The number of ROB reads +system.cpu0.rob.rob_writes 162411378 # The number of ROB writes +system.cpu0.timesIdled 376879 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3145521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3401736013 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57049783 # Number of Instructions Simulated +system.cpu0.committedOps 69312777 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.933841 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.933841 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.517106 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.517106 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 81821198 # number of integer regfile reads +system.cpu0.int_regfile_writes 46866866 # number of integer regfile writes +system.cpu0.fp_regfile_reads 17105 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13418 # number of floating regfile writes +system.cpu0.cc_regfile_reads 265587152 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27327021 # number of cc regfile writes +system.cpu0.misc_regfile_reads 147986326 # number of misc regfile reads +system.cpu0.misc_regfile_writes 766351 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853611 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.969012 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42370591 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 854123 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.607130 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 245.218931 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 266.750082 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.478943 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.520996 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189302421 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189302421 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12461175 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12728962 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25190137 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7687590 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8214972 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15902562 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 179184 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 184541 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 363725 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210025 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236354 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446379 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216363 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243044 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459407 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20148765 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20943934 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41092699 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20327949 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21128475 # number of overall hits -system.cpu0.dcache.overall_hits::total 41456424 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 423956 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 411527 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 835483 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1938723 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1762743 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3701466 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 85809 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 99027 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 184836 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13675 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14161 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 25 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 39 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 64 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2362679 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2174270 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5944122500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2431141924 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2360887452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4792029376 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5248824924 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5487326952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10736151876 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016156 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016356 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015513 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015031 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015268 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.249738 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.193578 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224012 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.020303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018860 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019593 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000094 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000164 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000128 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016111 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015677 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015889 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019183 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017572 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018360 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.134584 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15352.821210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15729.332202 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72640.013933 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 68115.819328 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70382.194493 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14648.484032 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15885.591477 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15138.194637 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19716.932842 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13401.726880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16723.586430 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28204.545455 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 31527.027027 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30288.135593 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39701.845171 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36908.899169 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38293.293987 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35413.425756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34441.074085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34938.327211 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189334.968418 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192431.802794 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190951.283369 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160694.158504 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189492.531664 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173699.774395 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174896.702009 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191156.098098 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182845.715483 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1933259 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.562237 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38860881 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1933771 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.095906 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9655718500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 227.659514 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 283.902722 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.444647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.554498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999145 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1936695 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.472430 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38860636 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1937207 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.060136 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11042568500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.854540 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 214.617890 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.579794 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.419176 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42875303 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42875303 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19083138 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19777743 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38860881 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19083138 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19777743 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38860881 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19083138 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19777743 # number of overall hits -system.cpu0.icache.overall_hits::total 38860881 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1035596 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1044946 # 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number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20822689 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40941423 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051474 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050183 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050818 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051474 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050183 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050818 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051474 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050183 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13454.153920 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.719888 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13465.989857 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13465.989857 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13465.989857 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11261 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42883011 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42883011 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19112796 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19747840 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38860636 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19112796 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19747840 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38860636 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19112796 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19747840 # number of overall hits +system.cpu0.icache.overall_hits::total 38860636 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 999725 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1085355 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2085080 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 999725 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1085355 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2085080 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 999725 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1085355 # number of overall misses +system.cpu0.icache.overall_misses::total 2085080 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14134312480 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 15390349487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29524661967 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14134312480 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 15390349487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29524661967 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14134312480 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 15390349487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29524661967 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20112521 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20833195 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40945716 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20112521 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20833195 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40945716 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20112521 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20833195 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40945716 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049707 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.052097 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050923 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049707 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.052097 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050923 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049707 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.052097 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050923 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14138.200485 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14180.014361 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14159.966029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14138.200485 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14180.014361 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14159.966029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14138.200485 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14180.014361 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14159.966029 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 20835 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 589 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 782 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.118846 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.643223 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72785 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 73876 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 146661 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 72785 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 73876 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 146661 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 72785 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 73876 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 146661 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 962811 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 971070 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1933881 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 962811 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 971070 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1933881 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 962811 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 971070 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1933881 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 670 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 670 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 670 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 670 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12308964487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12437182489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 24746146976 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12308964487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12437182489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 24746146976 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12308964487 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12437182489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 24746146976 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52946500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52946500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52946500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 52946500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047235 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047235 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047235 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12796.106366 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 70586 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 77198 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 147784 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 70586 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 77198 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 147784 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 70586 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 77198 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 147784 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 929139 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1008157 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1937296 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 929139 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1008157 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1937296 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 929139 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1008157 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1937296 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 668 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 668 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 668 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 668 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12404793984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13457356489 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 25862150473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12404793984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13457356489 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 25862150473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12404793984 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13457356489 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 25862150473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86442500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86442500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86442500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 86442500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047314 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047314 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047314 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13349.612281 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13349.612281 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13349.612281 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129404.940120 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129404.940120 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27575669 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14289271 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 524894 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17274855 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12959236 # Number of BTB hits +system.cpu1.branchPred.lookups 27956882 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14656819 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 538960 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17404345 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13151851 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.017915 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6858393 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 28646 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.566481 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6863409 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29253 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1325,83 +1329,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 57029 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 57029 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18821 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 12862 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25346 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31683 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 591.216110 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3688.783466 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 31359 98.98% 98.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 255 0.80% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 48 0.15% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 10 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 7 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 58688 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58688 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18912 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13793 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25983 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 32705 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 608.026296 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3710.555117 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32390 99.04% 99.04% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 251 0.77% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 38 0.12% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 12 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31683 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12352 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12478.424547 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10246.973289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7685.568959 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3962 32.08% 32.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5577 45.15% 77.23% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2494 20.19% 97.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 102 0.83% 98.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 90 0.73% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 118 0.96% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12352 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 89696770428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.667017 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.494297 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 89674974428 99.98% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 14056500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 3500500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 2366000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 661500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 722500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 410000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 58000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 89696770428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3380 68.04% 68.04% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1588 31.96% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 4968 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 57029 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 32705 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12474 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12069.344236 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9799.859677 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7714.985856 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 4605 36.92% 36.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5236 41.98% 78.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2264 18.15% 97.04% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 177 1.42% 98.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 81 0.65% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 107 0.86% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 12474 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 91615628244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.688499 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.485401 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 91592721244 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 15376000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 3652500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 2610000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 561000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 145500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 138500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 418000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 91615628244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3400 68.01% 68.01% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1599 31.99% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 4999 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58688 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 57029 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4968 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58688 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4999 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4968 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 61997 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4999 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63687 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14318727 # DTB read hits -system.cpu1.dtb.read_misses 47357 # DTB read misses -system.cpu1.dtb.write_hits 10661439 # DTB write hits -system.cpu1.dtb.write_misses 9672 # DTB write misses -system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14526505 # DTB read hits +system.cpu1.dtb.read_misses 49054 # DTB read misses +system.cpu1.dtb.write_hits 10631798 # DTB write hits +system.cpu1.dtb.write_misses 9634 # DTB write misses +system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 459 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3458 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 745 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1189 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3274 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1336 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14366084 # DTB read accesses -system.cpu1.dtb.write_accesses 10671111 # DTB write accesses +system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14575559 # DTB read accesses +system.cpu1.dtb.write_accesses 10641432 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24980166 # DTB hits -system.cpu1.dtb.misses 57029 # DTB misses -system.cpu1.dtb.accesses 25037195 # DTB accesses +system.cpu1.dtb.hits 25158303 # DTB hits +system.cpu1.dtb.misses 58688 # DTB misses +system.cpu1.dtb.accesses 25216991 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1431,387 +1434,382 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7307 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7307 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2390 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4761 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 156 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7151 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1572.647182 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6795.072359 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 6710 93.83% 93.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 190 2.66% 96.49% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 127 1.78% 98.27% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 50 0.70% 98.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 21 0.29% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 20 0.28% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 12 0.17% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.10% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::90112-98303 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-106495 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7151 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2506 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 14007.980846 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11793.815638 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8015.636923 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 694 27.69% 27.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1049 41.86% 69.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 688 27.45% 97.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 39 1.56% 98.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 20 0.80% 99.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 13 0.52% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2506 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 33862083580 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.923542 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.266537 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2594238448 7.66% 7.66% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 31264179132 92.33% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2561000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 759000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 256500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 89500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 33862083580 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1782 75.83% 75.83% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 568 24.17% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2350 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7824 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7824 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2815 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4844 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 165 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1312.247030 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 5391.308444 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7206 94.09% 94.09% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 209 2.73% 96.81% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 155 2.02% 98.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 49 0.64% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 13 0.17% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 13 0.17% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 4 0.05% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2378 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12869.007569 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10590.567886 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8075.239006 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 829 34.86% 34.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 979 41.17% 76.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 513 21.57% 97.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 0.67% 98.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 11 0.46% 98.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 27 1.14% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2378 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 31482348100 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.924096 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.265389 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2393427520 7.60% 7.60% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 29085771080 92.39% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2580000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 481500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 88000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 31482348100 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1649 74.51% 74.51% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 564 25.49% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2213 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7307 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7307 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7824 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2350 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2350 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 9657 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20824521 # ITB inst hits -system.cpu1.itb.inst_misses 7307 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2213 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2213 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10037 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20834938 # ITB inst hits +system.cpu1.itb.inst_misses 7824 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 459 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2324 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2128 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1310 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1257 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20831828 # ITB inst accesses -system.cpu1.itb.hits 20824521 # DTB hits -system.cpu1.itb.misses 7307 # DTB misses -system.cpu1.itb.accesses 20831828 # DTB accesses -system.cpu1.numCycles 108440670 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20842762 # ITB inst accesses +system.cpu1.itb.hits 20834938 # DTB hits +system.cpu1.itb.misses 7824 # DTB misses +system.cpu1.itb.accesses 20842762 # DTB accesses +system.cpu1.numCycles 114249199 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40658841 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 107348372 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27575669 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19817629 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 63179196 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3214627 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 116865 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 337 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 214773 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 119592 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20822690 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 365691 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3329 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105904439 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.219564 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.316618 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 41440028 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108062066 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27956882 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 20015260 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 67364504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3251122 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 125092 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 348 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 238931 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 130362 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20833198 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 375306 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3528 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 110929848 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.171009 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.281658 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 76345521 72.09% 72.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3953421 3.73% 75.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2478828 2.34% 78.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8244207 7.78% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1577040 1.49% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1177168 1.11% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6267610 5.92% 94.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1171227 1.11% 95.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4689417 4.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81198239 73.20% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3985157 3.59% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2477511 2.23% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8258795 7.45% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1633809 1.47% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1136557 1.02% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6389922 5.76% 94.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1173130 1.06% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4676728 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105904439 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.254293 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.989927 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27742693 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 59209108 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15734012 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1761502 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1456830 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1964004 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 152599 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89283066 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 495711 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1456830 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28693287 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4990149 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46482214 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16541431 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7740224 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85441153 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1754 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1703174 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 185824 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5043602 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88283625 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 394169118 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95445176 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5573 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 75350045 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12933564 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1608887 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1508528 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10148655 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15129586 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11812866 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2166416 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2845057 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82323765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1155194 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79175749 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 89458 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10712710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23890163 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 105302 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105904439 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.747615 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.428343 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 110929848 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.244701 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.945845 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 28438107 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 63381229 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15870082 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1769017 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1471120 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1958077 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 156563 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89815738 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 503200 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1471120 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 29385148 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6578856 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46582606 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16681881 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 10229932 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85972606 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3235 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1759145 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 332326 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 7382577 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89179456 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 395930491 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95980229 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5368 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 75492279 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13687169 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1580321 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1483697 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10084798 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15398688 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11726928 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2180756 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2876636 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82789954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1104868 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79357586 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91701 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 11257862 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24898946 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 112169 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 110929848 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.715385 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.405643 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74038259 69.91% 69.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10747404 10.15% 80.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8120323 7.67% 87.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6768186 6.39% 94.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2459889 2.32% 96.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1534209 1.45% 97.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1518475 1.43% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 479862 0.45% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 237832 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 79077492 71.29% 71.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10621201 9.57% 80.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8213587 7.40% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6738763 6.07% 94.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2479052 2.23% 96.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1519430 1.37% 97.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1589812 1.43% 99.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 483396 0.44% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 207115 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105904439 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 110929848 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 107820 9.57% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 518879 46.05% 55.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 500179 44.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 95512 8.42% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 536739 47.33% 55.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 501765 44.25% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 152 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53114016 67.08% 67.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58553 0.07% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 2 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4284 0.01% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14709821 18.58% 85.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11288919 14.26% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 1676 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53175622 67.01% 67.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 60064 0.08% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4456 0.01% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14922442 18.80% 85.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11193322 14.10% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79175749 # Type of FU issued -system.cpu1.iq.rate 0.730130 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1126884 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014233 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 265459723 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 94235106 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76889252 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12556 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6622 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5424 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 80295719 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6762 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 344779 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79357586 # Type of FU issued +system.cpu1.iq.rate 0.694601 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1134021 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014290 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 270859048 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95198962 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77052102 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11694 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6328 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5212 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 80483666 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6265 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 368068 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2039504 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2297 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51237 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1073925 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2171413 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2447 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 53780 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1110791 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 189496 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 106526 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 197752 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 83861 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1456830 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3996467 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 749020 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83580457 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 125116 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15129586 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11812866 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 584610 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40298 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 696432 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51237 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 238658 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 209145 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 447803 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78601263 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14483577 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 517602 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1471120 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5242635 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1056196 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84025940 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131684 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15398688 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11726928 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 568087 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44365 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 998937 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 53780 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 246243 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 216797 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 463040 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78768106 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14688147 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 530926 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 101498 # number of nop insts executed -system.cpu1.iew.exec_refs 25666157 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14648718 # Number of branches executed -system.cpu1.iew.exec_stores 11182580 # Number of stores executed -system.cpu1.iew.exec_rate 0.724832 # Inst execution rate -system.cpu1.iew.wb_sent 78056908 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76894676 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40431219 # num instructions producing a value -system.cpu1.iew.wb_consumers 70987120 # num instructions consuming a value +system.cpu1.iew.exec_nop 131118 # number of nop insts executed +system.cpu1.iew.exec_refs 25774139 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14898432 # Number of branches executed +system.cpu1.iew.exec_stores 11085992 # Number of stores executed +system.cpu1.iew.exec_rate 0.689441 # Inst execution rate +system.cpu1.iew.wb_sent 78239059 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77057314 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40452895 # num instructions producing a value +system.cpu1.iew.wb_consumers 70755105 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.709094 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.569557 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.674467 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.571731 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10746753 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1049892 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 374374 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103429928 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.704076 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.589371 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11247994 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 992699 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 384482 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 108382892 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.670890 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.556432 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75071598 72.58% 72.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12660376 12.24% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6524786 6.31% 91.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2717712 2.63% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1422802 1.38% 95.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 934618 0.90% 96.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1880111 1.82% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 428884 0.41% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1789041 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80053687 73.86% 73.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12617943 11.64% 85.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6573081 6.06% 91.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2685794 2.48% 94.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1383289 1.28% 95.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 946585 0.87% 96.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1968943 1.82% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 416822 0.38% 98.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1736748 1.60% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103429928 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60079421 # Number of instructions committed -system.cpu1.commit.committedOps 72822564 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 108382892 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59978464 # Number of instructions committed +system.cpu1.commit.committedOps 72712964 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23829023 # Number of memory references committed -system.cpu1.commit.loads 13090082 # Number of loads committed -system.cpu1.commit.membars 434438 # Number of memory barriers committed -system.cpu1.commit.branches 13936997 # Number of branches committed -system.cpu1.commit.fp_insts 5382 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63857795 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2718317 # Number of function calls committed. +system.cpu1.commit.refs 23843412 # Number of memory references committed +system.cpu1.commit.loads 13227275 # Number of loads committed +system.cpu1.commit.membars 402801 # Number of memory barriers committed +system.cpu1.commit.branches 14144728 # Number of branches committed +system.cpu1.commit.fp_insts 5158 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63547368 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2716364 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48932373 67.19% 67.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 56887 0.08% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4281 0.01% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13090082 17.98% 85.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10738941 14.75% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48806787 67.12% 67.12% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58309 0.08% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4456 0.01% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13227275 18.19% 85.40% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10616137 14.60% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 72822564 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1789041 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 172463469 # The number of ROB reads -system.cpu1.rob.rob_writes 169617134 # The number of ROB writes -system.cpu1.timesIdled 388810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2536231 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2437380839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60023102 # Number of Instructions Simulated -system.cpu1.committedOps 72766245 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.806649 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.806649 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553511 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553511 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 85555118 # number of integer regfile reads -system.cpu1.int_regfile_writes 48994368 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16096 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13216 # number of floating regfile writes -system.cpu1.cc_regfile_reads 277440920 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29218779 # number of cc regfile writes -system.cpu1.misc_regfile_reads 148245272 # number of misc regfile reads -system.cpu1.misc_regfile_writes 794768 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30198 # Transaction distribution -system.iobus.trans_dist::ReadResp 30198 # Transaction distribution +system.cpu1.commit.op_class_0::total 72712964 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1736748 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 177811075 # The number of ROB reads +system.cpu1.rob.rob_writes 170472987 # The number of ROB writes +system.cpu1.timesIdled 411472 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 3319351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2020087270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 59902456 # Number of Instructions Simulated +system.cpu1.committedOps 72636956 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.907254 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.907254 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.524314 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.524314 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 85743042 # number of integer regfile reads +system.cpu1.int_regfile_writes 48986759 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16090 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13161 # number of floating regfile writes +system.cpu1.cc_regfile_reads 278464634 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29701060 # number of cc regfile writes +system.cpu1.misc_regfile_reads 152671939 # number of misc regfile reads +system.cpu1.misc_regfile_writes 753578 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1836,9 +1834,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1861,9 +1859,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1904,70 +1902,68 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187527447 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186358814 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.980586 # Cycle average of tags in use -system.iocache.tags.total_refs 29 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000796 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234074441000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.980586 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061287 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061287 # Average percentage of cache occupancy +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.069707 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 236268040000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.069707 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.066857 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.066857 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328228 # Number of tag accesses -system.iocache.tags.data_accesses 328228 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 28 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 28 # number of WriteLineReq hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36196 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36196 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses -system.iocache.demand_misses::total 249 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 249 # number of overall misses -system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30886877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30886877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4270029570 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4270029570 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30886877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30886877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30886877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30886877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28976877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28976877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697901937 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697901937 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28976877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28976877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28976877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28976877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999227 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999227 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124043.682731 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124043.682731 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117969.653277 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117969.653277 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124043.682731 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124043.682731 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124364.278970 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124364.278970 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129690.314074 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129690.314074 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124364.278970 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124364.278970 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124364.278970 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124364.278970 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1976,296 +1972,296 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36161 # number of writebacks -system.iocache.writebacks::total 36161 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36196 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36196 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18436877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18436877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460229570 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460229570 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18436877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18436877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18436877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18436877 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17326877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17326877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886701937 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886701937 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17326877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17326877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17326877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17326877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999227 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999227 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74043.682731 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74043.682731 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67969.653277 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67969.653277 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74364.278970 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74364.278970 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79690.314074 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79690.314074 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74364.278970 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74364.278970 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74364.278970 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74364.278970 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104376 # number of replacements -system.l2c.tags.tagsinuse 65128.447881 # Cycle average of tags in use -system.l2c.tags.total_refs 5130866 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169621 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.249002 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 71309274500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48546.195919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 40.752142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4832.971752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2370.323357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 46.716496 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5940.987464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3350.500506 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.740756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000622 # Average percentage of cache occupancy +system.l2c.tags.replacements 104486 # number of replacements +system.l2c.tags.tagsinuse 65102.270180 # Cycle average of tags in use +system.l2c.tags.total_refs 5137781 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169691 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.277275 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 74417430500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48932.992978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.632841 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5110.689574 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3054.335380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 49.005856 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5438.208710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2472.404533 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.746658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000681 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073745 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.036168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000713 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.090652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051125 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993781 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3268 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9040 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52500 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994644 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45389875 # Number of tag accesses -system.l2c.tags.data_accesses 45389875 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 34639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7724 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34842 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 84634 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 704468 # number of Writeback hits -system.l2c.Writeback_hits::total 704468 # number of Writeback hits +system.l2c.tags.occ_percent::cpu0.inst 0.077983 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000748 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.082980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037726 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993382 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65113 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 92 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3230 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8952 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52567 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45423392 # Number of tag accesses +system.l2c.tags.data_accesses 45423392 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 33657 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7428 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 33997 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7416 # number of ReadReq hits +system.l2c.ReadReq_hits::total 82498 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 704529 # number of Writeback hits +system.l2c.Writeback_hits::total 704529 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 84 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 83572 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 73244 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156816 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 952414 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 960356 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1912770 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 273094 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 269324 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 542418 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34639 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7724 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 952414 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 356666 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34842 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 960356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 342568 # number of demand (read+write) hits -system.l2c.demand_hits::total 2696638 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34639 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7724 # number of overall hits -system.l2c.overall_hits::cpu0.inst 952414 # number of overall hits -system.l2c.overall_hits::cpu0.data 356666 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34842 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 960356 # number of overall hits -system.l2c.overall_hits::cpu1.data 342568 # number of overall hits -system.l2c.overall_hits::total 2696638 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu1.data 43 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 89 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 44 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 75544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 80883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156427 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 919122 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 997106 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1916228 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 280073 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 262362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 542435 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 919122 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 355617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 33997 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 997106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343245 # number of demand (read+write) hits +system.l2c.demand_hits::total 2697588 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 33657 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7428 # number of overall hits +system.l2c.overall_hits::cpu0.inst 919122 # number of overall hits +system.l2c.overall_hits::cpu0.data 355617 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 33997 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7416 # number of overall hits +system.l2c.overall_hits::cpu1.inst 997106 # number of overall hits +system.l2c.overall_hits::cpu1.data 343245 # number of overall hits +system.l2c.overall_hits::total 2697588 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 60 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 70 # number of ReadReq misses -system.l2c.ReadReq_misses::total 141 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1473 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1260 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2733 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 6 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 13 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 70675 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 69701 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140376 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10270 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10574 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 20844 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6975 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 8256 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15231 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 65 # number of ReadReq misses +system.l2c.ReadReq_misses::total 126 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1353 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1475 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2828 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 5 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 10 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 73008 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 66984 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139992 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 9909 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10879 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 20788 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8402 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 6880 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 15282 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 60 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73510.338915 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73413.759018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73387.647996 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177789.591528 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177294.445966 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.489323 # 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number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1043994500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 875170000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1919164500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 7548000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1226577500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10065012500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 8021500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 1330570000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 9174109000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21811961000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 7548000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 122500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1226577500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10065012500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 8021500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 1330570000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 9174109000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21811961000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 75943997 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2631657000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2923348500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5630949497 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2255045500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2217542500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4472588000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 75943997 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4886702500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5140891000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10103537497 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001780 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000135 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001525 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.967119 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.971673 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.969489 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.227273 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.270270 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.254237 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.491464 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.453002 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472277 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010657 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.010787 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010725 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028869 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025293 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027143 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001780 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000135 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010657 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.186112 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.176918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061254 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001780 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000135 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010657 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.186112 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.176918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061254 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125800 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 124539.682540 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70764.596452 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.711864 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70774.044908 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70400 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71050 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123562.047995 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123894.347904 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 123721.048346 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123884.203616 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122373.769889 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123093.650717 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125359.570125 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128512.481645 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126777.942925 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123884.203616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123746.096439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122373.769889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.527414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 123910.475487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123884.203616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123746.096439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122373.769889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.527414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 123910.475487 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176834.901223 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179931.587370 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 177090.590213 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149054.497984 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177987.198009 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162120.777149 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162830.378861 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179087.682018 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 170136.187539 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 31797 # Transaction distribution -system.membus.trans_dist::ReadResp 68110 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131966 # Transaction distribution -system.membus.trans_dist::CleanEvict 8584 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4648 # Transaction distribution -system.membus.trans_dist::ReadExReq 138475 # Transaction distribution -system.membus.trans_dist::ReadExResp 138475 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36314 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36195 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36195 # Transaction distribution +system.membus.trans_dist::ReadResp 68067 # Transaction distribution +system.membus.trans_dist::WriteReq 27588 # Transaction distribution +system.membus.trans_dist::WriteResp 27588 # Transaction distribution +system.membus.trans_dist::Writeback 132026 # Transaction distribution +system.membus.trans_dist::CleanEvict 8663 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4641 # Transaction distribution +system.membus.trans_dist::ReadExReq 138194 # Transaction distribution +system.membus.trans_dist::ReadExResp 138194 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36271 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473652 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 581222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 690052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 580716 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108899 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108899 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 689615 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17345628 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17509597 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2315264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19824861 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 415806 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17328028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17492021 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19809141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 503 # Total snoops (count) +system.membus.snoop_fanout::samples 415635 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 415806 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 415635 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 415806 # Request fanout histogram -system.membus.reqLayer0.occupancy 95819000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 415635 # Request fanout histogram +system.membus.reqLayer0.occupancy 95974000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1718000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 923516805 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 923083346 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1018756091 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1016456858 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64465031 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64493372 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2561,56 +2557,62 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 148196 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2639888 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 836438 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2043009 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 64 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297192 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297192 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1933881 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 557898 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36195 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5760848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2679672 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 39941 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 161233 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8641694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123794112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99989277 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 60616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 278484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224122489 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 209289 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5932182 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.049498 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.216906 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 5623278 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2831878 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 48082 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 557 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 147787 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2643011 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 836563 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2046694 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2917 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 59 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2976 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296419 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296419 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1937296 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 557950 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5772132 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2677725 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 39632 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 158982 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8648471 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124011712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99951221 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 59380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 271116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224293429 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 211232 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5937467 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.022790 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.149234 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5638548 95.05% 95.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 293634 4.95% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5802151 97.72% 97.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 135316 2.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5932182 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3595734997 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5937467 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3598371995 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 244500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2902818005 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2908371640 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1328890460 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1327935857 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24804964 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24806959 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 92041633 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 91622154 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 683a782fa..a8e4ce345 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.482239 # Number of seconds simulated -sim_ticks 47482239150000 # Number of ticks simulated -final_tick 47482239150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.464182 # Number of seconds simulated +sim_ticks 47464181819000 # Number of ticks simulated +final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126606 # Simulator instruction rate (inst/s) -host_op_rate 148916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6789587746 # Simulator tick rate (ticks/s) -host_mem_usage 767628 # Number of bytes of host memory used -host_seconds 6993.39 # Real time elapsed on the host -sim_insts 885402765 # Number of instructions simulated -sim_ops 1041431052 # Number of ops (including micro ops) simulated +host_inst_rate 165089 # Simulator instruction rate (inst/s) +host_op_rate 194182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9130718670 # Simulator tick rate (ticks/s) +host_mem_usage 773696 # Number of bytes of host memory used +host_seconds 5198.30 # Real time elapsed on the host +sim_insts 858179266 # Number of instructions simulated +sim_ops 1009414094 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 88704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 71680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8153920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 42330888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14734656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 154368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 137408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2906176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 14216400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12693312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441664 # Number of bytes read from this memory -system.physmem.bytes_read::total 95929176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8153920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2906176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11060096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 76090688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory +system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 76111272 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 127405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 661433 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 230229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2147 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 45409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 222144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 198333 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6901 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1498919 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1188917 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1191491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 891510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 310319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 299405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 267328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2020317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171726 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 232931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1602508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 226886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 74342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 180196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 74342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1349757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1602942 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1602508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 891943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 310319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 299405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 267328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3623259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1498919 # Number of read requests accepted -system.physmem.writeReqs 1191491 # Number of write requests accepted -system.physmem.readBursts 1498919 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1191491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 95891200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 39616 # Total number of bytes read from write queue -system.physmem.bytesWritten 76109696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 95929176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 76111272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 619 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1350190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1349757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 144970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 791709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 226886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 74342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 285629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 180196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3069119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1274831 # Number of read requests accepted +system.physmem.writeReqs 1003591 # Number of write requests accepted +system.physmem.readBursts 1274831 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1003591 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 81546816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue +system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81587544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 64085672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 217911 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89027 # Per bank write bursts -system.physmem.perBankRdBursts::1 94433 # Per bank write bursts -system.physmem.perBankRdBursts::2 86611 # Per bank write bursts -system.physmem.perBankRdBursts::3 92371 # Per bank write bursts -system.physmem.perBankRdBursts::4 85965 # Per bank write bursts -system.physmem.perBankRdBursts::5 91989 # Per bank write bursts -system.physmem.perBankRdBursts::6 84150 # Per bank write bursts -system.physmem.perBankRdBursts::7 94780 # Per bank write bursts -system.physmem.perBankRdBursts::8 85741 # Per bank write bursts -system.physmem.perBankRdBursts::9 143775 # Per bank write bursts -system.physmem.perBankRdBursts::10 89074 # Per bank write bursts -system.physmem.perBankRdBursts::11 90853 # Per bank write bursts -system.physmem.perBankRdBursts::12 89498 # Per bank write bursts -system.physmem.perBankRdBursts::13 91267 # Per bank write bursts -system.physmem.perBankRdBursts::14 94459 # Per bank write bursts -system.physmem.perBankRdBursts::15 94307 # Per bank write bursts -system.physmem.perBankWrBursts::0 73359 # Per bank write bursts -system.physmem.perBankWrBursts::1 78327 # Per bank write bursts -system.physmem.perBankWrBursts::2 72063 # Per bank write bursts -system.physmem.perBankWrBursts::3 77110 # Per bank write bursts -system.physmem.perBankWrBursts::4 71233 # Per bank write bursts -system.physmem.perBankWrBursts::5 76219 # Per bank write bursts -system.physmem.perBankWrBursts::6 70290 # Per bank write bursts -system.physmem.perBankWrBursts::7 78154 # Per bank write bursts -system.physmem.perBankWrBursts::8 70631 # Per bank write bursts -system.physmem.perBankWrBursts::9 75804 # Per bank write bursts -system.physmem.perBankWrBursts::10 71232 # Per bank write bursts -system.physmem.perBankWrBursts::11 74262 # Per bank write bursts -system.physmem.perBankWrBursts::12 72932 # Per bank write bursts -system.physmem.perBankWrBursts::13 74472 # Per bank write bursts -system.physmem.perBankWrBursts::14 77093 # Per bank write bursts -system.physmem.perBankWrBursts::15 76033 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 221043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69298 # Per bank write bursts +system.physmem.perBankRdBursts::1 80196 # Per bank write bursts +system.physmem.perBankRdBursts::2 71590 # Per bank write bursts +system.physmem.perBankRdBursts::3 80518 # Per bank write bursts +system.physmem.perBankRdBursts::4 76240 # Per bank write bursts +system.physmem.perBankRdBursts::5 80771 # Per bank write bursts +system.physmem.perBankRdBursts::6 77164 # Per bank write bursts +system.physmem.perBankRdBursts::7 81418 # Per bank write bursts +system.physmem.perBankRdBursts::8 74880 # Per bank write bursts +system.physmem.perBankRdBursts::9 125815 # Per bank write bursts +system.physmem.perBankRdBursts::10 65333 # Per bank write bursts +system.physmem.perBankRdBursts::11 79047 # Per bank write bursts +system.physmem.perBankRdBursts::12 75605 # Per bank write bursts +system.physmem.perBankRdBursts::13 79656 # Per bank write bursts +system.physmem.perBankRdBursts::14 77605 # Per bank write bursts +system.physmem.perBankRdBursts::15 79033 # Per bank write bursts +system.physmem.perBankWrBursts::0 58028 # Per bank write bursts +system.physmem.perBankWrBursts::1 64393 # Per bank write bursts +system.physmem.perBankWrBursts::2 59641 # Per bank write bursts +system.physmem.perBankWrBursts::3 64677 # Per bank write bursts +system.physmem.perBankWrBursts::4 61513 # Per bank write bursts +system.physmem.perBankWrBursts::5 65147 # Per bank write bursts +system.physmem.perBankWrBursts::6 63058 # Per bank write bursts +system.physmem.perBankWrBursts::7 64825 # Per bank write bursts +system.physmem.perBankWrBursts::8 60547 # Per bank write bursts +system.physmem.perBankWrBursts::9 63081 # Per bank write bursts +system.physmem.perBankWrBursts::10 56749 # Per bank write bursts +system.physmem.perBankWrBursts::11 64053 # Per bank write bursts +system.physmem.perBankWrBursts::12 61964 # Per bank write bursts +system.physmem.perBankWrBursts::13 65797 # Per bank write bursts +system.physmem.perBankWrBursts::14 62586 # Per bank write bursts +system.physmem.perBankWrBursts::15 65266 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 28 # Number of times write queue was full causing retry -system.physmem.totGap 47482237279500 # Total gap between requests +system.physmem.numWrRetry 59 # Number of times write queue was full causing retry +system.physmem.totGap 47464179840500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1498889 # Read request sizes (log2) +system.physmem.readPktSize::6 1274801 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1188917 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 923724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 366189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1001017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 816238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 315854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 14624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,164 +188,166 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 19684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 43592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 74023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 79204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 77889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 78555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 85240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 78371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 74036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 290 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 70319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 65705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 58334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 84 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 913839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 188.217382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 115.370572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 246.881339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 545143 59.65% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 181104 19.82% 79.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60696 6.64% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 30627 3.35% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20207 2.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12827 1.40% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9718 1.06% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9868 1.08% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 43649 4.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 913839 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 67807 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.096303 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 333.350943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 67804 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 193 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 760858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 191.403705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 116.807820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448904 59.00% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 151841 19.96% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50675 6.66% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27026 3.55% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 17061 2.24% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11068 1.45% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8074 1.06% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8214 1.08% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 760858 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56148 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 56145 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 67807 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 67807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.538219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.057457 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.559402 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64146 94.60% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1206 1.78% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 504 0.74% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 212 0.31% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 312 0.46% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 493 0.73% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 138 0.20% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.05% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 37 0.05% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 40 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.05% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.03% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 428 0.63% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 42 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 41 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 67807 # Writes before turning the bus around for reads -system.physmem.totQLat 45254251156 # Total ticks spent queuing -system.physmem.totMemAccLat 73347376156 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7491500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30203.73 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads +system.physmem.totQLat 34002300770 # Total ticks spent queuing +system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48953.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.02 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 1205783 # Number of row buffer hits during reads -system.physmem.writeRowHits 567891 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.75 # Row buffer hit rate for writes -system.physmem.avgGap 17648699.37 # Average gap between requests -system.physmem.pageHitRate 66.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3440351880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1877176125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5610742800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3866972400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1186805359620 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27448283421000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31751192752785 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.696261 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45662122488643 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585536160000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing +system.physmem.readRowHits 1026298 # Number of row buffer hits during reads +system.physmem.writeRowHits 488335 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes +system.physmem.avgGap 20832040.70 # Average gap between requests +system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.645246 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 234575955107 # Time in different power states +system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3468270960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1892409750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6075934800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3839134320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1190698585875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27444868310250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31752151374915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.716450 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45656375341719 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585536160000 # Time in different power states +system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.668617 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 240323289781 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -376,18 +378,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 141674450 # Number of BP lookups -system.cpu0.branchPred.condPredicted 99862421 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6468001 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 105068912 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76755781 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 135703894 # Number of BP lookups +system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.052799 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16951451 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1146227 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,66 +420,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 285287 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 285287 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10160 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74871 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 285287 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 285287 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 285287 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85031 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19876.756712 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18427.446368 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12146.929549 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 81330 95.65% 95.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3040 3.58% 99.22% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 313 0.37% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 238 0.28% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 17 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 17 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85031 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 74871 88.05% 88.05% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10160 11.95% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85031 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 285287 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 277006 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 285287 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85031 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85031 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 370318 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 92463041 # DTB read hits -system.cpu0.dtb.read_misses 237707 # DTB read misses -system.cpu0.dtb.write_hits 80598198 # DTB write hits -system.cpu0.dtb.write_misses 47580 # DTB write misses +system.cpu0.dtb.read_hits 88941283 # DTB read hits +system.cpu0.dtb.read_misses 229899 # DTB read misses +system.cpu0.dtb.write_hits 77314134 # DTB write hits +system.cpu0.dtb.write_misses 47107 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37525 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1680 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10312 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10309 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92700748 # DTB read accesses -system.cpu0.dtb.write_accesses 80645778 # DTB write accesses +system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 89171182 # DTB read accesses +system.cpu0.dtb.write_accesses 77361241 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 173061239 # DTB hits -system.cpu0.dtb.misses 285287 # DTB misses -system.cpu0.dtb.accesses 173346526 # DTB accesses +system.cpu0.dtb.hits 166255417 # DTB hits +system.cpu0.dtb.misses 277006 # DTB misses +system.cpu0.dtb.accesses 166532423 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,192 +505,192 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 62168 # Table walker walks requested -system.cpu0.itb.walker.walksLong 62168 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 557 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49936 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 62168 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 62168 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 62168 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50493 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 22007.793159 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 20271.994764 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13773.268921 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 46934 92.95% 92.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2907 5.76% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 206 0.41% 99.12% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 384 0.76% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 12 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50493 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 49936 98.90% 98.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 557 1.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50493 # Table walker page sizes translated +system.cpu0.itb.walker.walks 67964 # Table walker walks requested +system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62168 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50493 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50493 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 112661 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 254201587 # ITB inst hits -system.cpu0.itb.inst_misses 62168 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 243132835 # ITB inst hits +system.cpu0.itb.inst_misses 67964 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26890 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 207950 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 254263755 # ITB inst accesses -system.cpu0.itb.hits 254201587 # DTB hits -system.cpu0.itb.misses 62168 # DTB misses -system.cpu0.itb.accesses 254263755 # DTB accesses -system.cpu0.numCycles 1026940097 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses +system.cpu0.itb.hits 243132835 # DTB hits +system.cpu0.itb.misses 67964 # DTB misses +system.cpu0.itb.accesses 243200799 # DTB accesses +system.cpu0.numCycles 1024570142 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 473675073 # Number of instructions committed -system.cpu0.committedOps 555986446 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 46253045 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4767 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93938653200 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.168026 # CPI: cycles per instruction -system.cpu0.ipc 0.461249 # IPC: instructions per cycle +system.cpu0.committedInsts 453671847 # Number of instructions committed +system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.258395 # CPI: cycles per instruction +system.cpu0.ipc 0.442792 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15947 # number of quiesce instructions executed -system.cpu0.tickCycles 756887334 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 270052763 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5859905 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.688861 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 164189310 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5860417 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.016660 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.688861 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991580 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.991580 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed +system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5606815 # number of replacements +system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 349055381 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 349055381 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 84695912 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84695912 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74803438 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74803438 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 285827 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 285827 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 206325 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 206325 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1857926 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1857926 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1831957 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1831957 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159499350 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159499350 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 159785177 # number of overall hits -system.cpu0.dcache.overall_hits::total 159785177 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3661656 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3661656 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2387103 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2387103 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 659778 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 659778 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 802996 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 802996 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167218 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 167218 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191201 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 191201 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6048759 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6048759 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6708537 # number of overall misses -system.cpu0.dcache.overall_misses::total 6708537 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54989546000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54989546000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45746153500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 45746153500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55227374500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 55227374500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2454584500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2454584500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4061452500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4061452500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2247500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2247500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 100735699500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 100735699500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 100735699500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 100735699500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88357568 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88357568 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77190541 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77190541 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 945605 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 945605 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1009321 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1009321 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2025144 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2025144 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023158 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2023158 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 165548109 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 165548109 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 166493714 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 166493714 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041441 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041441 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030925 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030925 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.697731 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.697731 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.795580 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.795580 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082571 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082571 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094506 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094506 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036538 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036538 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040293 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040293 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15017.671239 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15017.671239 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.879187 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.879187 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 68776.649572 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 68776.649572 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14678.949037 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14678.949037 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21241.795283 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21241.795283 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153315707 # 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miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16542.179531 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16542.179531 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23170.640855 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23170.640855 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 89661.776150 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 89661.776150 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15509.669270 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15509.669270 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24075.189529 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24075.189529 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16653.944966 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16653.944966 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15016.045898 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15016.045898 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19182.078399 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19182.078399 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17313.219691 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17313.219691 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,161 +699,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3953843 # number of writebacks -system.cpu0.dcache.writebacks::total 3953843 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 461349 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 461349 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 989528 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 989528 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 101 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43137 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43137 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 40 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1450877 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1450877 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1450877 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1450877 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3200307 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3200307 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1397575 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1397575 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 654192 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 654192 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 802895 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 802895 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124081 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124081 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191161 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 191161 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4597882 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4597882 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5252074 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5252074 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32791 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65643 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43347515000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43347515000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25679741500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25679741500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14396564000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14396564000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54417843000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54417843000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1641270500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1641270500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3869107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3869107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2035000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2035000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69027256500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 69027256500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83423820500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 83423820500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5925160000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5925160000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5714063000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5714063000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11639223000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11639223000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018106 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018106 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.691824 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.691824 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.795480 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.795480 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061270 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061270 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094486 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094486 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031545 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031545 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13544.798983 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13544.798983 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18374.499759 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18374.499759 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22006.634138 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22006.634138 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 67777.035602 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 67777.035602 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13227.411933 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13227.411933 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20240.043733 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20240.043733 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3758761 # number of writebacks +system.cpu0.dcache.writebacks::total 3758761 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423304 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 423304 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 954060 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 954060 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 67 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 67 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43006 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43006 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 59 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1377364 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1377364 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1377364 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1377364 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3046910 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3046910 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342761 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1342761 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 616851 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 616851 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 787614 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 787614 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185665 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 185665 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4389671 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4389671 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5006522 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5006522 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14625 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30107 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45015119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45015119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30226463500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30226463500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15766385500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15766385500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 69831148500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 69831148500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1724289500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1724289500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4281874000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4281874000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4478500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4478500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75241583000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75241583000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91007968500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 91007968500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2444404000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15012.837759 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15012.837759 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15883.976597 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15883.976597 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180694.702815 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180694.702815 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173933.489590 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173933.489590 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177310.954710 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177310.954710 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 10143465 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.926573 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 243844472 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10143977 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.038350 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29838959000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926573 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9688574 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 518120904 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 518120904 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 243844472 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 243844472 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 243844472 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 243844472 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 243844472 # number of overall hits -system.cpu0.icache.overall_hits::total 243844472 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10143987 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10143987 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10143987 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10143987 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10143987 # number of overall misses -system.cpu0.icache.overall_misses::total 10143987 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100406017500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 100406017500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 100406017500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 100406017500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 100406017500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 100406017500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 253988459 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 253988459 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 253988459 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 253988459 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 253988459 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 253988459 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039939 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039939 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039939 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039939 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039939 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039939 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.082233 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.082233 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9898.082233 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9898.082233 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 233226662 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 233226662 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 233226662 # number of overall hits +system.cpu0.icache.overall_hits::total 233226662 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9689087 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9689087 # number of overall misses +system.cpu0.icache.overall_misses::total 9689087 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100299166000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 100299166000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 242915749 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 242915749 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -864,498 +862,500 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10143987 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10143987 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10143987 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10143987 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10143987 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10143987 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95334024500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 95334024500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95334024500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 95334024500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95334024500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 95334024500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039939 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039939 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039939 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9398.082283 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9689087 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9689087 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9689087 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9689087 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9689087 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9689087 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95454623000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 95454623000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95454623000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 95454623000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95454623000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 95454623000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039887 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039887 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039887 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.766529 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7957449 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7958709 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1099 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7463777 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7463951 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 154 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1036699 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2852729 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16231.938482 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 28072062 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2868819 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.785233 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 27361359000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6837.547665 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 84.005962 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.461189 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5084.590207 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3169.997386 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 963.336073 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.417331 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005127 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005643 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.310339 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.193481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058797 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.990719 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1316 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2596 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5686 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5177 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080322 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 536564472 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 536564472 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494323 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 145712 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 640035 # 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mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131699 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247254 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220723 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220723 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178383 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26975.398363 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45363.741930 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20262.523814 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20262.523814 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15383.814337 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15383.814337 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 283999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 283999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42293.793764 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42293.793764 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24227.493856 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27323.244934 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27323.244934 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 78134.775269 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 78134.775269 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27943.350118 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32502.371679 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172689.838675 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117792.238167 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166432.743821 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166432.743821 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169558.383986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 131341.548311 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 878258 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15087550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32852 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 7538926 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 15047066 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 979875 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 473443 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 345382 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 491005 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1529585 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1182209 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10143987 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6286308 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 908183 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 801455 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30533828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18915495 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 338792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1107688 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 50895803 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 652561728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 589425738 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1225096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4043800 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1247256362 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11033818 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 44172113 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.260955 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.439155 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 32645184 73.90% 73.90% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 11526929 26.10% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 44172113 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 20686801483 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 184431489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15296388050 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8393036752 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 185661487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 602239946 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 126920633 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90998639 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5685011 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 95306954 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 70103943 # Number of BTB hits +system.cpu1.branchPred.lookups 123013748 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.555958 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14523133 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 944517 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1385,61 +1385,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 273163 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 273163 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10101 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83297 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 273163 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 273163 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 273163 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 93398 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20769.759524 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.534327 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16072.129923 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 92090 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1102 1.18% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 44 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 68 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 64 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 93398 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1497259648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1497259648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1497259648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 83297 89.18% 89.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10101 10.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 93398 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 273163 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 261280 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 273163 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93398 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93398 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 366561 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80454143 # DTB read hits -system.cpu1.dtb.read_misses 224980 # DTB read misses -system.cpu1.dtb.write_hits 71458601 # DTB write hits -system.cpu1.dtb.write_misses 48183 # DTB write misses +system.cpu1.dtb.read_hits 79147380 # DTB read hits +system.cpu1.dtb.read_misses 216729 # DTB read misses +system.cpu1.dtb.write_hits 70165250 # DTB write hits +system.cpu1.dtb.write_misses 44551 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37844 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 998 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7832 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11981 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80679123 # DTB read accesses -system.cpu1.dtb.write_accesses 71506784 # DTB write accesses +system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79364109 # DTB read accesses +system.cpu1.dtb.write_accesses 70209801 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151912744 # DTB hits -system.cpu1.dtb.misses 273163 # DTB misses -system.cpu1.dtb.accesses 152185907 # DTB accesses +system.cpu1.dtb.hits 149312630 # DTB hits +system.cpu1.dtb.misses 261280 # DTB misses +system.cpu1.dtb.accesses 149573910 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1469,187 +1470,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69906 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69906 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 595 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61795 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 69906 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69906 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69906 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 62390 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23626.751082 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21282.847568 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17788.570372 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 60952 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1278 2.05% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.13% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 62390 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1498102148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1498102148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1498102148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61795 99.05% 99.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 595 0.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62390 # Table walker page sizes translated +system.cpu1.itb.walker.walks 64423 # Table walker walks requested +system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69906 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69906 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62390 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62390 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 132296 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 226287653 # ITB inst hits -system.cpu1.itb.inst_misses 69906 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 219650463 # ITB inst hits +system.cpu1.itb.inst_misses 64423 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26941 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 214530 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 226357559 # ITB inst accesses -system.cpu1.itb.hits 226287653 # DTB hits -system.cpu1.itb.misses 69906 # DTB misses -system.cpu1.itb.accesses 226357559 # DTB accesses -system.cpu1.numCycles 843613035 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses +system.cpu1.itb.hits 219650463 # DTB hits +system.cpu1.itb.misses 64423 # DTB misses +system.cpu1.itb.accesses 219714886 # DTB accesses +system.cpu1.numCycles 870330668 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 411727692 # Number of instructions committed -system.cpu1.committedOps 485444606 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 45963671 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5033 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94121734017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.048959 # CPI: cycles per instruction -system.cpu1.ipc 0.488053 # IPC: instructions per cycle +system.cpu1.committedInsts 404507419 # Number of instructions committed +system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.151581 # CPI: cycles per instruction +system.cpu1.ipc 0.464774 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5855 # number of quiesce instructions executed -system.cpu1.tickCycles 670689322 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 172923713 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4998697 # number of replacements -system.cpu1.dcache.tags.tagsinuse 442.736384 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144280355 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4999208 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.860643 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8387679361000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.736384 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.864720 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.864720 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306336541 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306336541 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73634827 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73634827 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66559153 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66559153 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 217159 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 217159 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 114949 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 114949 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1666179 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1666179 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1632337 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1632337 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 140193980 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 140193980 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 140411139 # number of overall hits -system.cpu1.dcache.overall_hits::total 140411139 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3169592 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3169592 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2202884 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2202884 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634590 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 634590 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446274 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 446274 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 155480 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 155480 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187648 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187648 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5372476 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5372476 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6007066 # number of overall misses -system.cpu1.dcache.overall_misses::total 6007066 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46997405500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 46997405500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36924614000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 36924614000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13123924500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 13123924500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2384254000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2384254000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3955578000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3955578000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3296000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3296000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 83922019500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 83922019500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 83922019500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 83922019500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76804419 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76804419 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 68762037 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68762037 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 851749 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 851749 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 561223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 561223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1821659 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1821659 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1819985 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1819985 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 145566456 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 145566456 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146418205 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146418205 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041268 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041268 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745043 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745043 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.795181 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.795181 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103104 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103104 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036907 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036907 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041027 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041027 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14827.588377 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14827.588377 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16761.942072 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16761.942072 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 29407.773027 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 29407.773027 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15334.795472 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15334.795472 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21079.777029 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21079.777029 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed +system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4754677 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits +system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses +system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41378134500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 143188790 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707385 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15620.734183 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15620.734183 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13970.550598 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13970.550598 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1658,161 +1659,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3232302 # number of writebacks -system.cpu1.dcache.writebacks::total 3232302 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357442 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 357442 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 916671 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 916671 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 62 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 62 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39535 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39535 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 40 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1274113 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1274113 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1274113 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1274113 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2812150 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2812150 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1286213 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1286213 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634154 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 634154 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446212 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 446212 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115945 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115945 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4098363 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4098363 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4732517 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4732517 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5214 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10217 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37676406000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37676406000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20748839500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20748839500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13118141500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13118141500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12673625000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 12673625000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1579299000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1579299000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3766730000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3766730000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3027000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3027000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58425245500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 58425245500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71543387000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 71543387000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 574067000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 574067000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 612660500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 612660500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1186727500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1186727500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036614 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036614 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018705 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018705 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.744532 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.744532 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.795071 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.795071 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063648 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063648 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028155 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028155 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032322 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032322 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13397.722739 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13397.722739 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16131.728959 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16131.728959 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20686.050234 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20686.050234 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 28402.698717 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 28402.698717 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13621.104834 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13621.104834 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20077.661933 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20077.661933 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks +system.cpu1.dcache.writebacks::total 3093987 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1182784 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3889795 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4459525 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4459525 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38219808000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24026284000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24026284000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13466616000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13466616000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1560972500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174804000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62246092000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75712708000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 75712708000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4058237000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3938068000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3938068000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7996305000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14255.751748 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14255.751748 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15117.407291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15117.407291 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110101.074031 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110101.074031 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 122458.624825 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 122458.624825 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116152.246256 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116152.246256 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16002.409381 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16002.409381 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16977.751666 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16977.751666 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172617.481923 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172617.481923 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174466.950204 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174466.950204 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173523.393082 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173523.393082 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8492244 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.981743 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 217573051 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8492756 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.618663 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8375822912000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.981743 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8864427 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.853262 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 210585390 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8864939 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 23.754861 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.853262 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989948 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989948 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 460624372 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 460624372 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 217573051 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 217573051 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 217573051 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 217573051 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 217573051 # number of overall hits -system.cpu1.icache.overall_hits::total 217573051 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8492757 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8492757 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8492757 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8492757 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8492757 # number of overall misses -system.cpu1.icache.overall_misses::total 8492757 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 83328642500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 83328642500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 83328642500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 83328642500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 83328642500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 83328642500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 226065808 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 226065808 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 226065808 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 226065808 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 226065808 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 226065808 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037568 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037568 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037568 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037568 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037568 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037568 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9811.730455 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9811.730455 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9811.730455 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9811.730455 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 447765626 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 447765626 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 210585390 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 210585390 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 210585390 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 210585390 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 210585390 # number of overall hits +system.cpu1.icache.overall_hits::total 210585390 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8864949 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8864949 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8864949 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8864949 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8864949 # number of overall misses +system.cpu1.icache.overall_misses::total 8864949 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93186086500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 93186086500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 93186086500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 93186086500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 93186086500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 93186086500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 219450339 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 219450339 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 219450339 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 219450339 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 219450339 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 219450339 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.040396 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.040396 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.040396 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.040396 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.040396 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.040396 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10511.745358 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10511.745358 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10511.745358 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10511.745358 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1821,257 +1822,255 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8492757 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8492757 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8492757 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8492757 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8492757 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8492757 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 79082264500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 79082264500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 79082264500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 79082264500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 79082264500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 79082264500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8371000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8371000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8371000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8371000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037568 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037568 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037568 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9311.730513 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90010.752688 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90010.752688 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8864949 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8864949 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8864949 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8864949 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8864949 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8864949 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88753612500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 88753612500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88753612500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 88753612500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88753612500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 88753612500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.040396 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.040396 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.040396 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10011.745414 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6929819 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6929951 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 118 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6449392 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6450426 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 905 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 828225 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2217454 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13495.655652 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 24120573 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2233034 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.801704 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10014360255000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5089.747096 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.528183 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 67.846494 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3761.982865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3615.755476 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 887.795537 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.310654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004427 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004141 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.229613 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.220688 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054187 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823709 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 323 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5272 # 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mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136378 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.187211 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33705.774715 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41619.107045 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20070.782644 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20070.782644 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15177.422589 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.422589 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 421916.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 421916.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31663.900997 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31663.900997 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22230.931390 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25745.144886 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25745.144886 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39124.087029 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39124.087029 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25242.843263 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29622.038954 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102090.621404 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101738.741285 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114956.825904 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 114956.825904 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 108390.868161 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108152.909796 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181559 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33051.111476 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43272.670972 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33917.573139 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33917.573139 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18746.017615 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18746.017615 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 709285.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 709285.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 42515.089416 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 42515.089416 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30006.524096 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29665.921682 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 900589 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12966269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 6817398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 13255066 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 909243 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 440871 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344666 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 456246 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1853750 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1095537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8492756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6090536 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 551879 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 445151 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25476691 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16156139 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 386266 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1103974 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43123070 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 543542336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511133259 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4021304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1060115923 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 11712363 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 39696559 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.307834 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.461597 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 27476611 69.22% 69.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12219948 30.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 39696559 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 17378215985 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 190636988 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12741161217 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7401084853 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 208902970 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 601334453 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40366 # Transaction distribution -system.iobus.trans_dist::ReadResp 40366 # Transaction distribution -system.iobus.trans_dist::WriteReq 136635 # Transaction distribution -system.iobus.trans_dist::WriteResp 136635 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47764 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40378 # Transaction distribution +system.iobus.trans_dist::ReadResp 40378 # Transaction distribution +system.iobus.trans_dist::WriteReq 136939 # Transaction distribution +system.iobus.trans_dist::WriteResp 136939 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2320,18 +2321,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2341,18 +2342,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36259000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36227000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2372,7 +2373,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2380,71 +2381,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569722386 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 567439447 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147920000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115594 # number of replacements -system.iocache.tags.tagsinuse 11.293777 # Cycle average of tags in use +system.iocache.tags.replacements 115886 # number of replacements +system.iocache.tags.tagsinuse 11.252205 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115610 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115902 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9174240356000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.830924 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.462853 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466428 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705861 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9146784544000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.402122 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.850083 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462633 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240630 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.703263 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040865 # Number of tag accesses -system.iocache.tags.data_accesses 1040865 # Number of data accesses +system.iocache.tags.tag_accesses 1043376 # Number of tag accesses +system.iocache.tags.data_accesses 1043376 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses -system.iocache.demand_misses::total 8924 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses +system.iocache.demand_misses::total 8947 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8884 # number of overall misses -system.iocache.overall_misses::total 8924 # number of overall misses +system.iocache.overall_misses::realview.ide 8907 # number of overall misses +system.iocache.overall_misses::total 8947 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1643383037 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1648578037 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1688317981 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1693512981 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12626572349 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12626572349 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13959998466 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13959998466 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1643383037 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1648947037 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1688317981 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1693881981 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1643383037 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1648947037 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1688317981 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1693881981 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2459,54 +2460,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184982.331945 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184797.448380 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189549.565623 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189346.263529 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118306.089770 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118306.089770 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130486.787426 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130486.787426 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184776.673801 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189324.017101 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184776.673801 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32047 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189324.017101 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34260 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3474 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3572 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.224813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.591265 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106949 # number of writebacks +system.iocache.writebacks::total 106949 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199183037 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1202528037 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242967981 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1246312981 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7290172349 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7290172349 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8610798466 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8610798466 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1199183037 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1202747037 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1242967981 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1246531981 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1199183037 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1202747037 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1242967981 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1246531981 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2521,613 +2522,619 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134982.331945 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134797.448380 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139549.565623 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139346.263529 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68306.089770 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68306.089770 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80486.787426 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80486.787426 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1417273 # number of replacements -system.l2c.tags.tagsinuse 63778.929439 # Cycle average of tags in use -system.l2c.tags.total_refs 6059487 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1477461 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.101284 # Average number of references to valid blocks. +system.l2c.tags.replacements 1172651 # number of replacements +system.l2c.tags.tagsinuse 63896.612844 # Cycle average of tags in use +system.l2c.tags.total_refs 5899189 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1234288 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.779427 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17721.105226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.826880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 142.018903 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5534.663770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7879.546362 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8528.634482 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 234.293349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 288.797420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3403.637563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8415.757562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11494.647922 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.270403 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084452 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.120232 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.130137 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003575 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.051935 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.128414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.175394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.973189 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9520 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 195 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50473 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 311 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1751 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5310 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.145264 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002975 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.770157 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 72899096 # Number of tag accesses -system.l2c.tags.data_accesses 72899096 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2396145 # number of Writeback hits -system.l2c.Writeback_hits::total 2396145 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 29304 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31986 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 61290 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6099 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5707 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11806 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 163881 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 167785 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 331666 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5962 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3875 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 733621 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 590091 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 312280 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6619 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4964 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 660183 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 546610 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 303770 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3167975 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3875 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 733621 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 753972 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 312280 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6619 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4964 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 660183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 714395 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 303770 # number of demand (read+write) hits -system.l2c.demand_hits::total 3499641 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5962 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3875 # number of overall hits -system.l2c.overall_hits::cpu0.inst 733621 # number of overall hits -system.l2c.overall_hits::cpu0.data 753972 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 312280 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6619 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4964 # number of overall hits -system.l2c.overall_hits::cpu1.inst 660183 # number of overall hits -system.l2c.overall_hits::cpu1.data 714395 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 303770 # number of overall hits -system.l2c.overall_hits::total 3499641 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 45221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 40936 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86157 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9627 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8295 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17922 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 527041 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 116613 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 643654 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1386 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1120 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 75246 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 138345 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 230447 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2412 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2147 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 45440 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 109170 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 198349 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 804062 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1386 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1120 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 75246 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 665386 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 230447 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 45440 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 225783 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 198349 # number of demand (read+write) misses -system.l2c.demand_misses::total 1447716 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1386 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1120 # number of overall misses -system.l2c.overall_misses::cpu0.inst 75246 # number of overall misses -system.l2c.overall_misses::cpu0.data 665386 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 230447 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2412 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2147 # number of overall misses -system.l2c.overall_misses::cpu1.inst 45440 # number of overall misses -system.l2c.overall_misses::cpu1.data 225783 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 198349 # number of overall misses -system.l2c.overall_misses::total 1447716 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 294012000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 222456500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 516468500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 58985000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48576500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 107561500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 49590710499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 9911915500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 59502625999 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 125671500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 101124000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6225311500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 12482167500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215227500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192832000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3809523500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 9886876499 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 85291823548 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 125671500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 101124000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6225311500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 62072877999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 215227500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 192832000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3809523500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 19798791999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 144794449547 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 125671500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 101124000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6225311500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 62072877999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 215227500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 192832000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3809523500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 19798791999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of overall miss cycles -system.l2c.overall_miss_latency::total 144794449547 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2396145 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2396145 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 74525 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 72922 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 147447 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15726 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14002 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29728 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 690922 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 284398 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 975320 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7348 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4995 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 808867 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 728436 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 542727 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9031 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7111 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 705623 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 655780 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 502119 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3972037 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7348 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 808867 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1419358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 542727 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9031 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7111 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 705623 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 940178 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 502119 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4947357 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.606790 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.561367 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.584325 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.612171 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592415 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.602866 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3627.315534 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.299474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003200 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003822 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.093813 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.190523 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.197490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.074680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.054121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055348 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974985 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12177 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 211 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49249 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 56 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1468 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 3502 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 7139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1696 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 11834 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 35465 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.185806 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003220 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.751480 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 69068672 # Number of tag accesses +system.l2c.tags.data_accesses 69068672 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2213157 # number of Writeback hits +system.l2c.Writeback_hits::total 2213157 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 26227 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189908 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166445 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202368 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.292574 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.292574 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20763.848676 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20748.656488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20756.630372 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20820.245144 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.859554 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20804.792992 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84092.699617 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74998.374967 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 82445.049668 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80225.346258 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80567.388288 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96087.167208 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154689.304992 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84123.177283 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97112.990662 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149431.465360 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 97955.526684 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142628.292167 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152057.942203 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90897.846304 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 110548.279438 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.637353 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.577245 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.607109 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.617680 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590164 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604156 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733738 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.429780 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.635958 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174987 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.138705 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.164773 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.259003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.259003 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73490.367618 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73686.823052 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73584.353755 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76477.928602 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76548.726968 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76511.919371 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134605.409508 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126936.197568 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 132938.149578 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128290.295779 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128534.399803 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 139782.944355 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90388 # Transaction distribution -system.membus.trans_dist::ReadResp 903121 # Transaction distribution -system.membus.trans_dist::WriteReq 37855 # Transaction distribution -system.membus.trans_dist::WriteResp 37855 # Transaction distribution -system.membus.trans_dist::Writeback 1188917 # Transaction distribution -system.membus.trans_dist::CleanEvict 251117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 423385 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 299485 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111205 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 657294 # Transaction distribution -system.membus.trans_dist::ReadExResp 636531 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 812733 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122698 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90534 # Transaction distribution +system.membus.trans_dist::ReadResp 722459 # Transaction distribution +system.membus.trans_dist::WriteReq 38054 # Transaction distribution +system.membus.trans_dist::WriteResp 38054 # Transaction distribution +system.membus.trans_dist::Writeback 1001017 # Transaction distribution +system.membus.trans_dist::CleanEvict 217536 # Transaction distribution +system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 614073 # Transaction distribution +system.membus.trans_dist::ReadExResp 593351 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5171308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5317856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5660582 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 164770304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 164975029 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7270144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 172245173 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 635192 # Total snoops (count) -system.membus.snoop_fanout::samples 3870084 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 620798 # Total snoops (count) +system.membus.snoop_fanout::samples 3413791 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3870084 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3870084 # Request fanout histogram -system.membus.reqLayer0.occupancy 109645497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3413791 # Request fanout histogram +system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19606499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8359681063 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8175730132 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229316266 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3181,46 +3188,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 90390 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4911274 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37855 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3585089 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1614217 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 477552 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 311291 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 788843 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 110 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1123188 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1123188 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4828127 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8913245 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6867211 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15780456 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 273644474 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200023995 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 473668469 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3257042 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13541412 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.121741 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.326987 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2987756 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11892865 87.83% 87.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1648547 12.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13541412 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8755054077 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5258284103 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4190040133 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index f3053af8f..767e8859f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.694125 # Number of seconds simulated -sim_ticks 51694125219000 # Number of ticks simulated -final_tick 51694125219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.667585 # Number of seconds simulated +sim_ticks 51667585479000 # Number of ticks simulated +final_tick 51667585479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131034 # Simulator instruction rate (inst/s) -host_op_rate 153967 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7136466436 # Simulator tick rate (ticks/s) -host_mem_usage 718208 # Number of bytes of host memory used -host_seconds 7243.66 # Real time elapsed on the host -sim_insts 949163000 # Number of instructions simulated -sim_ops 1115282140 # Number of ops (including micro ops) simulated +host_inst_rate 173260 # Simulator instruction rate (inst/s) +host_op_rate 203581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9711995066 # Simulator tick rate (ticks/s) +host_mem_usage 728604 # Number of bytes of host memory used +host_seconds 5319.98 # Real time elapsed on the host +sim_insts 921741550 # Number of instructions simulated +sim_ops 1083047600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 407680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 346624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10124864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 101217736 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 409088 # Number of bytes read from this memory -system.physmem.bytes_read::total 112505992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10124864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10124864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 94737216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 358592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 308608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10084224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94130760 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 400576 # Number of bytes read from this memory +system.physmem.bytes_read::total 105282760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10084224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10084224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87776448 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94757796 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6370 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 158201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1581540 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6392 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1757919 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1480269 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87797028 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 157566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1470806 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1645056 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1371507 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1482842 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 195861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1958012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2176379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 195861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 195861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1832650 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1374080 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 6940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 195175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1821853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2037695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 195175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 195175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1698869 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1833048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1832650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 195861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1958410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7914 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4009426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1757919 # Number of read requests accepted -system.physmem.writeReqs 1482842 # Number of write requests accepted -system.physmem.readBursts 1757919 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1482842 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 112457536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49280 # Total number of bytes read from write queue -system.physmem.bytesWritten 94756288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 112505992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 94757796 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 770 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 146200 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 105973 # Per bank write bursts -system.physmem.perBankRdBursts::1 111407 # Per bank write bursts -system.physmem.perBankRdBursts::2 105002 # Per bank write bursts -system.physmem.perBankRdBursts::3 101812 # Per bank write bursts -system.physmem.perBankRdBursts::4 108332 # Per bank write bursts -system.physmem.perBankRdBursts::5 117578 # Per bank write bursts -system.physmem.perBankRdBursts::6 104534 # Per bank write bursts -system.physmem.perBankRdBursts::7 108687 # Per bank write bursts -system.physmem.perBankRdBursts::8 103848 # Per bank write bursts -system.physmem.perBankRdBursts::9 161007 # Per bank write bursts -system.physmem.perBankRdBursts::10 107405 # Per bank write bursts -system.physmem.perBankRdBursts::11 110838 # Per bank write bursts -system.physmem.perBankRdBursts::12 104563 # Per bank write bursts -system.physmem.perBankRdBursts::13 103815 # Per bank write bursts -system.physmem.perBankRdBursts::14 100822 # Per bank write bursts -system.physmem.perBankRdBursts::15 101526 # Per bank write bursts -system.physmem.perBankWrBursts::0 90430 # Per bank write bursts -system.physmem.perBankWrBursts::1 94995 # Per bank write bursts -system.physmem.perBankWrBursts::2 91678 # Per bank write bursts -system.physmem.perBankWrBursts::3 90022 # Per bank write bursts -system.physmem.perBankWrBursts::4 94229 # Per bank write bursts -system.physmem.perBankWrBursts::5 99888 # Per bank write bursts -system.physmem.perBankWrBursts::6 89385 # Per bank write bursts -system.physmem.perBankWrBursts::7 93994 # Per bank write bursts -system.physmem.perBankWrBursts::8 90076 # Per bank write bursts -system.physmem.perBankWrBursts::9 95745 # Per bank write bursts -system.physmem.perBankWrBursts::10 91874 # Per bank write bursts -system.physmem.perBankWrBursts::11 95898 # Per bank write bursts -system.physmem.perBankWrBursts::12 91438 # Per bank write bursts -system.physmem.perBankWrBursts::13 92023 # Per bank write bursts -system.physmem.perBankWrBursts::14 89075 # Per bank write bursts -system.physmem.perBankWrBursts::15 89817 # Per bank write bursts +system.physmem.bw_write::total 1699267 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1698869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 6940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 195175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1822252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3736962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1645056 # Number of read requests accepted +system.physmem.writeReqs 1374080 # Number of write requests accepted +system.physmem.readBursts 1645056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1374080 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 105226304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 57280 # Total number of bytes read from write queue +system.physmem.bytesWritten 87795840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 105282760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87797028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 895 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 144878 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 98762 # Per bank write bursts +system.physmem.perBankRdBursts::1 104908 # Per bank write bursts +system.physmem.perBankRdBursts::2 100268 # Per bank write bursts +system.physmem.perBankRdBursts::3 95741 # Per bank write bursts +system.physmem.perBankRdBursts::4 100817 # Per bank write bursts +system.physmem.perBankRdBursts::5 109226 # Per bank write bursts +system.physmem.perBankRdBursts::6 96584 # Per bank write bursts +system.physmem.perBankRdBursts::7 96517 # Per bank write bursts +system.physmem.perBankRdBursts::8 93312 # Per bank write bursts +system.physmem.perBankRdBursts::9 154793 # Per bank write bursts +system.physmem.perBankRdBursts::10 99831 # Per bank write bursts +system.physmem.perBankRdBursts::11 102735 # Per bank write bursts +system.physmem.perBankRdBursts::12 98206 # Per bank write bursts +system.physmem.perBankRdBursts::13 101977 # Per bank write bursts +system.physmem.perBankRdBursts::14 93251 # Per bank write bursts +system.physmem.perBankRdBursts::15 97233 # Per bank write bursts +system.physmem.perBankWrBursts::0 83938 # Per bank write bursts +system.physmem.perBankWrBursts::1 86643 # Per bank write bursts +system.physmem.perBankWrBursts::2 85449 # Per bank write bursts +system.physmem.perBankWrBursts::3 83391 # Per bank write bursts +system.physmem.perBankWrBursts::4 87884 # Per bank write bursts +system.physmem.perBankWrBursts::5 92979 # Per bank write bursts +system.physmem.perBankWrBursts::6 83797 # Per bank write bursts +system.physmem.perBankWrBursts::7 84591 # Per bank write bursts +system.physmem.perBankWrBursts::8 82134 # Per bank write bursts +system.physmem.perBankWrBursts::9 88444 # Per bank write bursts +system.physmem.perBankWrBursts::10 84764 # Per bank write bursts +system.physmem.perBankWrBursts::11 87315 # Per bank write bursts +system.physmem.perBankWrBursts::12 85408 # Per bank write bursts +system.physmem.perBankWrBursts::13 87944 # Per bank write bursts +system.physmem.perBankWrBursts::14 81647 # Per bank write bursts +system.physmem.perBankWrBursts::15 85482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 51694123514000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51667583532000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1757904 # Read request sizes (log2) +system.physmem.readPktSize::6 1645041 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1480269 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1422025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 328688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1371507 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1321455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 316451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,165 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 71947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 88213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 88480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 88386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 88377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 91264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 92065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 94405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 93246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 93724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 90170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 90391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 88772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 87233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 690739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 299.988042 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.369601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.443819 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 271817 39.35% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 165800 24.00% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63380 9.18% 72.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36796 5.33% 77.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 26984 3.91% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18833 2.73% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14857 2.15% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13605 1.97% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 78667 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 690739 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 86593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.291686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 270.345126 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 86590 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 15056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 66293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 82840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 82796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 83570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 85247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 84372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 92227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 82440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 83507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 80252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 646368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.625675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.464471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.594716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 252807 39.11% 39.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 155954 24.13% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60049 9.29% 72.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34895 5.40% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25863 4.00% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18951 2.93% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14056 2.17% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13035 2.02% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70758 10.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 646368 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.651179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 282.749901 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 79611 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 86593 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 86593 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.097999 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.728630 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.809360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 84121 97.15% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.17% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 413 0.48% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 198 0.23% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 310 0.36% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 507 0.59% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 123 0.14% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 41 0.05% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 24 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 40 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 29 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 413 0.48% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 31 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 79614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.230763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.794029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.276538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 77327 97.13% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 304 0.38% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 0.07% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 307 0.39% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 57 0.07% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 338 0.42% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 219 0.28% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.08% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 131 0.16% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 34 0.04% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 35 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 493 0.62% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 27 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 21 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 122 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 86593 # Writes before turning the bus around for reads -system.physmem.totQLat 26847024830 # Total ticks spent queuing -system.physmem.totMemAccLat 59793568580 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8785745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15278.74 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79614 # Writes before turning the bus around for reads +system.physmem.totQLat 26413369588 # Total ticks spent queuing +system.physmem.totMemAccLat 57241388338 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8220805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16064.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34028.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34814.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing -system.physmem.readRowHits 1436721 # Number of row buffer hits during reads -system.physmem.writeRowHits 1110255 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes -system.physmem.avgGap 15951229.82 # Average gap between requests -system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2651919480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1446979875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6733888200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4825144080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308234674070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29868898243500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34569199516005 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.725939 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49688706621634 # Time in different power states -system.physmem_0.memoryStateTime::REF 1726180300000 # Time in different power states +system.physmem.avgWrQLen 21.46 # Average write queue length when enqueuing +system.physmem.readRowHits 1338705 # Number of row buffer hits during reads +system.physmem.writeRowHits 1030897 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.15 # Row buffer hit rate for writes +system.physmem.avgGap 17113367.38 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2462533920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1343644500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6262011600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4462594560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1320469447905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29842244670000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34551920396805 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.734956 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49644314314893 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725294220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 279237825366 # Time in different power states +system.physmem_0.memoryStateTime::ACT 297976817607 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2570067360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1402318500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6971827200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4768930080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1306063695690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29870802610500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34568988116130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.721850 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49691848230640 # Time in different power states -system.physmem_1.memoryStateTime::REF 1726180300000 # Time in different power states +system.physmem_1.actEnergy 2424008160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1322623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6562436400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4426734240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1320896835045 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29841869760750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34552177892415 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.739940 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49643648149046 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725294220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 276092348110 # Time in different power states +system.physmem_1.memoryStateTime::ACT 298642969704 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -341,15 +338,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 260286663 # Number of BP lookups -system.cpu.branchPred.condPredicted 182589592 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12077009 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 191806323 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136128585 # Number of BTB hits +system.cpu.branchPred.lookups 252423071 # Number of BP lookups +system.cpu.branchPred.condPredicted 176427079 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11938474 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 185221577 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131501265 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.971896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31602025 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2167880 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.996731 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30906734 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2133609 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -380,61 +377,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 582770 # Table walker walks requested -system.cpu.dtb.walker.walksLong 582770 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22376 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191329 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 582770 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 582770 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 582770 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213705 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 211142 98.80% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2168 1.01% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 149 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 124 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 84 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213705 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191330 89.53% 89.53% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22376 10.47% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213706 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 582770 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 560833 # Table walker walks requested +system.cpu.dtb.walker.walksLong 560833 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21083 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178899 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 560833 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 560833 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 560833 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 199982 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 27029.240132 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22851.547546 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20760.636291 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 197624 98.82% 98.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 98.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2039 1.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 79 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 199982 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 178900 89.46% 89.46% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21083 10.54% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 199983 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560833 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 582770 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213706 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560833 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199983 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213706 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 796476 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199983 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 760816 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183257458 # DTB read hits -system.cpu.dtb.read_misses 481031 # DTB read misses -system.cpu.dtb.write_hits 162586595 # DTB write hits -system.cpu.dtb.write_misses 101739 # DTB write misses +system.cpu.dtb.read_hits 178232351 # DTB read hits +system.cpu.dtb.read_misses 463077 # DTB read misses +system.cpu.dtb.write_hits 157845440 # DTB write hits +system.cpu.dtb.write_misses 97756 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80339 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1450 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15121 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 77809 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1378 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14628 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23575 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183738489 # DTB read accesses -system.cpu.dtb.write_accesses 162688334 # DTB write accesses +system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 178695428 # DTB read accesses +system.cpu.dtb.write_accesses 157943196 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 345844053 # DTB hits -system.cpu.dtb.misses 582770 # DTB misses -system.cpu.dtb.accesses 346426823 # DTB accesses +system.cpu.dtb.hits 336077791 # DTB hits +system.cpu.dtb.misses 560833 # DTB misses +system.cpu.dtb.accesses 336638624 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,183 +463,184 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136614 # Table walker walks requested -system.cpu.itb.walker.walksLong 136614 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1073 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118911 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136614 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136614 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136614 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119984 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28837.324143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116985 97.50% 97.50% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2707 2.26% 99.76% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 180 0.15% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 56 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 24 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119984 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118911 99.11% 99.11% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1073 0.89% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119984 # Table walker page sizes translated +system.cpu.itb.walker.walks 134950 # Table walker walks requested +system.cpu.itb.walker.walksLong 134950 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117621 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 134950 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 134950 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 134950 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118695 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30170.011374 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25640.228509 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23413.242871 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 115997 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2500 2.11% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 50 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 104 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118695 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117621 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118695 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136614 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136614 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134950 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 134950 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119984 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119984 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256598 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 452975639 # ITB inst hits -system.cpu.itb.inst_misses 136614 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118695 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118695 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253645 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 438786222 # ITB inst hits +system.cpu.itb.inst_misses 134950 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57698 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 55568 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 370160 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 357024 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 453112253 # ITB inst accesses -system.cpu.itb.hits 452975639 # DTB hits -system.cpu.itb.misses 136614 # DTB misses -system.cpu.itb.accesses 453112253 # DTB accesses -system.cpu.numCycles 2511767999 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 438921172 # ITB inst accesses +system.cpu.itb.hits 438786222 # DTB hits +system.cpu.itb.misses 134950 # DTB misses +system.cpu.itb.accesses 438921172 # DTB accesses +system.cpu.numCycles 2561969113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 949163000 # Number of instructions committed -system.cpu.committedOps 1115282140 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97160712 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7743 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100877722288 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.646298 # CPI: cycles per instruction -system.cpu.ipc 0.377886 # IPC: instructions per cycle +system.cpu.committedInsts 921741550 # Number of instructions committed +system.cpu.committedOps 1083047600 # Number of ops (including micro ops) committed +system.cpu.discardedOps 92851518 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100774422273 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.779487 # CPI: cycles per instruction +system.cpu.ipc 0.359779 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 19481 # number of quiesce instructions executed -system.cpu.tickCycles 1790897935 # Number of cycles that the object actually ticked -system.cpu.idleCycles 720870064 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11142195 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957822 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 329410408 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11142707 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.562871 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957822 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 19360 # number of quiesce instructions executed +system.cpu.tickCycles 1740348403 # Number of cycles that the object actually ticked +system.cpu.idleCycles 821620710 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10715341 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930095 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320246754 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10715853 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.885325 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930095 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1384553632 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1384553632 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 168394927 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168394927 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151754199 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151754199 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 523439 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 523439 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336679 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336679 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4017108 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4017108 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4334477 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4334477 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 320149126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320149126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320672565 # number of overall hits -system.cpu.dcache.overall_hits::total 320672565 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6628843 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6628843 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4317749 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4317749 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1481094 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1481094 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1245106 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1245106 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 319103 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 319103 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1345291071 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1345291071 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 163948346 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 163948346 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 147386054 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 147386054 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 512627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 512627 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336269 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336269 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854490 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3854490 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4160967 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4160967 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 311334400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 311334400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 311847027 # number of overall hits +system.cpu.dcache.overall_hits::total 311847027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6367020 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6367020 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4130399 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4130399 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1400627 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1400627 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1238807 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1238807 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 308186 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 308186 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10946592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10946592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12427686 # number of overall misses -system.cpu.dcache.overall_misses::total 12427686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107264639000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 153170066000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58641269000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 58641269000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4837420500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4837420500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 260434705000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 260434705000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 260434705000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 260434705000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 175023770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 175023770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156071948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156071948 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004533 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2004533 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1581785 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1581785 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4336211 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4336211 # 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average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024527 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024527 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028686 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028686 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17224.207129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17224.207129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46228.053595 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46228.053595 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 414273354 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24143539 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.158767 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.872432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 115 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477169361 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477169361 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 428017274 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428017274 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428017274 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428017274 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428017274 # number of overall hits -system.cpu.icache.overall_hits::total 428017274 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24576044 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24576044 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.373370 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122657.517379 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122657.517379 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122111.048317 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122111.048317 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124663.523334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124663.523334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128719.944876 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128719.944876 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126109.187059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122111.048317 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123335.131466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123243.710266 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126109.187059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122111.048317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123335.131466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123243.710266 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160539.795828 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131918.017348 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161165.296980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161165.296980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160852.588164 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140152.854350 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1789463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33899423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10034845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 27401014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49574 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 70464557 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35605124 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2275 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 1730195 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33090138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 9595897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 26867205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 47929 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2364622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2364622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24576044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7542009 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1351619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1244955 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73828388 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33661752 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 699908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2274176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 110464224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576213440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1181188062 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2333736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7831184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2767566422 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2271727 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 75147333 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.047128 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.211913 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 47931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2261624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2261624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24143549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7224490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238665 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72531044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32377896 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 689100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164239 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 107762279 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548534656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133143634 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2287216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7385984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2691351490 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160503 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 73254310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097963 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 71605763 95.29% 95.29% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3541570 4.71% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 72544433 99.03% 99.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 709877 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 75147333 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 45226020496 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 73254310 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 44006051993 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1484899 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36946016966 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36299896753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15544978992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14910158065 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408213455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403245904 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1295285984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1241004972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40306 # Transaction distribution -system.iobus.trans_dist::ReadResp 40306 # Transaction distribution +system.iobus.trans_dist::ReadReq 40332 # Transaction distribution +system.iobus.trans_dist::ReadResp 40332 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1243,11 +1249,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231022 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353806 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1264,11 +1270,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334520 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334520 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492440 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1297,71 +1303,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568890575 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565934074 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115467 # number of replacements -system.iocache.tags.tagsinuse 10.447125 # Cycle average of tags in use +system.iocache.tags.replacements 115493 # number of replacements +system.iocache.tags.tagsinuse 10.440039 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115483 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13147039080000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519011 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928115 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433007 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652945 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13160095445000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.520833 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919206 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220052 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432450 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652502 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039722 # Number of tag accesses -system.iocache.tags.data_accesses 1039722 # Number of data accesses +system.iocache.tags.tag_accesses 1039956 # Number of tag accesses +system.iocache.tags.data_accesses 1039956 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8884 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8821 # number of demand (read+write) misses -system.iocache.demand_misses::total 8861 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8847 # number of demand (read+write) misses +system.iocache.demand_misses::total 8887 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8821 # number of overall misses -system.iocache.overall_misses::total 8861 # number of overall misses +system.iocache.overall_misses::realview.ide 8847 # number of overall misses +system.iocache.overall_misses::total 8887 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1605437158 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1610506158 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1639357105 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1644426105 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610481417 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610481417 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13823164969 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13823164969 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1605437158 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1610857158 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1639357105 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1644777105 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1605437158 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1610857158 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1639357105 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1644777105 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8884 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8821 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8861 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8847 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8887 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8821 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8861 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8847 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8887 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1376,54 +1382,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181813.745541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185300.904826 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185099.741670 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129595.411470 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129595.411470 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181791.802054 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185076.753123 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181791.802054 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31114 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185076.753123 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32638 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3332 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3399 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.337935 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.602236 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8884 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8821 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8861 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8847 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8887 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8821 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8861 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8847 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8887 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164387158 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1167606158 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1197007105 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1200226105 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277281417 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7277281417 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8489964969 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8489964969 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1164387158 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1167807158 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1197007105 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1200427105 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1164387158 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1167807158 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1197007105 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1200427105 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1438,72 +1444,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135300.904826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135099.741670 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79595.411470 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79595.411470 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 85994 # Transaction distribution -system.membus.trans_dist::ReadResp 540915 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::Writeback 1480269 # Transaction distribution -system.membus.trans_dist::CleanEvict 239619 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39541 # Transaction distribution +system.membus.trans_dist::ReadReq 86006 # Transaction distribution +system.membus.trans_dist::ReadResp 529580 # Transaction distribution +system.membus.trans_dist::WriteReq 33706 # Transaction distribution +system.membus.trans_dist::WriteResp 33706 # Transaction distribution +system.membus.trans_dist::Writeback 1371507 # Transaction distribution +system.membus.trans_dist::CleanEvict 234789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38219 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39543 # Transaction distribution -system.membus.trans_dist::ReadExReq 1253823 # Transaction distribution -system.membus.trans_dist::ReadExResp 1253823 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 454921 # Transaction distribution +system.membus.trans_dist::UpgradeResp 38221 # Transaction distribution +system.membus.trans_dist::ReadExReq 1152452 # Transaction distribution +system.membus.trans_dist::ReadExResp 1152452 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 443574 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5195008 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5324666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5666061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4853436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4983088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5324252 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200030316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 200200734 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7233472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 207434206 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3131 # Total snoops (count) -system.membus.snoop_fanout::samples 3697223 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185854828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186025234 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7224960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7224960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 193250194 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3290 # Total snoops (count) +system.membus.snoop_fanout::samples 3469738 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3697223 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3469738 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3697223 # Request fanout histogram -system.membus.reqLayer0.occupancy 102366500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3469738 # Request fanout histogram +system.membus.reqLayer0.occupancy 102307500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5756000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5483000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9961724084 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9286465077 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9396279986 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8797329089 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228925719 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228468079 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1514,11 +1520,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index e2a586128..91c027805 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.562170 # Number of seconds simulated -sim_ticks 51562169701000 # Number of ticks simulated -final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.291801 # Number of seconds simulated +sim_ticks 51291801227000 # Number of ticks simulated +final_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60233 # Simulator instruction rate (inst/s) -host_op_rate 70799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2812244888 # Simulator tick rate (ticks/s) -host_mem_usage 727556 # Number of bytes of host memory used -host_seconds 18334.88 # Real time elapsed on the host -sim_insts 1104366834 # Number of instructions simulated -sim_ops 1298086167 # Number of ops (including micro ops) simulated +host_inst_rate 74063 # Simulator instruction rate (inst/s) +host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4454709483 # Simulator tick rate (ticks/s) +host_mem_usage 731804 # Number of bytes of host memory used +host_seconds 11514.06 # Real time elapsed on the host +sim_insts 852762944 # Number of instructions simulated +sim_ops 1002063356 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory -system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory +system.physmem.bytes_read::total 81891560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69986404 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2467786 # Number of read requests accepted -system.physmem.writeReqs 2184211 # Number of write requests accepted -system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue -system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 149005 # Per bank write bursts -system.physmem.perBankRdBursts::1 156339 # Per bank write bursts -system.physmem.perBankRdBursts::2 155955 # Per bank write bursts -system.physmem.perBankRdBursts::3 150628 # Per bank write bursts -system.physmem.perBankRdBursts::4 148084 # Per bank write bursts -system.physmem.perBankRdBursts::5 159303 # Per bank write bursts -system.physmem.perBankRdBursts::6 149188 # Per bank write bursts -system.physmem.perBankRdBursts::7 152515 # Per bank write bursts -system.physmem.perBankRdBursts::8 150862 # Per bank write bursts -system.physmem.perBankRdBursts::9 179370 # Per bank write bursts -system.physmem.perBankRdBursts::10 150320 # Per bank write bursts -system.physmem.perBankRdBursts::11 155893 # Per bank write bursts -system.physmem.perBankRdBursts::12 152080 # Per bank write bursts -system.physmem.perBankRdBursts::13 155961 # Per bank write bursts -system.physmem.perBankRdBursts::14 150556 # Per bank write bursts -system.physmem.perBankRdBursts::15 150970 # Per bank write bursts -system.physmem.perBankWrBursts::0 132106 # Per bank write bursts -system.physmem.perBankWrBursts::1 138501 # Per bank write bursts -system.physmem.perBankWrBursts::2 137398 # Per bank write bursts -system.physmem.perBankWrBursts::3 135602 # Per bank write bursts -system.physmem.perBankWrBursts::4 133392 # Per bank write bursts -system.physmem.perBankWrBursts::5 140433 # Per bank write bursts -system.physmem.perBankWrBursts::6 132940 # Per bank write bursts -system.physmem.perBankWrBursts::7 137025 # Per bank write bursts -system.physmem.perBankWrBursts::8 135656 # Per bank write bursts -system.physmem.perBankWrBursts::9 141181 # Per bank write bursts -system.physmem.perBankWrBursts::10 134433 # Per bank write bursts -system.physmem.perBankWrBursts::11 138339 # Per bank write bursts -system.physmem.perBankWrBursts::12 136301 # Per bank write bursts -system.physmem.perBankWrBursts::13 138853 # Per bank write bursts -system.physmem.perBankWrBursts::14 135122 # Per bank write bursts -system.physmem.perBankWrBursts::15 134659 # Per bank write bursts +system.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1364074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1364475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1364074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1467351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2961057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1295521 # Number of read requests accepted +system.physmem.writeReqs 1095789 # Number of write requests accepted +system.physmem.readBursts 1295521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1095789 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 82863680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue +system.physmem.bytesWritten 69985152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81891560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69986404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 141837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 78118 # Per bank write bursts +system.physmem.perBankRdBursts::1 81473 # Per bank write bursts +system.physmem.perBankRdBursts::2 82762 # Per bank write bursts +system.physmem.perBankRdBursts::3 80112 # Per bank write bursts +system.physmem.perBankRdBursts::4 77452 # Per bank write bursts +system.physmem.perBankRdBursts::5 84131 # Per bank write bursts +system.physmem.perBankRdBursts::6 77443 # Per bank write bursts +system.physmem.perBankRdBursts::7 77113 # Per bank write bursts +system.physmem.perBankRdBursts::8 74240 # Per bank write bursts +system.physmem.perBankRdBursts::9 104872 # Per bank write bursts +system.physmem.perBankRdBursts::10 79788 # Per bank write bursts +system.physmem.perBankRdBursts::11 80502 # Per bank write bursts +system.physmem.perBankRdBursts::12 82162 # Per bank write bursts +system.physmem.perBankRdBursts::13 82091 # Per bank write bursts +system.physmem.perBankRdBursts::14 76266 # Per bank write bursts +system.physmem.perBankRdBursts::15 76220 # Per bank write bursts +system.physmem.perBankWrBursts::0 65460 # Per bank write bursts +system.physmem.perBankWrBursts::1 68510 # Per bank write bursts +system.physmem.perBankWrBursts::2 70351 # Per bank write bursts +system.physmem.perBankWrBursts::3 69772 # Per bank write bursts +system.physmem.perBankWrBursts::4 67735 # Per bank write bursts +system.physmem.perBankWrBursts::5 71090 # Per bank write bursts +system.physmem.perBankWrBursts::6 66311 # Per bank write bursts +system.physmem.perBankWrBursts::7 67773 # Per bank write bursts +system.physmem.perBankWrBursts::8 64800 # Per bank write bursts +system.physmem.perBankWrBursts::9 72411 # Per bank write bursts +system.physmem.perBankWrBursts::10 67462 # Per bank write bursts +system.physmem.perBankWrBursts::11 69064 # Per bank write bursts +system.physmem.perBankWrBursts::12 70238 # Per bank write bursts +system.physmem.perBankWrBursts::13 69848 # Per bank write bursts +system.physmem.perBankWrBursts::14 66451 # Per bank write bursts +system.physmem.perBankWrBursts::15 66242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 51562168447500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 51291799925500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2446501 # Read request sizes (log2) +system.physmem.readPktSize::6 1274236 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2181638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1093216 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 662611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 153233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 129247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,161 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 12367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 46525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 65687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 68922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 68990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 505036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.648619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.485841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.471265 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 200174 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 119366 23.64% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 47641 9.43% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24555 4.86% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19234 3.81% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12076 2.39% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11328 2.24% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8283 1.64% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62379 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 505036 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.744284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 264.086390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 62410 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads -system.physmem.totQLat 61876185756 # Total ticks spent queuing -system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.520677 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.965036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.067360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 59523 95.37% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 900 1.44% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 0.09% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 320 0.51% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 34 0.05% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 343 0.55% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 222 0.36% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.03% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 51 0.08% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 131 0.21% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 40 0.06% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 504 0.81% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.06% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 123 0.20% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62413 # Writes before turning the bus around for reads +system.physmem.totQLat 33295532684 # Total ticks spent queuing +system.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6473725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 2056722 # Number of row buffer hits during reads -system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes -system.physmem.avgGap 11083878.27 # Average gap between requests -system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.871313 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing +system.physmem.readRowHits 1061078 # Number of row buffer hits during reads +system.physmem.writeRowHits 822147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes +system.physmem.avgGap 21449247.45 # Average gap between requests +system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.513169 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states +system.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states +system.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.883816 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.516119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states +system.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states +system.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -325,27 +327,27 @@ system.realview.nvmem.num_reads::cpu.data 5 # N system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 288825634 # Number of BP lookups -system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits +system.cpu.branchPred.lookups 225483777 # Number of BP lookups +system.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104065621 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,45 +378,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 346524 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 346524 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 346524 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 346524 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 346524 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 1622408500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 1622408500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 1622408500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 271954 90.33% 90.33% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 29125 9.67% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 301079 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 346524 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 198855 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 198855 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 198855 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 198855 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 198855 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples -1585443796 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 -1585443796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total -1585443796 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 154365 91.27% 91.27% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 14759 8.73% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 169124 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 198855 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 346524 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 301079 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 198855 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169124 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 301079 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 647603 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169124 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 367979 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 204557812 # DTB read hits -system.cpu.checker.dtb.read_misses 253438 # DTB read misses -system.cpu.checker.dtb.write_hits 188384851 # DTB write hits -system.cpu.checker.dtb.write_misses 93086 # DTB write misses -system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.dtb.read_hits 160299016 # DTB read hits +system.cpu.checker.dtb.read_misses 147713 # DTB read misses +system.cpu.checker.dtb.write_hits 145602296 # DTB write hits +system.cpu.checker.dtb.write_misses 51142 # DTB write misses +system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 87812 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 72297 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 10297 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7392 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 24573 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 204811250 # DTB read accesses -system.cpu.checker.dtb.write_accesses 188477937 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19169 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 160446729 # DTB read accesses +system.cpu.checker.dtb.write_accesses 145653438 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 392942663 # DTB hits -system.cpu.checker.dtb.misses 346524 # DTB misses -system.cpu.checker.dtb.accesses 393289187 # DTB accesses +system.cpu.checker.dtb.hits 305901312 # DTB hits +system.cpu.checker.dtb.misses 198855 # DTB misses +system.cpu.checker.dtb.accesses 306100167 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -444,46 +446,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 130770 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 130770 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 130770 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 130770 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 130770 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 1621807000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 1621807000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 1621807000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 116506 98.90% 98.90% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1293 1.10% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 117799 # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 120055 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 120055 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 120055 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 120055 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 120055 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples -1586395296 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 -1586395296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total -1586395296 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108145 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109425 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 130770 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 130770 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120055 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120055 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 117799 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 117799 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 248569 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 1104906556 # ITB inst hits -system.cpu.checker.itb.inst_misses 130770 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109425 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109425 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 229480 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 853171657 # ITB inst hits +system.cpu.checker.itb.inst_misses 120055 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 60682 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 51971 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 1105037326 # ITB inst accesses -system.cpu.checker.itb.hits 1104906556 # DTB hits -system.cpu.checker.itb.misses 130770 # DTB misses -system.cpu.checker.itb.accesses 1105037326 # DTB accesses -system.cpu.checker.numCycles 1298799784 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 853291712 # ITB inst accesses +system.cpu.checker.itb.hits 853171657 # DTB hits +system.cpu.checker.itb.misses 120055 # DTB misses +system.cpu.checker.itb.accesses 853291712 # DTB accesses +system.cpu.checker.numCycles 1002635249 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -515,84 +517,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 1430156 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 951545 # Table walker walks requested +system.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217117628 # DTB read hits -system.cpu.dtb.read_misses 1002788 # DTB read misses -system.cpu.dtb.write_hits 192115888 # DTB write hits -system.cpu.dtb.write_misses 427368 # DTB write misses -system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 170217039 # DTB read hits +system.cpu.dtb.read_misses 674912 # DTB read misses +system.cpu.dtb.write_hits 148367148 # DTB write hits +system.cpu.dtb.write_misses 276633 # DTB write misses +system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218120416 # DTB read accesses -system.cpu.dtb.write_accesses 192543256 # DTB write accesses +system.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170891951 # DTB read accesses +system.cpu.dtb.write_accesses 148643781 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409233516 # DTB hits -system.cpu.dtb.misses 1430156 # DTB misses -system.cpu.dtb.accesses 410663672 # DTB accesses +system.cpu.dtb.hits 318584187 # DTB hits +system.cpu.dtb.misses 951545 # DTB misses +system.cpu.dtb.accesses 319535732 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -622,877 +627,881 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 177415 # Table walker walks requested -system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walks 161585 # Table walker walks requested +system.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 461294711 # ITB inst hits -system.cpu.itb.inst_misses 177415 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 358536824 # ITB inst hits +system.cpu.itb.inst_misses 161585 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 461472126 # ITB inst accesses -system.cpu.itb.hits 461294711 # DTB hits -system.cpu.itb.misses 177415 # DTB misses -system.cpu.itb.accesses 461472126 # DTB accesses -system.cpu.numCycles 2141240199 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 358698409 # ITB inst accesses +system.cpu.itb.hits 358536824 # DTB hits +system.cpu.itb.misses 161585 # DTB misses +system.cpu.itb.accesses 358698409 # DTB accesses +system.cpu.numCycles 1657263364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434692108 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 440187114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued -system.cpu.iq.rate 0.633727 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued +system.cpu.iq.rate 0.634165 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 272684 # number of nop insts executed -system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed -system.cpu.iew.exec_branches 255119365 # Number of branches executed -system.cpu.iew.exec_stores 192124980 # Number of stores executed -system.cpu.iew.exec_rate 0.627523 # Inst execution rate -system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back -system.cpu.iew.wb_producers 573421420 # num instructions producing a value -system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value +system.cpu.iew.exec_nop 222579 # number of nop insts executed +system.cpu.iew.exec_refs 318568485 # number of memory reference insts executed +system.cpu.iew.exec_branches 197267293 # Number of branches executed +system.cpu.iew.exec_stores 148362844 # Number of stores executed +system.cpu.iew.exec_rate 0.627402 # Inst execution rate +system.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back +system.cpu.iew.wb_producers 440084197 # num instructions producing a value +system.cpu.iew.wb_consumers 711913770 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623840 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1104366834 # Number of instructions committed -system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle +system.cpu.commit.committedInsts 852762944 # Number of instructions committed +system.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 393173853 # Number of memory references committed -system.cpu.commit.loads 204756836 # Number of loads committed -system.cpu.commit.membars 9104821 # Number of memory barriers committed -system.cpu.commit.branches 246834909 # Number of branches committed -system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. -system.cpu.commit.function_calls 30876862 # Number of function calls committed. +system.cpu.commit.refs 306001487 # Number of memory references committed +system.cpu.commit.loads 160395163 # Number of loads committed +system.cpu.commit.membars 6971183 # Number of memory barriers committed +system.cpu.commit.branches 190333133 # Number of branches committed +system.cpu.commit.fp_insts 897329 # Number of committed floating point instructions. +system.cpu.commit.int_insts 920660333 # Number of committed integer instructions. +system.cpu.commit.function_calls 25420821 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 693695163 69.23% 69.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2156692 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98172 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction -system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3405665880 # The number of ROB reads -system.cpu.rob.rob_writes 2734432791 # The number of ROB writes -system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1104366834 # Number of Instructions Simulated -system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads -system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads -system.cpu.int_regfile_writes 940526506 # number of integer regfile writes -system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads -system.cpu.fp_regfile_writes 765828 # number of floating regfile writes -system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads -system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes -system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads -system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes -system.cpu.dcache.tags.replacements 13614186 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1002063356 # Class of committed instruction +system.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2620126782 # The number of ROB reads +system.cpu.rob.rob_writes 2119163855 # The number of ROB writes +system.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 852762944 # Number of Instructions Simulated +system.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.943405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.514561 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1230978083 # number of integer regfile reads +system.cpu.int_regfile_writes 734956712 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462594 # number of floating regfile reads +system.cpu.fp_regfile_writes 785720 # number of floating regfile writes +system.cpu.cc_regfile_reads 226481409 # number of cc regfile reads +system.cpu.cc_regfile_writes 227147205 # number of cc regfile writes +system.cpu.misc_regfile_reads 2590605655 # number of misc regfile reads +system.cpu.misc_regfile_writes 27218545 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9745793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972785 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 284478201 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9746305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.188313 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972785 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # 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number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses -system.cpu.dcache.overall_misses::total 33384034 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 203343916000 # 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miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1242843351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1242843351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147746281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147746281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128943597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128943597 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 378897 # 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number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11373760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11373760 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1183380 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1183380 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233189 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233189 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 450358 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 450358 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20973518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20973518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22156898 # number of overall misses +system.cpu.dcache.overall_misses::total 22156898 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 170465804000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 170465804000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 459745522921 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 459745522921 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 90424230789 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 90424230789 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6989283500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6989283500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276500 # 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number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557906 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557906 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3771413 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3771413 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3719267 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3719267 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297663396 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297663396 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299225673 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299225673 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081057 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757471 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.757471 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791568 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791568 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119414 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119414 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.070461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074047 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074047 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17757.302215 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17757.302215 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40421.595226 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40421.595226 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 73325.524951 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 73325.524951 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15519.394571 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15519.394571 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55300 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55300 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30047.955089 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30047.955089 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28443.120825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28443.120825 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 50799342 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1609216 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.567758 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks -system.cpu.dcache.writebacks::total 10299062 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7545853 # number of writebacks +system.cpu.dcache.writebacks::total 7545853 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4464090 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4464090 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9352283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9352283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6863 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6863 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220342 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 220342 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13816373 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13816373 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13816373 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13816373 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5135668 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5135668 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2021477 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2021477 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1176591 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1176591 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226326 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226326 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230016 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230016 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7157145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7157145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8333736 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8333736 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85690864500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 85690864500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79882963880 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79882963880 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24040362000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24040362000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 88797727789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 88797727789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3265448000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3265448000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060989 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060989 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23134.060911 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23134.060911 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22752.603440 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22752.603440 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173152.610310 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173152.610310 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 16756542 # number of replacements -system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15058288 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916796 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 342301291 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15058800 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.730981 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916796 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits -system.cpu.icache.overall_hits::total 443237235 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses -system.cpu.icache.overall_misses::total 17559241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 460796476 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 767143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 767143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15059021 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15059021 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15059021 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15059021 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15059021 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15059021 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191438172888 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191438172888 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191438172888 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191438172888 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191438172888 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191438172888 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684494000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 2684494000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.042049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.042049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12712.524465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12712.524465 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12712.524465 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12712.524465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12712.524465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12712.524465 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126062.174219 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126062.174219 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2345734 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65318.237935 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 55622573 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2409067 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.088844 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 265.508156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 348.644093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6890.433367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.546517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004051 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.105140 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.335649 # 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mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785587 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785587 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005633 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040343 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040343 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.409431 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.409431 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.031106 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.031106 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128612.839940 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70763.655401 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70763.655401 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129127.304187 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129127.304187 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124571.716553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124571.716553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129275.526257 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1898399 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40298 # Transaction distribution system.iobus.trans_dist::ReadResp 40298 # Transaction distribution @@ -1761,7 +1776,7 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565777121 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1772,16 +1787,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.417924 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103107119000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.546641 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.871282 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1800,19 +1815,19 @@ system.iocache.demand_misses::total 8853 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8813 # number of overall misses system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5101000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670573105 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675674105 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13828326016 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13828326016 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5452000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1670573105 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1676025105 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5452000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1670573105 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1676025105 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -1839,24 +1854,24 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137864.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189557.824237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189341.706780 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129643.797495 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129643.797495 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34546 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3397 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.169561 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1875,19 +1890,19 @@ system.iocache.demand_mshr_misses::total 8853 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3251000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229923105 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1233174105 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3452000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1229923105 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1233375105 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3452000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1229923105 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1233375105 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1901,73 +1916,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87864.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139557.824237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139341.706780 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54987 # Transaction distribution -system.membus.trans_dist::ReadResp 601962 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::Writeback 2181638 # Transaction distribution -system.membus.trans_dist::CleanEvict 277040 # Transaction distribution -system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution +system.membus.trans_dist::ReadReq 54973 # Transaction distribution +system.membus.trans_dist::ReadResp 419838 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::Writeback 1093216 # Transaction distribution +system.membus.trans_dist::CleanEvict 195829 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35178 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution -system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35181 # Transaction distribution +system.membus.trans_dist::ReadExReq 912510 # Transaction distribution +system.membus.trans_dist::ReadExResp 912510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 364865 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3830691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3960313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4301676 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2989 # Total snoops (count) -system.membus.snoop_fanout::samples 5154600 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3147 # Total snoops (count) +system.membus.snoop_fanout::samples 2799608 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5154600 # Request fanout histogram -system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2799608 # Request fanout histogram +system.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1978,11 +1993,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2022,6 +2037,6 @@ system.realview.realview_io.osc_smb.clock 20000 # C system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 9055480cb..973772ffd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.309815 # Number of seconds simulated -sim_ticks 47309815475000 # Number of ticks simulated -final_tick 47309815475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.434893 # Number of seconds simulated +sim_ticks 47434893411000 # Number of ticks simulated +final_tick 47434893411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80227 # Simulator instruction rate (inst/s) -host_op_rate 94350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4125416978 # Simulator tick rate (ticks/s) -host_mem_usage 770696 # Number of bytes of host memory used -host_seconds 11467.89 # Real time elapsed on the host -sim_insts 920033396 # Number of instructions simulated -sim_ops 1081995375 # Number of ops (including micro ops) simulated +host_inst_rate 99639 # Simulator instruction rate (inst/s) +host_op_rate 117176 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5152463712 # Simulator tick rate (ticks/s) +host_mem_usage 784704 # Number of bytes of host memory used +host_seconds 9206.25 # Real time elapsed on the host +sim_insts 917301737 # Number of instructions simulated +sim_ops 1078753903 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 174848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 152512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4545760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43325128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 19040640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 136192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 127232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2550688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17518992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15564544 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439744 # Number of bytes read from this memory -system.physmem.bytes_read::total 103576280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4545760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2550688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7096448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86607680 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 208192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 203648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4658336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 45847432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 22095168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 91328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 66368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2323808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12264528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10934912 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory +system.physmem.bytes_read::total 99115800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4658336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2323808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6982144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83002560 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86628264 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2732 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 676968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 297510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2128 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 273747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 243196 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1634401 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1353245 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83023144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3253 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 88739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 716379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 345237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1427 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1037 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 36353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 191646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 170858 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1564706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1296915 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1355819 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 96085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 915775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 402467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 370304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 328992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2189319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 96085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 149999 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1830649 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1299489 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 98205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 966534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 465800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 258555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 230525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2089512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 98205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 147194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1749821 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1831084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1830649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 96085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 916210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 402467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 370304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 328992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4020403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1634401 # Number of read requests accepted -system.physmem.writeReqs 1355819 # Number of write requests accepted -system.physmem.readBursts 1634401 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1355819 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104570688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue -system.physmem.bytesWritten 86627008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 103576280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86628264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1750255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1749821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 98205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 966968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 465800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 258555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 230525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3839767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1564706 # Number of read requests accepted +system.physmem.writeReqs 1299489 # Number of write requests accepted +system.physmem.readBursts 1564706 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1299489 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 100111296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 29888 # Total number of bytes read from write queue +system.physmem.bytesWritten 83021568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 99115800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83023144 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 467 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 224542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 101664 # Per bank write bursts -system.physmem.perBankRdBursts::1 108898 # Per bank write bursts -system.physmem.perBankRdBursts::2 93497 # Per bank write bursts -system.physmem.perBankRdBursts::3 100406 # Per bank write bursts -system.physmem.perBankRdBursts::4 99202 # Per bank write bursts -system.physmem.perBankRdBursts::5 111502 # Per bank write bursts -system.physmem.perBankRdBursts::6 102695 # Per bank write bursts -system.physmem.perBankRdBursts::7 105017 # Per bank write bursts -system.physmem.perBankRdBursts::8 95660 # Per bank write bursts -system.physmem.perBankRdBursts::9 119055 # Per bank write bursts -system.physmem.perBankRdBursts::10 95976 # Per bank write bursts -system.physmem.perBankRdBursts::11 99461 # Per bank write bursts -system.physmem.perBankRdBursts::12 97685 # Per bank write bursts -system.physmem.perBankRdBursts::13 98791 # Per bank write bursts -system.physmem.perBankRdBursts::14 102404 # Per bank write bursts -system.physmem.perBankRdBursts::15 102004 # Per bank write bursts -system.physmem.perBankWrBursts::0 83138 # Per bank write bursts -system.physmem.perBankWrBursts::1 88505 # Per bank write bursts -system.physmem.perBankWrBursts::2 79517 # Per bank write bursts -system.physmem.perBankWrBursts::3 83751 # Per bank write bursts -system.physmem.perBankWrBursts::4 82730 # Per bank write bursts -system.physmem.perBankWrBursts::5 91993 # Per bank write bursts -system.physmem.perBankWrBursts::6 85763 # Per bank write bursts -system.physmem.perBankWrBursts::7 87476 # Per bank write bursts -system.physmem.perBankWrBursts::8 80354 # Per bank write bursts -system.physmem.perBankWrBursts::9 84626 # Per bank write bursts -system.physmem.perBankWrBursts::10 82451 # Per bank write bursts -system.physmem.perBankWrBursts::11 83951 # Per bank write bursts -system.physmem.perBankWrBursts::12 82076 # Per bank write bursts -system.physmem.perBankWrBursts::13 85332 # Per bank write bursts -system.physmem.perBankWrBursts::14 85178 # Per bank write bursts -system.physmem.perBankWrBursts::15 86706 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 228681 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 96105 # Per bank write bursts +system.physmem.perBankRdBursts::1 104079 # Per bank write bursts +system.physmem.perBankRdBursts::2 99076 # Per bank write bursts +system.physmem.perBankRdBursts::3 102555 # Per bank write bursts +system.physmem.perBankRdBursts::4 95026 # Per bank write bursts +system.physmem.perBankRdBursts::5 98411 # Per bank write bursts +system.physmem.perBankRdBursts::6 98571 # Per bank write bursts +system.physmem.perBankRdBursts::7 95349 # Per bank write bursts +system.physmem.perBankRdBursts::8 90083 # Per bank write bursts +system.physmem.perBankRdBursts::9 124090 # Per bank write bursts +system.physmem.perBankRdBursts::10 93867 # Per bank write bursts +system.physmem.perBankRdBursts::11 97434 # Per bank write bursts +system.physmem.perBankRdBursts::12 91060 # Per bank write bursts +system.physmem.perBankRdBursts::13 95554 # Per bank write bursts +system.physmem.perBankRdBursts::14 90000 # Per bank write bursts +system.physmem.perBankRdBursts::15 92979 # Per bank write bursts +system.physmem.perBankWrBursts::0 80467 # Per bank write bursts +system.physmem.perBankWrBursts::1 87240 # Per bank write bursts +system.physmem.perBankWrBursts::2 82424 # Per bank write bursts +system.physmem.perBankWrBursts::3 84720 # Per bank write bursts +system.physmem.perBankWrBursts::4 78521 # Per bank write bursts +system.physmem.perBankWrBursts::5 82917 # Per bank write bursts +system.physmem.perBankWrBursts::6 81751 # Per bank write bursts +system.physmem.perBankWrBursts::7 80612 # Per bank write bursts +system.physmem.perBankWrBursts::8 77294 # Per bank write bursts +system.physmem.perBankWrBursts::9 85251 # Per bank write bursts +system.physmem.perBankWrBursts::10 78271 # Per bank write bursts +system.physmem.perBankWrBursts::11 81127 # Per bank write bursts +system.physmem.perBankWrBursts::12 78007 # Per bank write bursts +system.physmem.perBankWrBursts::13 81137 # Per bank write bursts +system.physmem.perBankWrBursts::14 77706 # Per bank write bursts +system.physmem.perBankWrBursts::15 79767 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 54 # Number of times write queue was full causing retry -system.physmem.totGap 47309813973500 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 47434891912500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1613043 # Read request sizes (log2) +system.physmem.readPktSize::6 1543348 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1353245 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 578892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 412924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 179105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 178845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 107013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 63608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2741 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1296915 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 588411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 392193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 156445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 159831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 99518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 60251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2603 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see @@ -188,163 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 19221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 41881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 50025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 77253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 82334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 88348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 89969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 94025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 94875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 112446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 104983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 99994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 89665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 146 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1028414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.914855 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.442896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.413322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 618503 60.14% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 202037 19.65% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 65034 6.32% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35244 3.43% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24806 2.41% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13355 1.30% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14362 1.40% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8867 0.86% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46206 4.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1028414 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77347 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.124284 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 260.957500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 77345 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 21518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 33036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 40734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 49908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 58222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 73957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 80711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 93166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 91933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 94699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 106371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 99156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 93223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 82575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 977888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 187.273406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 115.248079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.900483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 583799 59.70% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193375 19.77% 79.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62560 6.40% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34177 3.49% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24599 2.52% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13672 1.40% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13781 1.41% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7457 0.76% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44468 4.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 977888 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.246927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 254.221432 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 73618 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77347 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.499670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.056595 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.288618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 72278 93.45% 93.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2489 3.22% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 567 0.73% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 275 0.36% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 300 0.39% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 491 0.63% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 126 0.16% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 49 0.06% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 40 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 44 0.06% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 35 0.05% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 27 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 405 0.52% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 43 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 50 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 52 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 16 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 23 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 73621 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.620136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.126079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.628572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 68415 92.93% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2834 3.85% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 416 0.57% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 328 0.45% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 84 0.11% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 303 0.41% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 179 0.24% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 107 0.15% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 91 0.12% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 122 0.17% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 36 0.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 46 0.06% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 419 0.57% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 25 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 117 0.16% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77347 # Writes before turning the bus around for reads -system.physmem.totQLat 84737173288 # Total ticks spent queuing -system.physmem.totMemAccLat 115373117038 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8169585000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51861.37 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 73621 # Writes before turning the bus around for reads +system.physmem.totQLat 78457411069 # Total ticks spent queuing +system.physmem.totMemAccLat 107786892319 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7821195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 50156.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70611.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68906.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.70 # Average write queue length when enqueuing -system.physmem.readRowHits 1319893 # Number of row buffer hits during reads -system.physmem.writeRowHits 639153 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.22 # Row buffer hit rate for writes -system.physmem.avgGap 15821516.13 # Average gap between requests -system.physmem.pageHitRate 65.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3982161960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2172806625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6418448400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4425017040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1165891095180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27363173363250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31636109560215 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.700864 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45520771842112 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579778460000 # Time in different power states +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.14 # Average write queue length when enqueuing +system.physmem.readRowHits 1261076 # Number of row buffer hits during reads +system.physmem.writeRowHits 622485 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.99 # Row buffer hit rate for writes +system.physmem.avgGap 16561334.66 # Average gap between requests +system.physmem.pageHitRate 65.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3784611600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2065016250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6155541600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4268064960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175166619965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27430083930000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31719739959975 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.700662 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45632003284876 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583955100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 209258446888 # Time in different power states +system.physmem_0.memoryStateTime::ACT 218928032624 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3792625200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2069388750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6326026200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4345967520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1161508413915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27367017820500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31635106909845 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.679671 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45527169156111 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579778460000 # Time in different power states +system.physmem_1.actEnergy 3608221680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1968771750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6045468000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4137868800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1172302278480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27432596510250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31718875294560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.682434 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45636187348814 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583955100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 202865647889 # Time in different power states +system.physmem_1.memoryStateTime::ACT 214746668686 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,15 +378,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 147707110 # Number of BP lookups -system.cpu0.branchPred.condPredicted 98263896 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7114286 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103765470 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67713845 # Number of BTB hits +system.cpu0.branchPred.lookups 146144434 # Number of BP lookups +system.cpu0.branchPred.condPredicted 97047776 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7141884 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 102585049 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 68142392 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.256626 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20037326 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 200169 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.425266 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20061645 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208019 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,90 +417,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 575296 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 575296 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12884 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88904 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 257665 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 317631 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2022.074357 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 315561 99.35% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1443 0.45% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 466 0.15% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 74 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 64 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 317631 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 284896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 269179 94.48% 94.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 12793 4.49% 98.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1124 0.39% 99.37% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 999 0.35% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 121 0.04% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 154 0.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 275 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 60 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 49 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 59 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 25 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 18 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 284896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 550505269948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.606717 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.533946 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 549425097448 99.80% 99.80% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 576911000 0.10% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 232215500 0.04% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 109337500 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 81684000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 43624500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 15920500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 20013500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 440500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 25500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 550505269948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88905 87.34% 87.34% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12884 12.66% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101789 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 575296 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 627056 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 627056 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13350 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 99805 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 293358 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 333698 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2422.801455 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 330908 99.16% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1425 0.43% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 1094 0.33% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 333698 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 325671 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 321319 98.66% 98.66% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 949 0.29% 98.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2404 0.74% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 140 0.04% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 546 0.17% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 110 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 121 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 45 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 325671 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 568195090048 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.606171 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.541778 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 566772056048 99.75% 99.75% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 811255500 0.14% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 288193500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 133409000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 101036500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 47966000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 17568000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 22933000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 641000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 31500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 568195090048 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 99806 88.20% 88.20% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13350 11.80% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 113156 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 627056 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 575296 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101789 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 627056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113156 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101789 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 677085 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113156 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 740212 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 107498760 # DTB read hits -system.cpu0.dtb.read_misses 398450 # DTB read misses -system.cpu0.dtb.write_hits 89911233 # DTB write hits -system.cpu0.dtb.write_misses 176846 # DTB write misses +system.cpu0.dtb.read_hits 106442927 # DTB read hits +system.cpu0.dtb.read_misses 452572 # DTB read misses +system.cpu0.dtb.write_hits 87367482 # DTB write hits +system.cpu0.dtb.write_misses 174484 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36343 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6513 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 43076 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 336 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7862 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 107897210 # DTB read accesses -system.cpu0.dtb.write_accesses 90088079 # DTB write accesses +system.cpu0.dtb.perms_faults 41749 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106895499 # DTB read accesses +system.cpu0.dtb.write_accesses 87541966 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 197409993 # DTB hits -system.cpu0.dtb.misses 575296 # DTB misses -system.cpu0.dtb.accesses 197985289 # DTB accesses +system.cpu0.dtb.hits 193810409 # DTB hits +system.cpu0.dtb.misses 627056 # DTB misses +system.cpu0.dtb.accesses 194437465 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -530,1169 +525,1171 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 88373 # Table walker walks requested -system.cpu0.itb.walker.walksLong 88373 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1010 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63733 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10354 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 78019 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1154.635409 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8302.318133 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 77325 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 373 0.48% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 149 0.19% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 144 0.18% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 78019 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 75097 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 68416 91.10% 91.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 5120 6.82% 97.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 490 0.65% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 809 1.08% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 63 0.08% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 55 0.07% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 56 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 27 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 16 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 17 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 75097 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 413042823976 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.838558 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.368059 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 66699023100 16.15% 16.15% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 346328877376 83.85% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 13315500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1543000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 65000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 413042823976 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 63733 98.44% 98.44% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1010 1.56% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64743 # Table walker page sizes translated +system.cpu0.itb.walker.walks 89572 # Table walker walks requested +system.cpu0.itb.walker.walksLong 89572 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1024 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63745 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10456 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 79116 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1699.586683 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 78197 98.84% 98.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 434 0.55% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 37 0.05% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 79 0.10% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 275 0.35% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 79116 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 75225 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 72890 96.90% 96.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 127 0.17% 97.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1867 2.48% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 130 0.17% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 117 0.16% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 47 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 75225 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 417841685688 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.859653 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.347613 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 58676119976 14.04% 14.04% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 359136359212 85.95% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 25573000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 3283500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 186000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 60000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 104000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 417841685688 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 63745 98.42% 98.42% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1024 1.58% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64769 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88373 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 89572 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 89572 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64743 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64743 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 153116 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 231997623 # ITB inst hits -system.cpu0.itb.inst_misses 88373 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64769 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64769 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 154341 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 230754760 # ITB inst hits +system.cpu0.itb.inst_misses 89572 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26272 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31365 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 223051 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 227814 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 232085996 # ITB inst accesses -system.cpu0.itb.hits 231997623 # DTB hits -system.cpu0.itb.misses 88373 # DTB misses -system.cpu0.itb.accesses 232085996 # DTB accesses -system.cpu0.numCycles 807086065 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 230844332 # ITB inst accesses +system.cpu0.itb.hits 230754760 # DTB hits +system.cpu0.itb.misses 89572 # DTB misses +system.cpu0.itb.accesses 230844332 # DTB accesses +system.cpu0.numCycles 860058385 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 93861008 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 652896475 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 147707110 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87751171 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 672171434 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15342460 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1905506 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 292447 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6425780 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 696882 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 817665 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 231773404 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1782410 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 29765 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 783841952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.977378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.220143 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 93823767 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 647034006 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 146144434 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 88204037 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 713428063 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15421284 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2142608 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 370377 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6662477 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 811703 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 935488 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 230526197 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1802314 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29828 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 825885125 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.917836 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.204243 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 417241550 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 142387565 18.17% 71.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 48916006 6.24% 77.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 175296831 22.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 462725297 56.03% 56.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 141134334 17.09% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49183945 5.96% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 172841549 20.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 783841952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.183013 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.808955 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 111750908 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 381172853 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 246402586 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39053255 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5462350 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21288781 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2252861 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 678905918 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24756446 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5462350 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 148938841 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55630896 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 250198036 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 247704695 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 75907134 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 660737654 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6369939 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10029778 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 264844 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 301380 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 39545548 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 629064095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1015658028 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 780465434 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 875541 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 567964584 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61099508 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16110257 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14023115 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79266160 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 107669777 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 93504359 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9663954 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8219387 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 637670623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16186083 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 641968825 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2865871 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 57572234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37073972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 286236 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 783841952 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.819003 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071442 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 825885125 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.169924 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.752314 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 112769742 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 426082666 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 241448796 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 40086734 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5497187 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21049410 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2256773 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 670218998 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24585217 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5497187 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 150343342 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 70257974 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 265091659 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 243360217 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 91334746 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 651968055 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6322268 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11333163 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 398238 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 892987 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 53687870 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 12055 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 623161441 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1008090615 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 769730678 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 803084 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 561865875 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61295566 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16618595 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14448752 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 81009207 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 106588320 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90921259 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9791542 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8386441 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 628410475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16690332 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 633219394 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2873840 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57472988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37517559 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 288712 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 825885125 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.766716 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.051496 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 436124999 55.64% 55.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 142425457 18.17% 73.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 124936152 15.94% 89.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 71756087 9.15% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8593482 1.10% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5775 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 480372364 58.16% 58.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 144500445 17.50% 75.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 122618774 14.85% 90.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 70098834 8.49% 99.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8288641 1.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 6067 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 783841952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 825885125 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67185359 45.52% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 54880 0.04% 45.56% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 27644 0.02% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 23 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37910313 25.69% 71.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 42413379 28.74% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65372240 45.40% 45.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 70238 0.05% 45.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24747 0.02% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37918627 26.33% 71.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40615883 28.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 438393066 68.29% 68.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1458143 0.23% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 76119 0.01% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 8 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 85008 0.01% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 110671978 17.24% 85.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 91284446 14.22% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 433018605 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1583156 0.25% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 81666 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 80947 0.01% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 109728452 17.33% 85.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88726558 14.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 641968825 # Type of FU issued -system.cpu0.iq.rate 0.795416 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 147591598 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229905 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2216794106 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 710999195 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 623995458 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1442965 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 583548 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 537913 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 788669354 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 891059 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2946784 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 633219394 # Type of FU issued +system.cpu0.iq.rate 0.736252 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 144001764 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227412 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2237858803 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 702176142 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 615023589 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1340714 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 546565 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 499647 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 776393889 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 827259 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2940154 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13030035 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 154978 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6224286 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13228982 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17998 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 150420 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6097724 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2912970 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4614756 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2855732 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4944067 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5462350 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6648440 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 5673367 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 653983600 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5497187 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8555370 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7804154 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 645228891 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 107669777 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 93504359 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13738155 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 65760 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5541873 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 154978 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2183890 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3035421 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5219311 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 633716914 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 107489609 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7688831 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 106588320 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90921259 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14154267 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 60797 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7667643 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 150420 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2190803 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3056972 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5247775 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 624930976 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106438227 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7669606 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126894 # number of nop insts executed -system.cpu0.iew.exec_refs 197402015 # number of memory reference insts executed -system.cpu0.iew.exec_branches 119462239 # Number of branches executed -system.cpu0.iew.exec_stores 89912406 # Number of stores executed -system.cpu0.iew.exec_rate 0.785191 # Inst execution rate -system.cpu0.iew.wb_sent 625355277 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 624533371 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 303033924 # num instructions producing a value -system.cpu0.iew.wb_consumers 497197749 # num instructions consuming a value +system.cpu0.iew.exec_nop 128084 # number of nop insts executed +system.cpu0.iew.exec_refs 193805308 # number of memory reference insts executed +system.cpu0.iew.exec_branches 117788400 # Number of branches executed +system.cpu0.iew.exec_stores 87367081 # Number of stores executed +system.cpu0.iew.exec_rate 0.726615 # Inst execution rate +system.cpu0.iew.wb_sent 616360773 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 615523236 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 299533919 # num instructions producing a value +system.cpu0.iew.wb_consumers 491459888 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.773813 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609484 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.715676 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609478 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50242588 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15899847 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4905406 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 774311548 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.770083 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.572660 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50152735 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16401620 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4928429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 816336878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.719835 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.528210 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 515220918 66.54% 66.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 132191074 17.07% 83.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 58451829 7.55% 91.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19702970 2.54% 93.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 14118724 1.82% 95.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9514083 1.23% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6460440 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3939203 0.51% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14712307 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 559210939 68.50% 68.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 132620550 16.25% 84.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 57447612 7.04% 91.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19359516 2.37% 94.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13667086 1.67% 95.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9472900 1.16% 96.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6300261 0.77% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3865026 0.47% 98.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14392988 1.76% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 774311548 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 507069048 # Number of instructions committed -system.cpu0.commit.committedOps 596284470 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 816336878 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 500561663 # Number of instructions committed +system.cpu0.commit.committedOps 587627818 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 181919815 # Number of memory references committed -system.cpu0.commit.loads 94639742 # Number of loads committed -system.cpu0.commit.membars 4012038 # Number of memory barriers committed -system.cpu0.commit.branches 113466884 # Number of branches committed -system.cpu0.commit.fp_insts 524978 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 547272509 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14945710 # Number of function calls committed. +system.cpu0.commit.refs 178182873 # Number of memory references committed +system.cpu0.commit.loads 93359338 # Number of loads committed +system.cpu0.commit.membars 3999106 # Number of memory barriers committed +system.cpu0.commit.branches 111869987 # Number of branches committed +system.cpu0.commit.fp_insts 487433 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 538915028 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14906557 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 413008446 69.26% 69.26% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1219700 0.20% 69.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 60724 0.01% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 75743 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 94639742 15.87% 85.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 87280073 14.64% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 407981366 69.43% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1327807 0.23% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 64470 0.01% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 71302 0.01% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93359338 15.89% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84823535 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 596284470 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14712307 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1401646047 # The number of ROB reads -system.cpu0.rob.rob_writes 1302545204 # The number of ROB writes -system.cpu0.timesIdled 1046717 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23244113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93812546108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 507069048 # Number of Instructions Simulated -system.cpu0.committedOps 596284470 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.591669 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.591669 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.628271 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.628271 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 748239233 # number of integer regfile reads -system.cpu0.int_regfile_writes 444460602 # number of integer regfile writes -system.cpu0.fp_regfile_reads 860614 # number of floating regfile reads -system.cpu0.fp_regfile_writes 470540 # number of floating regfile writes -system.cpu0.cc_regfile_reads 137535879 # number of cc regfile reads -system.cpu0.cc_regfile_writes 138377705 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1393834331 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16112974 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6187008 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.050028 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169602823 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6187519 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.410473 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.050028 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986426 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986426 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 376921548 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 376921548 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87937173 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87937173 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76339825 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76339825 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228046 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 228046 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 267132 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 267132 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1986809 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1986809 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2024617 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2024617 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164276998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164276998 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164505044 # number of overall hits -system.cpu0.dcache.overall_hits::total 164505044 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6895567 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6895567 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7624089 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7624089 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 725854 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 725854 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 804065 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 804065 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 277240 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 277240 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200055 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200055 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14519656 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14519656 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15245510 # number of overall misses -system.cpu0.dcache.overall_misses::total 15245510 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102037717000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 102037717000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 136358862160 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 136358862160 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 72398693034 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 72398693034 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4092900000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4092900000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4230014500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4230014500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5283500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5283500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 238396579160 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 238396579160 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 238396579160 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 238396579160 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 94832740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 94832740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 83963914 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 83963914 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 953900 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 953900 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1071197 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1071197 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2264049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2264049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2224672 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2224672 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 178796654 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 178796654 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179750554 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179750554 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.072713 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.090802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.090802 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760933 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760933 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.750623 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.750623 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122453 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122453 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089926 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089926 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081208 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.081208 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084815 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.084815 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829 # average StoreCondReq miss latency +system.cpu0.commit.op_class_0::total 587627818 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14392988 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1435053387 # The number of ROB reads +system.cpu0.rob.rob_writes 1285071513 # The number of ROB writes +system.cpu0.timesIdled 1102508 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 34173260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94009700955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 500561663 # Number of Instructions Simulated +system.cpu0.committedOps 587627818 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.718187 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.718187 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.582009 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.582009 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 737541509 # number of integer regfile reads +system.cpu0.int_regfile_writes 438217894 # number of integer regfile writes +system.cpu0.fp_regfile_reads 788412 # number of floating regfile reads +system.cpu0.fp_regfile_writes 466436 # number of floating regfile writes +system.cpu0.cc_regfile_reads 137084844 # number of cc regfile reads +system.cpu0.cc_regfile_writes 137795028 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1439828550 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16463907 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6421526 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.135251 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165251545 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6422031 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.731976 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.135251 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 369713036 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 369713036 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86498014 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86498014 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73594824 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73594824 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223952 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 223952 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261481 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 261481 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906554 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1906554 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1959919 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1959919 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 160092838 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 160092838 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 160316790 # number of overall hits +system.cpu0.dcache.overall_hits::total 160316790 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7115044 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7115044 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7950326 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7950326 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 760555 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 760555 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 841390 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 841390 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287295 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 287295 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195310 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195310 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15065370 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15065370 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15825925 # number of overall misses +system.cpu0.dcache.overall_misses::total 15825925 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123619441500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 123619441500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 174765170319 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 174765170319 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 99329075406 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 99329075406 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4513560000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4513560000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4763112500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4763112500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4991000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4991000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 298384611819 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 298384611819 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 298384611819 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 298384611819 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93613058 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93613058 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81545150 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81545150 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 984507 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 984507 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1102871 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1102871 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193849 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2193849 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2155229 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2155229 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 175158208 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 175158208 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 176142715 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 176142715 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076005 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076005 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097496 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.097496 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772524 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772524 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.762909 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.762909 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130955 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130955 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090621 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090621 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086010 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086010 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089847 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089847 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17374.374846 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17374.374846 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21982.138886 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21982.138886 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118053.548778 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118053.548778 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15710.541430 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15710.541430 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24387.448159 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24387.448159 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 22487796 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 20190626 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 731543 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 741822 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.740224 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.217616 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19805.992937 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19805.992937 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18854.165669 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 31101776 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 27008277 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 772694 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 787427 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.251090 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 34.299404 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4210788 # number of writebacks -system.cpu0.dcache.writebacks::total 4210788 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3513002 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3513002 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6114706 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6114706 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4602 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4602 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 143782 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 143782 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9627708 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9627708 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9627708 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9627708 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3382565 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3382565 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1509383 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1509383 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 718663 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 718663 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 799463 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 799463 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 133458 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 133458 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200041 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200041 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4891948 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4891948 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5610611 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5610611 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32342 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64165 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48415097500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48415097500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29340240291 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29340240291 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16426692500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16426692500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 71393732534 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71393732534 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1844525500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1844525500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4030091500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4030091500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5165500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5165500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77755337791 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 77755337791 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94182030291 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 94182030291 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5817539000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5817539000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5518707000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5518707000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11336246000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11336246000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035669 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035669 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017977 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017977 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753394 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.753394 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746327 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746327 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058947 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058947 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089919 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089919 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027360 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027360 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031213 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031213 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4324525 # number of writebacks +system.cpu0.dcache.writebacks::total 4324525 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3632070 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3632070 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6394266 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6394266 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4384 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4384 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147311 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147311 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10026336 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10026336 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10026336 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10026336 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3482974 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3482974 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1556060 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1556060 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 753575 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 753575 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 837006 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 837006 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139984 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139984 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039034 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5039034 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5792609 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5792609 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31951 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63436 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56753773500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56753773500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38838935578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38838935578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19682576500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19682576500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 98248508406 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 98248508406 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1973900000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1973900000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4567861500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4567861500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4933000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4933000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95592709078 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 95592709078 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5771319500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5771319500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5597630000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5597630000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11368949500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368949500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037206 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019082 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019082 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765434 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765434 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758934 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758934 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063807 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063807 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090621 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090621 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028768 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028768 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032886 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032886 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6407339 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224970066 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6407851 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.108505 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6358728 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.935177 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 223756411 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6359240 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.186030 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935177 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 330 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 469899085 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 469899085 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224970066 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224970066 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224970066 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224970066 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224970066 # number of overall hits -system.cpu0.icache.overall_hits::total 224970066 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6775541 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6775541 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6775541 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6775541 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6775541 # number of overall misses -system.cpu0.icache.overall_misses::total 6775541 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71079582898 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 71079582898 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 71079582898 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 71079582898 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 71079582898 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 71079582898 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 231745607 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 231745607 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 231745607 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 231745607 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 231745607 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 231745607 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029237 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029237 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029237 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029237 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029237 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029237 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10490.613650 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10490.613650 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10215206 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 732 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 767906 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.302678 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 467353436 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 467353436 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 223756411 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 223756411 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 223756411 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 223756411 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 223756411 # number of overall hits +system.cpu0.icache.overall_hits::total 223756411 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6740667 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6740667 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6740667 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6740667 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6740667 # number of overall misses +system.cpu0.icache.overall_misses::total 6740667 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78361220616 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 78361220616 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 78361220616 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 78361220616 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 78361220616 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 78361220616 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 230497078 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 230497078 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 230497078 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 230497078 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 230497078 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 230497078 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029244 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029244 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029244 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029244 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029244 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029244 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11625.143419 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11625.143419 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11625.143419 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11625.143419 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12527067 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1547 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 814769 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.374992 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 367670 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 367670 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 367670 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 367670 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 367670 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 367670 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6407871 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6407871 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6407871 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6407871 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6407871 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6407871 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381387 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 381387 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 381387 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 381387 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 381387 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 381387 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6359280 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6359280 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6359280 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6359280 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6359280 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6359280 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64388034562 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 64388034562 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64388034562 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64388034562 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64388034562 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64388034562 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027650 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027650 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027650 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70398317173 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 70398317173 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70398317173 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 70398317173 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70398317173 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 70398317173 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027589 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027589 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027589 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11070.171021 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8228747 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8235731 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 6331 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8863203 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8872058 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7949 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1065389 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2775717 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16223.891094 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 21402394 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2791423 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.667198 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7115.603862 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.900810 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.351377 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4177.499611 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3867.898858 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.636576 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.434302 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004816 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005148 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254974 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.236078 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054909 # 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mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160015 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208689 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208689 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.107884 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249757 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249757 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747055 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747055 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161369 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222515 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227685 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51553.623009 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80780.391099 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35453.709413 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35453.709413 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19477.722669 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19477.722669 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 749666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 749666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62857.073830 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62857.073830 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33413.183246 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39373.096991 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39373.096991 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145707.870573 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145707.870573 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 972246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11719640 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31823 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 8100286 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 11177309 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1018919 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 495790 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 366670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 532232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 139 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1670081 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1283370 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6407871 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6502663 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 904766 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 798038 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19264194 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20025393 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428101 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1250579 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 40968267 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 410442912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629983858 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1576264 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4556320 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1046559354 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11261603 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 37657626 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.313855 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.464058 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 26498119 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13615382 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2337 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 550917 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 550892 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 25 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 1014324 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11851775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31486 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31485 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 5956604 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 10410037 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1088232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 474368 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351600 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 519661 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1396851 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1324661 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6359280 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5366614 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 842272 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 835494 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19118379 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20677259 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436050 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348581 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41580269 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407332384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 648350241 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1616944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4971488 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1062271057 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6461178 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 33294085 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.028312 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.165866 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 25838573 68.61% 68.61% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 11819053 31.39% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 32351497 97.17% 97.17% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 942563 2.83% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 25 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 37657626 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 17602075916 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 33294085 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 17918792438 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 231593980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208202715 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9637654372 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9565441520 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8931019988 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9227310290 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 231432265 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 234328206 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 681669728 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 727701378 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 121094303 # Number of BP lookups -system.cpu1.branchPred.condPredicted 80706133 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6142160 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 84960891 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56341743 # Number of BTB hits +system.cpu1.branchPred.lookups 122053066 # Number of BP lookups +system.cpu1.branchPred.condPredicted 81331643 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6140345 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 85523370 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 55672017 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 66.314915 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16429988 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 173246 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.095677 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16431061 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 166790 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1722,90 +1719,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 582230 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 582230 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14388 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94420 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 278308 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 303922 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1994.445943 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 299685 98.61% 98.61% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2211 0.73% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 696 0.23% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 740 0.24% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 294 0.10% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 141 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 47 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 22 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 303922 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 314895 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 312363 99.20% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1838 0.58% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 299 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 215 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 97 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 314895 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 417361955272 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.556480 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.556703 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 416192825272 99.72% 99.72% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 674141500 0.16% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 223425500 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 105228000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 86739500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 43806500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 16133000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 19234500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 421500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 417361955272 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94420 86.78% 86.78% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14388 13.22% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108808 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 582230 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 513343 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 513343 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10145 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80504 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 231589 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 281754 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2191.677847 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 279857 99.33% 99.33% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1045 0.37% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 593 0.21% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 12 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 281754 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 256242 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 254819 99.44% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 556 0.22% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 633 0.25% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 56 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 78 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 256242 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 430767474576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.581742 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.547950 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 429773436576 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 519356000 0.12% 99.89% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 211618500 0.05% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 107822000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 75775500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 45293000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 13801500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 19976000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 394000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 430767474576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 80504 88.81% 88.81% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10145 11.19% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 90649 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 513343 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 582230 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108808 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 513343 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90649 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108808 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 691038 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90649 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 603992 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 89807249 # DTB read hits -system.cpu1.dtb.read_misses 419450 # DTB read misses -system.cpu1.dtb.write_hits 72180592 # DTB write hits -system.cpu1.dtb.write_misses 162780 # DTB write misses +system.cpu1.dtb.read_hits 90392235 # DTB read hits +system.cpu1.dtb.read_misses 355030 # DTB read misses +system.cpu1.dtb.write_hits 74292452 # DTB write hits +system.cpu1.dtb.write_misses 158313 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41875 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 370 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6410 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34737 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 572 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5833 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 41502 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90226699 # DTB read accesses -system.cpu1.dtb.write_accesses 72343372 # DTB write accesses +system.cpu1.dtb.perms_faults 38175 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90747265 # DTB read accesses +system.cpu1.dtb.write_accesses 74450765 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 161987841 # DTB hits -system.cpu1.dtb.misses 582230 # DTB misses -system.cpu1.dtb.accesses 162570071 # DTB accesses +system.cpu1.dtb.hits 164684687 # DTB hits +system.cpu1.dtb.misses 513343 # DTB misses +system.cpu1.dtb.accesses 165198030 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1835,1148 +1828,1159 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 81350 # Table walker walks requested -system.cpu1.itb.walker.walksLong 81350 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 844 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59039 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9413 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 71937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1124.310160 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8422.739912 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 71675 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 232 0.32% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 79836 # Table walker walks requested +system.cpu1.itb.walker.walksLong 79836 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 812 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57876 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9466 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 70370 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1202.877647 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9654.881733 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 70178 99.73% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 41 0.06% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 131 0.19% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 71937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 69296 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 67837 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1226 1.77% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 116 0.17% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkWaitTime::total 70370 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 68154 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 67528 99.08% 99.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 75 0.11% 99.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 455 0.67% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 42 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 69296 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 391589144496 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.846934 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.360225 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 59961618480 15.31% 15.31% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 331606536516 84.68% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 19274500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1690500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 391589144496 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 59039 98.59% 98.59% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 844 1.41% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 59883 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 68154 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 396407660708 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.833666 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.372525 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 65955607768 16.64% 16.64% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 330434317940 83.36% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 16293000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1234500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 163500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 44000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 396407660708 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57876 98.62% 98.62% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 812 1.38% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58688 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81350 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81350 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79836 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79836 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59883 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59883 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 141233 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 191639831 # ITB inst hits -system.cpu1.itb.inst_misses 81350 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58688 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58688 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 138524 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 192024896 # ITB inst hits +system.cpu1.itb.inst_misses 79836 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29949 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24498 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 209776 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203556 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 191721181 # ITB inst accesses -system.cpu1.itb.hits 191639831 # DTB hits -system.cpu1.itb.misses 81350 # DTB misses -system.cpu1.itb.accesses 191721181 # DTB accesses -system.cpu1.numCycles 657106376 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 192104732 # ITB inst accesses +system.cpu1.itb.hits 192024896 # DTB hits +system.cpu1.itb.misses 79836 # DTB misses +system.cpu1.itb.accesses 192104732 # DTB accesses +system.cpu1.numCycles 663967264 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 80139865 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 537547218 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 121094303 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 72771731 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 544595085 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13230640 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1750818 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 245014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5964311 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 783127 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 735374 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 191409476 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1578665 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27162 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 640828914 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.984123 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.220773 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 80600357 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 540678400 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 122053066 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 72103078 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 547218750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13194102 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1722175 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 292741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5852987 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 747163 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 786410 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 191800841 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1580435 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27130 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643817634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.987423 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.222838 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 338710091 52.85% 52.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 117550572 18.34% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 40600676 6.34% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 143967575 22.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 339738489 52.77% 52.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 118160249 18.35% 71.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40196713 6.24% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 145722183 22.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 640828914 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.184284 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.818052 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 96524622 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 306596217 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 198367702 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34666699 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4673674 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17189225 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1979171 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 555902892 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21032284 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4673674 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 128741707 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 40944507 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 207984500 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 200380023 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 58104503 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 540647070 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5273833 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8920508 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 357666 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 869250 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 25304278 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 12220 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 515542885 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 838360476 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 639083471 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 635892 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 463444914 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52097965 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14931648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13102843 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 69578208 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 89907304 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 75221964 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8553187 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7364919 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 519731744 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15160501 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 524719232 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2440222 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 49181333 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32199370 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 264903 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 640828914 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.818813 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.060738 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643817634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.183824 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.814315 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 95925032 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 307565159 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 202328162 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33349835 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4649446 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17381659 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1984856 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 561624259 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21210320 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4649446 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 127605464 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 43917048 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 205458777 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 203595973 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58590926 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 546425758 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5335623 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9251054 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 227617 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 291872 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 27374536 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10500 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 518347442 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 840457464 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 646223551 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 691924 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 466279930 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52067506 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14268129 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12524757 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 67234415 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 90658674 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 77385188 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8528695 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7392702 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 526120257 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14498185 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 530312729 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2450487 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 49492350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31830796 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 264307 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643817634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.823700 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.068099 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 351184657 54.80% 54.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 125580577 19.60% 74.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 99945390 15.60% 89.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 57229371 8.93% 98.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6884833 1.07% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4086 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 353942401 54.98% 54.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 122398683 19.01% 73.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 101611501 15.78% 89.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 58772797 9.13% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7088607 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3645 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 640828914 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643817634 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 51884545 43.66% 43.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 60325 0.05% 43.71% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 6398 0.01% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 32949736 27.73% 71.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 33928397 28.55% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53425749 43.94% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 46790 0.04% 43.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 9685 0.01% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 19 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32795787 26.97% 70.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35319606 29.05% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 357316080 68.10% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1302107 0.25% 68.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 73183 0.01% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 41368 0.01% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 92637950 17.65% 86.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 73348522 13.98% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 360430820 67.97% 67.97% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1171247 0.22% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 68672 0.01% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 45220 0.01% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 93137728 17.56% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 75458910 14.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 524719232 # Type of FU issued -system.cpu1.iq.rate 0.798530 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 118829423 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226463 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1810487568 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 583794764 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 509259381 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1049453 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 417103 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 385439 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 642894662 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 653971 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2364683 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 530312729 # Type of FU issued +system.cpu1.iq.rate 0.798703 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 121597636 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.229294 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1827371450 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 589808611 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 515064806 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1119763 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 442884 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 412109 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 651211996 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 698285 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2417067 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11367007 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15961 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 139264 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5290675 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11379314 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14413 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 141714 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5438356 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2384785 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4103064 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2432171 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3747564 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4673674 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6987028 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1738087 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 535009487 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4649446 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5786949 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2152685 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 540731877 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 89907304 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 75221964 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12892176 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 53410 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1616074 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 139264 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1829419 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2640296 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4469715 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 517720791 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 89804186 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6423141 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 90658674 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 77385188 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12325629 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58000 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2039251 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 141714 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1867697 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2587615 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4455312 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 523333067 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 90385914 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6476972 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 117242 # number of nop insts executed -system.cpu1.iew.exec_refs 161982461 # number of memory reference insts executed -system.cpu1.iew.exec_branches 97046647 # Number of branches executed -system.cpu1.iew.exec_stores 72178275 # Number of stores executed -system.cpu1.iew.exec_rate 0.787880 # Inst execution rate -system.cpu1.iew.wb_sent 510319956 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 509644820 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 247330259 # num instructions producing a value -system.cpu1.iew.wb_consumers 405058762 # num instructions consuming a value +system.cpu1.iew.exec_nop 113435 # number of nop insts executed +system.cpu1.iew.exec_refs 164677509 # number of memory reference insts executed +system.cpu1.iew.exec_branches 98047931 # Number of branches executed +system.cpu1.iew.exec_stores 74291595 # Number of stores executed +system.cpu1.iew.exec_rate 0.788191 # Inst execution rate +system.cpu1.iew.wb_sent 516143321 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 515476915 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 249234254 # num instructions producing a value +system.cpu1.iew.wb_consumers 407965513 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.775590 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610603 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.776359 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610920 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43050408 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14895598 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4200514 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 632658676 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.767730 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.562752 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43327267 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14233878 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4192740 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 635627275 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.772664 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.570415 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 417403815 65.98% 65.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 113799591 17.99% 83.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 46934435 7.42% 91.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15547292 2.46% 93.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10981139 1.74% 95.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7643765 1.21% 96.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5190686 0.82% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3150553 0.50% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12007400 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 419865335 66.06% 66.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 112371204 17.68% 83.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 47717309 7.51% 91.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15913228 2.50% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11392527 1.79% 95.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7668933 1.21% 96.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5369975 0.84% 97.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3184156 0.50% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12144608 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 632658676 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 412964348 # Number of instructions committed -system.cpu1.commit.committedOps 485710905 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 635627275 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 416740074 # Number of instructions committed +system.cpu1.commit.committedOps 491126085 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 148471585 # Number of memory references committed -system.cpu1.commit.loads 78540296 # Number of loads committed -system.cpu1.commit.membars 3510647 # Number of memory barriers committed -system.cpu1.commit.branches 92021861 # Number of branches committed -system.cpu1.commit.fp_insts 377145 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 445805015 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12220081 # Number of function calls committed. +system.cpu1.commit.refs 151226191 # Number of memory references committed +system.cpu1.commit.loads 79279359 # Number of loads committed +system.cpu1.commit.membars 3502305 # Number of memory barriers committed +system.cpu1.commit.branches 92953281 # Number of branches committed +system.cpu1.commit.fp_insts 403468 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 451237639 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12195676 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 336089825 69.20% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1056611 0.22% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 57564 0.01% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 35320 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 78540296 16.17% 85.60% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 69931289 14.40% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 338863536 69.00% 69.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 941904 0.19% 69.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 54586 0.01% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 39826 0.01% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 79279359 16.14% 85.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 71946832 14.65% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 485710905 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12007400 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1145678392 # The number of ROB reads -system.cpu1.rob.rob_writes 1065656273 # The number of ROB writes -system.cpu1.timesIdled 931363 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 16277462 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93962526294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 412964348 # Number of Instructions Simulated -system.cpu1.committedOps 485710905 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.591194 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.591194 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.628459 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.628459 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 611833579 # number of integer regfile reads -system.cpu1.int_regfile_writes 362533704 # number of integer regfile writes -system.cpu1.fp_regfile_reads 622107 # number of floating regfile reads -system.cpu1.fp_regfile_writes 321740 # number of floating regfile writes -system.cpu1.cc_regfile_reads 111613116 # number of cc regfile reads -system.cpu1.cc_regfile_writes 112230966 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1145938750 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14868837 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5274603 # number of replacements -system.cpu1.dcache.tags.tagsinuse 426.947513 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 137535053 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5275114 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.072432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.947513 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.833882 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.833882 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 308540922 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 308540922 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 72744707 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72744707 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 60628902 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 60628902 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161948 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 161948 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50338 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 50338 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624470 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1624470 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1636906 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1636906 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 133373609 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 133373609 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 133535557 # number of overall hits -system.cpu1.dcache.overall_hits::total 133535557 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6201374 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6201374 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6969409 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6969409 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662990 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 662990 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447840 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 447840 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 255439 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 255439 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 200646 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 200646 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13170783 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13170783 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13833773 # number of overall misses -system.cpu1.dcache.overall_misses::total 13833773 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 88228717500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 88228717500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 123237994379 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 123237994379 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20350455489 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20350455489 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3706894000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3706894000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4288443500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4288443500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6003000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6003000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 211466711879 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 211466711879 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 211466711879 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 78946081 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 78946081 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67598311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67598311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824938 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 824938 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498178 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 498178 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1879909 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1879909 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1837552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146544392 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146544392 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 147369330 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 147369330 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.103100 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.103100 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.803685 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.803685 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.898956 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.898956 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135878 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135878 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089876 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.089876 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093871 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.093871 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 491126085 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12144608 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1154417922 # The number of ROB reads +system.cpu1.rob.rob_writes 1077060232 # The number of ROB writes +system.cpu1.timesIdled 910594 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 20149630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94205821171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 416740074 # Number of Instructions Simulated +system.cpu1.committedOps 491126085 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.593241 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.593241 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.627652 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.627652 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 618723699 # number of integer regfile reads +system.cpu1.int_regfile_writes 366638237 # number of integer regfile writes +system.cpu1.fp_regfile_reads 681038 # number of floating regfile reads +system.cpu1.fp_regfile_writes 305796 # number of floating regfile writes +system.cpu1.cc_regfile_reads 111144597 # number of cc regfile reads +system.cpu1.cc_regfile_writes 111901561 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1146158029 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14345264 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5008277 # number of replacements +system.cpu1.dcache.tags.tagsinuse 444.234833 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 141116395 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5008789 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.173755 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.234833 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867646 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.867646 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 313835409 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 313835409 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73808968 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73808968 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 63012404 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 63012404 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 166300 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 166300 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 49799 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 49799 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1689842 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1689842 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1700596 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1700596 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 136821372 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 136821372 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 136987672 # number of overall hits +system.cpu1.dcache.overall_hits::total 136987672 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5891473 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5891473 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6580040 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6580040 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 617645 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 617645 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 417038 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 417038 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243108 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 243108 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 189778 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 189778 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12471513 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12471513 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13089158 # number of overall misses +system.cpu1.dcache.overall_misses::total 13089158 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92058874500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 92058874500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 133118807489 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 133118807489 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16001999882 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16001999882 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3690480000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3690480000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4542175000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4542175000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4462000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4462000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 225177681989 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 225177681989 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 225177681989 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 225177681989 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79700441 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79700441 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69592444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69592444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 783945 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 783945 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 466837 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 466837 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1932950 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1932950 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1890374 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1890374 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 149292885 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 149292885 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 150076830 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 150076830 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.073920 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.073920 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094551 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.094551 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787868 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787868 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.893327 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.893327 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125770 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125770 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083537 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083537 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087216 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087216 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15625.782296 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15625.782296 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20230.698824 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20230.698824 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 38370.603835 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 38370.603835 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15180.413643 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15180.413643 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23934.149375 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 5662057 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 20000375 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 377912 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 710012 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.982475 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.169066 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18055.362007 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18055.362007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17203.374120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17203.374120 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4151520 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 21118604 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 339495 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 658226 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.228516 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32.084123 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3411546 # number of writebacks -system.cpu1.dcache.writebacks::total 3411546 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3176462 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3176462 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5650771 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5650771 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3283 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3283 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 129585 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 129585 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8827233 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8827233 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8827233 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8827233 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3024912 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3024912 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1318638 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1318638 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 662904 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 662904 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 444557 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 444557 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125854 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125854 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 200639 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 200639 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4343550 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4343550 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5006454 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5006454 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6436 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13289 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40779010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40779010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24146673124 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24146673124 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13797097500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13797097500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19809664989 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19809664989 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1736527500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1736527500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4087933500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4087933500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5874000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5874000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64925683124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 64925683124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78722780624 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 78722780624 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 710484000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 710484000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859770500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859770500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1570254500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1570254500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.038316 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.038316 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019507 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019507 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.803580 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.803580 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.892366 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.892366 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066947 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066947 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109188 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109188 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029640 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029640 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033972 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033972 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3259663 # number of writebacks +system.cpu1.dcache.writebacks::total 3259663 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2995366 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 2995366 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5317058 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5317058 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3866 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3866 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125871 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125871 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8312424 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8312424 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8312424 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8312424 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2896107 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2896107 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1262982 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1262982 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 617580 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 617580 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 413172 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 413172 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117237 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117237 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189777 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4159089 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4159089 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4776669 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4776669 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6826 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6826 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7171 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13997 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13997 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41972381500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41972381500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27436414661 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27436414661 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14179581000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14179581000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15426665382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15426665382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1682703500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1682703500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4352455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4352455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69408796161 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69408796161 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83588377161 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83588377161 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 764918000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 764918000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 914224500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 914224500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1679142500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1679142500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018148 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018148 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787785 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787785 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.885046 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.885046 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060652 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060652 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027859 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027859 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031828 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031828 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14492.690187 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21723.519940 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21723.519940 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22934.575844 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110392.169049 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125458.996060 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125458.996060 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118161.976070 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 118161.976070 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17499.302791 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112059.478465 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 112059.478465 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 127489.122856 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 127489.122856 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119964.456669 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119964.456669 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5512111 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.811781 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 185560716 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5512623 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.661057 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811781 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5544230 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.780204 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 185921865 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5544742 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.531202 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.780204 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980039 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980039 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 388319278 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 388319278 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 185560716 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 185560716 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 185560716 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 185560716 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 185560716 # number of overall hits -system.cpu1.icache.overall_hits::total 185560716 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5842603 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5842603 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5842603 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5842603 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5842603 # number of overall misses -system.cpu1.icache.overall_misses::total 5842603 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 60453928731 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 60453928731 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 60453928731 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 60453928731 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 60453928731 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 60453928731 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 191403319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 191403319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 191403319 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 191403319 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 191403319 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 191403319 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030525 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030525 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030525 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030525 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030525 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030525 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10347.088230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10347.088230 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8745745 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 74 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 694595 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.591143 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 74 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 389132386 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 389132386 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 185921865 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 185921865 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 185921865 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 185921865 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 185921865 # number of overall hits +system.cpu1.icache.overall_hits::total 185921865 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5871956 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5871956 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5871956 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5871956 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5871956 # number of overall misses +system.cpu1.icache.overall_misses::total 5871956 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64156067699 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 64156067699 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 64156067699 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 64156067699 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 64156067699 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 64156067699 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 191793821 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 191793821 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 191793821 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 191793821 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 191793821 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 191793821 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030616 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030616 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030616 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030616 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030616 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030616 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10925.842717 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10925.842717 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10925.842717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10925.842717 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9696468 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 348 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 701587 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.820763 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 69.600000 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 329963 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 329963 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 329963 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 329963 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 329963 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 329963 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5512640 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5512640 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5512640 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5512640 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5512640 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5512640 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 327212 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 327212 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 327212 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 327212 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 327212 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 327212 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5544744 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5544744 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5544744 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5544744 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5544744 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5544744 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54827935019 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 54827935019 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54827935019 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 54827935019 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54827935019 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 54827935019 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028801 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028801 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9945.858068 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 57863828928 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 57863828928 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 57863828928 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 57863828928 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 57863828928 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 57863828928 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10435.798105 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7331800 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7336274 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4099 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6820164 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6823757 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3326 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 897950 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2207622 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13131.101294 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 18758807 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2223617 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.436168 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9687561014000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5032.423158 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.618743 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.333738 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3261.641393 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.864250 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.220012 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.307155 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004799 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005269 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199075 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229484 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055677 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.801459 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1285 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14630 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 250 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 623 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 379 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1375 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5281 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4801 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3028 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078430 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892944 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 369655582 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 369655582 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 548671 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168948 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 717619 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3411534 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3411534 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70189 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 70189 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33871 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 33871 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 868044 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 868044 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4905635 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4905635 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2835466 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2835466 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 174715 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 174715 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 548671 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168948 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4905635 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3703510 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9326764 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 548671 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168948 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4905635 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3703510 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9326764 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11848 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8514 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20362 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139128 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 139128 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166752 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 166752 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 16 # 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number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1223803 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1851167 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11848 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8514 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 607002 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1223803 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1851167 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446786000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 357242500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 804028500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2996930500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2996930500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3475655499 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3475655499 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5675991 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5675991 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11909522998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11909522998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17320734000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17320734000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31800458472 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31800458472 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219320 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219320 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101167 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254968 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254968 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.537852 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.537852 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042058 # 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average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219807 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35692.532902 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55678.903673 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32979.671319 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32979.671319 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18419.859853 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18419.859853 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 496937.125000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 950963 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10318053 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7301053 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 10168977 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 922205 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 460948 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364065 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477238 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1860044 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1122762 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5512640 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6310959 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 550275 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 443547 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16537003 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17033306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 391276 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1237529 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 35199114 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352809840 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 540363378 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4484152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 899077066 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 11781593 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 34442064 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.358530 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479569 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 21930537 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11284587 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 520648 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 520636 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 828450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10092423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4200793 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 9135588 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 838070 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 423377 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345989 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 462829 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1138657 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1069017 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5544744 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688366 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 419379 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 411859 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16633313 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16198816 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385145 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1121131 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34338405 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 354864624 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 515112392 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1411752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4066000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 875454768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5438478 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 27571945 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.031057 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.173474 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 22093559 64.15% 64.15% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12348505 35.85% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26715663 96.89% 96.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 856270 3.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 34442064 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14907193441 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 27571945 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14479823475 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 189176968 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 180399406 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8273171683 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8321735869 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7832975507 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7455510168 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 214052518 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 208987874 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 677527956 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 613445865 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40376 # Transaction distribution -system.iobus.trans_dist::ReadResp 40376 # Transaction distribution -system.iobus.trans_dist::WriteReq 136648 # Transaction distribution -system.iobus.trans_dist::WriteResp 136648 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47800 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40368 # Transaction distribution +system.iobus.trans_dist::ReadResp 40368 # Transaction distribution +system.iobus.trans_dist::WriteReq 136681 # Transaction distribution +system.iobus.trans_dist::WriteResp 136681 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2986,18 +2990,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122682 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3007,18 +3011,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36303000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3038,7 +3042,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -3046,71 +3050,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569813871 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565777885 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92765000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147982000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115623 # number of replacements -system.iocache.tags.tagsinuse 11.307008 # Cycle average of tags in use +system.iocache.tags.replacements 115577 # number of replacements +system.iocache.tags.tagsinuse 11.305567 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115639 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9081350424000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.848834 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.458174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466136 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706688 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9126912991000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.834509 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.471058 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239657 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466941 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041144 # Number of tag accesses -system.iocache.tags.data_accesses 1041144 # Number of data accesses +system.iocache.tags.tag_accesses 1040721 # Number of tag accesses +system.iocache.tags.data_accesses 1040721 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8952 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8915 # number of demand (read+write) misses -system.iocache.demand_misses::total 8955 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses +system.iocache.demand_misses::total 8908 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8915 # number of overall misses -system.iocache.overall_misses::total 8955 # number of overall misses +system.iocache.overall_misses::realview.ide 8868 # number of overall misses +system.iocache.overall_misses::total 8908 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1625113033 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1630308033 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1707562057 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1712757057 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12635282838 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12635282838 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13922427828 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13922427828 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1625113033 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1630677033 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1707562057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1713126057 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1625113033 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1630677033 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1707562057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1713126057 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8915 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8952 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8915 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8955 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8915 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8955 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3125,54 +3129,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182116.625670 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 192553.231507 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192336.558899 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130447.753429 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130447.753429 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182096.821106 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192313.208015 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182096.821106 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 30957 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192313.208015 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35527 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3511 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.908489 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.118770 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106693 # number of writebacks -system.iocache.writebacks::total 106693 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8952 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8915 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8955 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8915 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8955 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179363033 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1182708033 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1264162057 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1267507057 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298882838 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7298882838 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8586027828 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8586027828 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1179363033 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1182927033 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1264162057 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1267726057 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1179363033 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1182927033 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1264162057 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1267726057 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3187,623 +3191,616 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142553.231507 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 142336.558899 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80447.753429 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80447.753429 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1604376 # number of replacements -system.l2c.tags.tagsinuse 63973.571253 # Cycle average of tags in use -system.l2c.tags.total_refs 5805157 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1664778 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.487046 # Average number of references to valid blocks. +system.l2c.tags.replacements 1523284 # number of replacements +system.l2c.tags.tagsinuse 63784.617798 # Cycle average of tags in use +system.l2c.tags.total_refs 5785768 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1584080 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.652447 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16659.203027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 347.238411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 480.079854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4726.149973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 13722.940289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19518.694683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 39.930664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 37.878689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2515.843694 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3528.824222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2396.787747 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.254199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007325 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.209395 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.297832 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000578 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.038389 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.053846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976159 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10879 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 17262.204967 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 288.051541 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 383.464514 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4972.263689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12806.585942 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17387.012671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.287470 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 93.857044 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2455.379438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4782.512624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3267.997898 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.263400 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005851 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.195413 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.265305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001301 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001432 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.037466 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.072975 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.973276 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10918 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 244 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49634 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2538 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5035 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41740 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.166595 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.757355 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 71725289 # Number of tag accesses +system.l2c.tags.data_accesses 71725289 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2493194 # number of Writeback hits +system.l2c.Writeback_hits::total 2493194 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.630379 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.582188 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.606465 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.625565 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.606158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.616713 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.767553 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.388438 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.665485 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215848 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.149076 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.234829 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.322484 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.322484 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73588.862847 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73670.670892 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73627.833592 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76501.501360 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76430.731355 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.773718 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168727.781569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139531.928329 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 164139.771808 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137511.142948 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134704.947242 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157038.604224 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 60137 # Transaction distribution -system.membus.trans_dist::ReadResp 1008264 # Transaction distribution -system.membus.trans_dist::WriteReq 38676 # Transaction distribution -system.membus.trans_dist::WriteResp 38676 # Transaction distribution -system.membus.trans_dist::Writeback 1353245 # Transaction distribution -system.membus.trans_dist::CleanEvict 256072 # Transaction distribution -system.membus.trans_dist::UpgradeReq 446472 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 317458 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117838 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 689582 # Transaction distribution -system.membus.trans_dist::ReadExResp 667715 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 948127 # Transaction distribution +system.membus.trans_dist::ReadReq 60136 # Transaction distribution +system.membus.trans_dist::ReadResp 965246 # Transaction distribution +system.membus.trans_dist::WriteReq 38656 # Transaction distribution +system.membus.trans_dist::WriteResp 38656 # Transaction distribution +system.membus.trans_dist::Writeback 1296915 # Transaction distribution +system.membus.trans_dist::CleanEvict 243951 # Transaction distribution +system.membus.trans_dist::UpgradeReq 452760 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 304384 # Transaction distribution +system.membus.trans_dist::UpgradeResp 121976 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 662340 # Transaction distribution +system.membus.trans_dist::ReadExResp 641281 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 905110 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122682 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5660502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5810264 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6152907 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5450054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5599774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5941804 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54004 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182936448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 183146836 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7268096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190414932 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 670794 # Total snoops (count) -system.membus.snoop_fanout::samples 4218827 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174888448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 175098585 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7250496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 182349081 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 659296 # Total snoops (count) +system.membus.snoop_fanout::samples 4073524 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4218827 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4073524 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4218827 # Request fanout histogram -system.membus.reqLayer0.occupancy 97993999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4073524 # Request fanout histogram +system.membus.reqLayer0.occupancy 98143499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22746984 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22747469 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9381331556 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9016528809 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8783305125 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8432717951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229295864 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 230475062 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3857,50 +3854,56 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 60139 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4816420 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38676 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3889503 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1527175 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 497158 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 330081 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 827239 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 247 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1142368 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1142368 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4763508 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 11519638 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5862055 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2048796 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 167370 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 156134 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11236 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 60138 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4755206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38656 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38656 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3790142 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1500041 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 506577 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 316392 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 822969 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1127077 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1127077 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4702306 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8767118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899331 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15666449 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271825986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202528722 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 474354708 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3515812 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13605383 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.134927 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.341646 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9146865 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6326733 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15473598 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 285949105 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 180962856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 466911961 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3420267 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13372960 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.331842 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.472656 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11769647 86.51% 86.51% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1835736 13.49% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8946480 66.90% 66.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4415244 33.02% 99.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11236 0.08% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13605383 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8891301093 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13372960 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8776402150 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2589000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2601544 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5132723331 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5338662327 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4211299918 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3896618177 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14670 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 14407 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 7288 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 7094 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 591f883e9..df2086525 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.562170 # Number of seconds simulated -sim_ticks 51562169701000 # Number of ticks simulated -final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.291801 # Number of seconds simulated +sim_ticks 51291801227000 # Number of ticks simulated +final_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82472 # Simulator instruction rate (inst/s) -host_op_rate 96938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3850541751 # Simulator tick rate (ticks/s) -host_mem_usage 726532 # Number of bytes of host memory used -host_seconds 13390.89 # Real time elapsed on the host -sim_insts 1104366834 # Number of instructions simulated -sim_ops 1298086167 # Number of ops (including micro ops) simulated +host_inst_rate 104106 # Simulator instruction rate (inst/s) +host_op_rate 122333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6261768882 # Simulator tick rate (ticks/s) +host_mem_usage 729608 # Number of bytes of host memory used +host_seconds 8191.26 # Real time elapsed on the host +sim_insts 852762944 # Number of instructions simulated +sim_ops 1002063356 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory -system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory +system.physmem.bytes_read::total 81891560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69986404 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2467786 # Number of read requests accepted -system.physmem.writeReqs 2184211 # Number of write requests accepted -system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue -system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 149005 # Per bank write bursts -system.physmem.perBankRdBursts::1 156339 # Per bank write bursts -system.physmem.perBankRdBursts::2 155955 # Per bank write bursts -system.physmem.perBankRdBursts::3 150628 # Per bank write bursts -system.physmem.perBankRdBursts::4 148084 # Per bank write bursts -system.physmem.perBankRdBursts::5 159303 # Per bank write bursts -system.physmem.perBankRdBursts::6 149188 # Per bank write bursts -system.physmem.perBankRdBursts::7 152515 # Per bank write bursts -system.physmem.perBankRdBursts::8 150862 # Per bank write bursts -system.physmem.perBankRdBursts::9 179370 # Per bank write bursts -system.physmem.perBankRdBursts::10 150320 # Per bank write bursts -system.physmem.perBankRdBursts::11 155893 # Per bank write bursts -system.physmem.perBankRdBursts::12 152080 # Per bank write bursts -system.physmem.perBankRdBursts::13 155961 # Per bank write bursts -system.physmem.perBankRdBursts::14 150556 # Per bank write bursts -system.physmem.perBankRdBursts::15 150970 # Per bank write bursts -system.physmem.perBankWrBursts::0 132106 # Per bank write bursts -system.physmem.perBankWrBursts::1 138501 # Per bank write bursts -system.physmem.perBankWrBursts::2 137398 # Per bank write bursts -system.physmem.perBankWrBursts::3 135602 # Per bank write bursts -system.physmem.perBankWrBursts::4 133392 # Per bank write bursts -system.physmem.perBankWrBursts::5 140433 # Per bank write bursts -system.physmem.perBankWrBursts::6 132940 # Per bank write bursts -system.physmem.perBankWrBursts::7 137025 # Per bank write bursts -system.physmem.perBankWrBursts::8 135656 # Per bank write bursts -system.physmem.perBankWrBursts::9 141181 # Per bank write bursts -system.physmem.perBankWrBursts::10 134433 # Per bank write bursts -system.physmem.perBankWrBursts::11 138339 # Per bank write bursts -system.physmem.perBankWrBursts::12 136301 # Per bank write bursts -system.physmem.perBankWrBursts::13 138853 # Per bank write bursts -system.physmem.perBankWrBursts::14 135122 # Per bank write bursts -system.physmem.perBankWrBursts::15 134659 # Per bank write bursts +system.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1364074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1364475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1364074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1467351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2961057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1295521 # Number of read requests accepted +system.physmem.writeReqs 1095789 # Number of write requests accepted +system.physmem.readBursts 1295521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1095789 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 82863680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue +system.physmem.bytesWritten 69985152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81891560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69986404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 141837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 78118 # Per bank write bursts +system.physmem.perBankRdBursts::1 81473 # Per bank write bursts +system.physmem.perBankRdBursts::2 82762 # Per bank write bursts +system.physmem.perBankRdBursts::3 80112 # Per bank write bursts +system.physmem.perBankRdBursts::4 77452 # Per bank write bursts +system.physmem.perBankRdBursts::5 84131 # Per bank write bursts +system.physmem.perBankRdBursts::6 77443 # Per bank write bursts +system.physmem.perBankRdBursts::7 77113 # Per bank write bursts +system.physmem.perBankRdBursts::8 74240 # Per bank write bursts +system.physmem.perBankRdBursts::9 104872 # Per bank write bursts +system.physmem.perBankRdBursts::10 79788 # Per bank write bursts +system.physmem.perBankRdBursts::11 80502 # Per bank write bursts +system.physmem.perBankRdBursts::12 82162 # Per bank write bursts +system.physmem.perBankRdBursts::13 82091 # Per bank write bursts +system.physmem.perBankRdBursts::14 76266 # Per bank write bursts +system.physmem.perBankRdBursts::15 76220 # Per bank write bursts +system.physmem.perBankWrBursts::0 65460 # Per bank write bursts +system.physmem.perBankWrBursts::1 68510 # Per bank write bursts +system.physmem.perBankWrBursts::2 70351 # Per bank write bursts +system.physmem.perBankWrBursts::3 69772 # Per bank write bursts +system.physmem.perBankWrBursts::4 67735 # Per bank write bursts +system.physmem.perBankWrBursts::5 71090 # Per bank write bursts +system.physmem.perBankWrBursts::6 66311 # Per bank write bursts +system.physmem.perBankWrBursts::7 67773 # Per bank write bursts +system.physmem.perBankWrBursts::8 64800 # Per bank write bursts +system.physmem.perBankWrBursts::9 72411 # Per bank write bursts +system.physmem.perBankWrBursts::10 67462 # Per bank write bursts +system.physmem.perBankWrBursts::11 69064 # Per bank write bursts +system.physmem.perBankWrBursts::12 70238 # Per bank write bursts +system.physmem.perBankWrBursts::13 69848 # Per bank write bursts +system.physmem.perBankWrBursts::14 66451 # Per bank write bursts +system.physmem.perBankWrBursts::15 66242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 51562168447500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 51291799925500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2446501 # Read request sizes (log2) +system.physmem.readPktSize::6 1274236 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2181638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1093216 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 662611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 153233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 129247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,161 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 12367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 46525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 65687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 68922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 68990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 505036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.648619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.485841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.471265 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 200174 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 119366 23.64% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 47641 9.43% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24555 4.86% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19234 3.81% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12076 2.39% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11328 2.24% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8283 1.64% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62379 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 505036 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.744284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 264.086390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 62410 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads -system.physmem.totQLat 61876185756 # Total ticks spent queuing -system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.520677 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.965036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.067360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 59523 95.37% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 900 1.44% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 0.09% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 320 0.51% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 34 0.05% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 343 0.55% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 222 0.36% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.03% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 51 0.08% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 131 0.21% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 40 0.06% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 504 0.81% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.06% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 123 0.20% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62413 # Writes before turning the bus around for reads +system.physmem.totQLat 33295532684 # Total ticks spent queuing +system.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6473725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 2056722 # Number of row buffer hits during reads -system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes -system.physmem.avgGap 11083878.27 # Average gap between requests -system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.871313 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing +system.physmem.readRowHits 1061078 # Number of row buffer hits during reads +system.physmem.writeRowHits 822147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes +system.physmem.avgGap 21449247.45 # Average gap between requests +system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.513169 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states +system.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states +system.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.883816 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.516119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states +system.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states +system.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -325,27 +327,27 @@ system.realview.nvmem.num_reads::cpu.data 5 # N system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 288825634 # Number of BP lookups -system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits +system.cpu.branchPred.lookups 225483777 # Number of BP lookups +system.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104065621 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,84 +378,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 1430156 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 951545 # Table walker walks requested +system.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217117628 # DTB read hits -system.cpu.dtb.read_misses 1002788 # DTB read misses -system.cpu.dtb.write_hits 192115888 # DTB write hits -system.cpu.dtb.write_misses 427368 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 170217039 # DTB read hits +system.cpu.dtb.read_misses 674912 # DTB read misses +system.cpu.dtb.write_hits 148367148 # DTB write hits +system.cpu.dtb.write_misses 276633 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218120416 # DTB read accesses -system.cpu.dtb.write_accesses 192543256 # DTB write accesses +system.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170891951 # DTB read accesses +system.cpu.dtb.write_accesses 148643781 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409233516 # DTB hits -system.cpu.dtb.misses 1430156 # DTB misses -system.cpu.dtb.accesses 410663672 # DTB accesses +system.cpu.dtb.hits 318584187 # DTB hits +system.cpu.dtb.misses 951545 # DTB misses +system.cpu.dtb.accesses 319535732 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,877 +488,881 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 177415 # Table walker walks requested -system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walks 161585 # Table walker walks requested +system.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 461294711 # ITB inst hits -system.cpu.itb.inst_misses 177415 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 358536824 # ITB inst hits +system.cpu.itb.inst_misses 161585 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 461472126 # ITB inst accesses -system.cpu.itb.hits 461294711 # DTB hits -system.cpu.itb.misses 177415 # DTB misses -system.cpu.itb.accesses 461472126 # DTB accesses -system.cpu.numCycles 2141240199 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 358698409 # ITB inst accesses +system.cpu.itb.hits 358536824 # DTB hits +system.cpu.itb.misses 161585 # DTB misses +system.cpu.itb.accesses 358698409 # DTB accesses +system.cpu.numCycles 1657263364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434692108 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 440187114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued -system.cpu.iq.rate 0.633727 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued +system.cpu.iq.rate 0.634165 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 272684 # number of nop insts executed -system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed -system.cpu.iew.exec_branches 255119365 # Number of branches executed -system.cpu.iew.exec_stores 192124980 # Number of stores executed -system.cpu.iew.exec_rate 0.627523 # Inst execution rate -system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back -system.cpu.iew.wb_producers 573421420 # num instructions producing a value -system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value +system.cpu.iew.exec_nop 222579 # number of nop insts executed +system.cpu.iew.exec_refs 318568485 # number of memory reference insts executed +system.cpu.iew.exec_branches 197267293 # Number of branches executed +system.cpu.iew.exec_stores 148362844 # Number of stores executed +system.cpu.iew.exec_rate 0.627402 # Inst execution rate +system.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back +system.cpu.iew.wb_producers 440084197 # num instructions producing a value +system.cpu.iew.wb_consumers 711913770 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623840 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1104366834 # Number of instructions committed -system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle +system.cpu.commit.committedInsts 852762944 # Number of instructions committed +system.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 393173853 # Number of memory references committed -system.cpu.commit.loads 204756836 # Number of loads committed -system.cpu.commit.membars 9104821 # Number of memory barriers committed -system.cpu.commit.branches 246834909 # Number of branches committed -system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. -system.cpu.commit.function_calls 30876862 # Number of function calls committed. +system.cpu.commit.refs 306001487 # Number of memory references committed +system.cpu.commit.loads 160395163 # Number of loads committed +system.cpu.commit.membars 6971183 # Number of memory barriers committed +system.cpu.commit.branches 190333133 # Number of branches committed +system.cpu.commit.fp_insts 897329 # Number of committed floating point instructions. +system.cpu.commit.int_insts 920660333 # Number of committed integer instructions. +system.cpu.commit.function_calls 25420821 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 693695163 69.23% 69.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2156692 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98172 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction -system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3405665880 # The number of ROB reads -system.cpu.rob.rob_writes 2734432791 # The number of ROB writes -system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1104366834 # Number of Instructions Simulated -system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads -system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads -system.cpu.int_regfile_writes 940526203 # number of integer regfile writes -system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads -system.cpu.fp_regfile_writes 765828 # number of floating regfile writes -system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads -system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes -system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads -system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes -system.cpu.dcache.tags.replacements 13614186 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1002063356 # Class of committed instruction +system.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2620126782 # The number of ROB reads +system.cpu.rob.rob_writes 2119163855 # The number of ROB writes +system.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 852762944 # Number of Instructions Simulated +system.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.943405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.514561 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1230978083 # number of integer regfile reads +system.cpu.int_regfile_writes 734956592 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462594 # number of floating regfile reads +system.cpu.fp_regfile_writes 785720 # number of floating regfile writes +system.cpu.cc_regfile_reads 226481409 # number of cc regfile reads +system.cpu.cc_regfile_writes 227147205 # number of cc regfile writes +system.cpu.misc_regfile_reads 2590605655 # number of misc regfile reads +system.cpu.misc_regfile_writes 27218545 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9745793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972785 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 284478201 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9746305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.188313 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 2742937500 # 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average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55300 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30047.955089 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30047.955089 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28443.120825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28443.120825 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 50799342 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1609216 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.567758 # 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number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7545853 # number of writebacks +system.cpu.dcache.writebacks::total 7545853 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4464090 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4464090 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9352283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9352283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6863 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6863 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220342 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 220342 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13816373 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13816373 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13816373 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13816373 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5135668 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5135668 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2021477 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2021477 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1176591 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1176591 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226326 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226326 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230016 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230016 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7157145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7157145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8333736 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8333736 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85690864500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 85690864500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79882963880 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79882963880 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24040362000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24040362000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 88797727789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 88797727789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3265448000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3265448000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060989 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060989 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23134.060911 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23134.060911 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22752.603440 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22752.603440 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173152.610310 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173152.610310 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 16756542 # number of replacements -system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15058288 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916796 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 342301291 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15058800 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.730981 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916796 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits -system.cpu.icache.overall_hits::total 443237235 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses -system.cpu.icache.overall_misses::total 17559241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13271300000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006808 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785587 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785587 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005633 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040343 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040343 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.409431 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.409431 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.031106 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.031106 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128612.839940 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70763.655401 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70763.655401 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129127.304187 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129127.304187 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124571.716553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124571.716553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129275.526257 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1898399 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40298 # Transaction distribution system.iobus.trans_dist::ReadResp 40298 # Transaction distribution @@ -1622,7 +1637,7 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565777121 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1633,16 +1648,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.417924 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103107119000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.546641 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.871282 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1661,19 +1676,19 @@ system.iocache.demand_misses::total 8853 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8813 # number of overall misses system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5101000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670573105 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675674105 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13828326016 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13828326016 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5452000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1670573105 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1676025105 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5452000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1670573105 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1676025105 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -1700,24 +1715,24 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137864.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189557.824237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189341.706780 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129643.797495 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129643.797495 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34546 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3397 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.169561 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1736,19 +1751,19 @@ system.iocache.demand_mshr_misses::total 8853 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3251000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229923105 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1233174105 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3452000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1229923105 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1233375105 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3452000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1229923105 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1233375105 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1762,73 +1777,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87864.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139557.824237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139341.706780 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54987 # Transaction distribution -system.membus.trans_dist::ReadResp 601962 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::Writeback 2181638 # Transaction distribution -system.membus.trans_dist::CleanEvict 277040 # Transaction distribution -system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution +system.membus.trans_dist::ReadReq 54973 # Transaction distribution +system.membus.trans_dist::ReadResp 419838 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::Writeback 1093216 # Transaction distribution +system.membus.trans_dist::CleanEvict 195829 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35178 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution -system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35181 # Transaction distribution +system.membus.trans_dist::ReadExReq 912510 # Transaction distribution +system.membus.trans_dist::ReadExResp 912510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 364865 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3830691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3960313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4301676 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2989 # Total snoops (count) -system.membus.snoop_fanout::samples 5154600 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3147 # Total snoops (count) +system.membus.snoop_fanout::samples 2799608 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5154600 # Request fanout histogram -system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2799608 # Request fanout histogram +system.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1839,11 +1854,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1883,6 +1898,6 @@ system.realview.realview_io.osc_smb.clock 20000 # C system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index 3b35220e8..e1c9b6ef6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926984 # Simulator instruction rate (inst/s) -host_op_rate 1089358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48121696814 # Simulator tick rate (ticks/s) -host_mem_usage 716268 # Number of bytes of host memory used -host_seconds 1062.12 # Real time elapsed on the host +host_inst_rate 1154147 # Simulator instruction rate (inst/s) +host_op_rate 1356312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59914222846 # Simulator tick rate (ticks/s) +host_mem_usage 725376 # Number of bytes of host memory used +host_seconds 853.07 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -414,9 +414,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1722572 # number of replacements system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor @@ -439,8 +439,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits @@ -554,12 +554,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks system.cpu.l2cache.writebacks::total 1503689 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution @@ -569,28 +575,28 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram +system.cpu.toL2Bus.snoops 1954373 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -708,7 +714,7 @@ system.membus.trans_dist::ReadResp 525878 # Tr system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution system.membus.trans_dist::Writeback 1610320 # Transaction distribution -system.membus.trans_dist::CleanEvict 228940 # Transaction distribution +system.membus.trans_dist::CleanEvict 225581 # Transaction distribution system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution @@ -720,11 +726,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) @@ -734,17 +740,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3922914 # Request fanout histogram +system.membus.snoop_fanout::samples 3921686 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3922914 # Request fanout histogram +system.membus.snoop_fanout::total 3921686 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index f07b9fa73..e3c32f3fb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,74 +4,74 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 873779 # Simulator instruction rate (inst/s) -host_op_rate 1027923 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42295108650 # Simulator tick rate (ticks/s) -host_mem_usage 724108 # Number of bytes of host memory used -host_seconds 1116.37 # Real time elapsed on the host +host_inst_rate 1096625 # Simulator instruction rate (inst/s) +host_op_rate 1290081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53081906922 # Simulator tick rate (ticks/s) +host_mem_usage 734248 # Number of bytes of host memory used +host_seconds 889.51 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory -system.physmem.bytes_read::total 116483508 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 152640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 127168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3766772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 62976200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 221312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 220864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2509128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 46395632 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419264 # Number of bytes read from this memory +system.physmem.bytes_read::total 116788980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3766772 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2509128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6275900 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100984448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101059432 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101005032 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 99263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 984016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39312 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 724948 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6551 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1865371 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1577882 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1580456 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 79776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1333766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 982608 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2473462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 79776 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 132917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2138739 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2139175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2138739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 79776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1334202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 982608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4612637 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -303,11 +303,11 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 15195 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 6272773 # number of replacements +system.cpu0.dcache.tags.replacements 6272771 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy @@ -317,40 +317,40 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919852 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919852 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262009 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 262009 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits -system.cpu0.dcache.overall_hits::total 167350352 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036568 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036568 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134763 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134763 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350417 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350417 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475590 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475590 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831711 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 831711 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses -system.cpu0.dcache.overall_misses::total 5557176 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158575 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158575 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4784972 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4784972 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557111 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557111 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) @@ -373,16 +373,16 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760442 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760442 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072239 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,8 +391,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks -system.cpu0.dcache.writebacks::total 4472506 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4465852 # number of writebacks +system.cpu0.dcache.writebacks::total 4465852 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 5539081 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use @@ -450,139 +450,139 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2713035 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2711851 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16210.481258 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 18787660 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2727832 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.887396 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 5681.130997 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.077110 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.001745 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4560.666382 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5858.605025 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.346749 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003240 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003479 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278361 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357581 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989409 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15935 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1157 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4616 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5323 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4610 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972595 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 396153496 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 396153496 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271024 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 142798 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 413822 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4465852 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4465852 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3520 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3520 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634528 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 634528 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4971317 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4971317 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2943098 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2943098 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222986 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 222986 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271024 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 142798 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4971317 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3577626 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8962765 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271024 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 142798 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4971317 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3577626 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8962765 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11253 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8486 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 19739 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128216 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128216 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158575 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158575 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709702 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709702 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568281 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 568281 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1258239 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1258239 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608349 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 608349 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11253 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8486 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 568281 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1967941 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2555961 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11253 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8486 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 568281 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1967941 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2555961 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282277 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151284 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 433561 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4465852 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4465852 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131736 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131736 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158575 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158575 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282277 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151284 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11518726 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282277 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151284 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11518726 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056093 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973280 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973280 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527962 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527962 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102585 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102585 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299485 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299485 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731774 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731774 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056093 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102585 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354867 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.221896 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056093 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102585 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354867 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.221896 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,46 +591,52 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks -system.cpu0.l2cache.writebacks::total 1573891 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1571493 # number of writebacks +system.cpu0.l2cache.writebacks::total 1571493 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.snoop_filter.tot_requests 24275029 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12358536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 471082 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 471076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4465852 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 7344601 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131736 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158575 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290311 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19736583 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37534931 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 640924169 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3360861 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 1000009861 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4846239 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 29334646 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.024894 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.155804 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28604393 97.51% 97.51% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 730247 2.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 29334646 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -847,36 +853,36 @@ system.cpu1.dcache.tags.tag_accesses 348813711 # Nu system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990146 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990146 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits -system.cpu1.dcache.overall_hits::total 160875656 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048851 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048851 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687710 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687710 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875564 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875564 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453330 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453330 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses -system.cpu1.dcache.overall_misses::total 5603811 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158898 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158898 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811552 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811552 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603903 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603903 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) @@ -895,18 +901,18 @@ system.cpu1.dcache.overall_accesses::cpu1.data 166479467 system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018527 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018527 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071973 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071973 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029073 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029073 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -917,8 +923,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks -system.cpu1.dcache.writebacks::total 4032489 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4029235 # number of writebacks +system.cpu1.dcache.writebacks::total 4029235 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 4741297 # number of replacements system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use @@ -975,98 +981,98 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2278625 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 2280083 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13449.950084 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17410791 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2296131 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.582664 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 5225.723861 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.459971 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.577044 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.184130 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5219.005079 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.318953 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004178 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005345 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173900 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.318543 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.820920 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15943 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1612 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5944 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4501 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3801 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973083 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 360471879 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 360471879 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324612 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 139654 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 464266 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 4029235 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 4029235 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3866 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 3866 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614223 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614223 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4216163 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4216163 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057520 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3057520 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161092 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 161092 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324612 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 139654 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4216163 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3671743 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8352172 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324612 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 139654 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4216163 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3671743 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8352172 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12357 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9710 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 22067 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133787 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 133787 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158898 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158898 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701667 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 701667 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 525646 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 525646 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239873 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1239873 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265754 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 265754 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12357 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9710 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 525646 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1941540 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2489253 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12357 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9710 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 525646 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1941540 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2489253 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336969 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149364 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 486333 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 4029235 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4029235 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137653 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137653 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158898 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158898 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) @@ -1075,41 +1081,41 @@ system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336969 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149364 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10841425 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336969 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149364 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 10841425 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065009 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.045374 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971915 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971915 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533226 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533226 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110853 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110853 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288517 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288517 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622599 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622599 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065009 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110853 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345883 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229606 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065009 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110853 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345883 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229606 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1118,46 +1124,52 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks -system.cpu1.l2cache.writebacks::total 1184748 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1182496 # number of writebacks +system.cpu1.l2cache.writebacks::total 1182496 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.snoop_filter.tot_requests 22040452 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11258515 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 465210 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 465207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4029235 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 6656743 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137653 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158898 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296551 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643588 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34068144 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617159548 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3842126 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 925433620 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4444908 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 26656221 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.027820 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.164457 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 25914657 97.22% 97.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 741561 2.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 26656221 # Request fanout histogram system.iobus.trans_dist::ReadReq 40295 # Transaction distribution system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136634 # Transaction distribution @@ -1270,192 +1282,192 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1751385 # number of replacements -system.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use -system.l2c.tags.total_refs 6017106 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks. +system.l2c.tags.replacements 1756378 # number of replacements +system.l2c.tags.tagsinuse 62298.874763 # Cycle average of tags in use +system.l2c.tags.total_refs 4716146 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1814465 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.599194 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 85814440 # Number of tag accesses -system.l2c.tags.data_accesses 85814440 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits -system.l2c.Writeback_hits::total 2758639 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1481 # 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number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses -system.l2c.demand_misses::total 1833467 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses -system.l2c.overall_misses::cpu0.inst 54154 # number of overall misses -system.l2c.overall_misses::cpu0.data 996948 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses -system.l2c.overall_misses::cpu1.inst 37696 # number of overall misses -system.l2c.overall_misses::cpu1.data 733404 # number of overall misses -system.l2c.overall_misses::total 1833467 # number of overall misses -system.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses) +system.l2c.tags.occ_blocks::writebacks 34280.883889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.238820 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 58.953050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3333.891398 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6982.835280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.005625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 424.754545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2990.314104 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13873.998053 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.523085 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000900 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004700 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045629 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.211700 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.950605 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 228 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 57859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 548 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5562 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48240 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.882858 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74820318 # Number of tag accesses +system.l2c.tags.data_accesses 74820318 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2753989 # number of Writeback hits +system.l2c.Writeback_hits::total 2753989 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13132 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10939 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24071 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1512 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1301 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2813 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 319600 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 264468 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 584068 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6283 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4584 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 512119 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 747634 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5445 # 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number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15209 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 816140 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 547219 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 1363359 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2385 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1987 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 56162 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 181808 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3458 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3451 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 39211 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 186749 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 475211 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2385 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1987 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 56162 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 997948 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3451 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 39211 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 733968 # number of demand (read+write) misses +system.l2c.demand_misses::total 1838570 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2385 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1987 # number of overall misses +system.l2c.overall_misses::cpu0.inst 56162 # number of overall misses +system.l2c.overall_misses::cpu0.data 997948 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3458 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3451 # number of overall misses +system.l2c.overall_misses::cpu1.inst 39211 # number of overall misses +system.l2c.overall_misses::cpu1.data 733968 # number of overall misses +system.l2c.overall_misses::total 1838570 # number of overall misses +system.l2c.Writeback_accesses::writebacks 2753989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2753989 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71829 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 65059 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136888 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9320 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8702 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18022 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1135740 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 811687 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1947427 # number of ReadExReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6571 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 568281 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 929442 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8903 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7019 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 525646 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 882344 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2936874 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6571 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 568281 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 2065182 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8903 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7019 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 525646 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1694031 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4884301 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses +system.l2c.overall_accesses::cpu0.itb.walker 6571 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 568281 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 2065182 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8903 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7019 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 525646 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1694031 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4884301 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.817177 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831860 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.824156 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.837768 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850494 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.843913 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.718598 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.674175 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.700082 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.302389 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098828 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.195610 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.491665 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.074596 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211651 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.161808 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.302389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.098828 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.483225 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.491665 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.074596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.433267 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.376424 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.302389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.098828 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.483225 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.491665 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.074596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.433267 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.376424 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1464,51 +1476,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1472038 # number of writebacks -system.l2c.writebacks::total 1472038 # number of writebacks +system.l2c.writebacks::writebacks 1471188 # number of writebacks +system.l2c.writebacks::total 1471188 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 82131 # Transaction distribution -system.membus.trans_dist::ReadResp 560921 # Transaction distribution +system.membus.trans_dist::ReadResp 566255 # Transaction distribution system.membus.trans_dist::WriteReq 38802 # Transaction distribution system.membus.trans_dist::WriteResp 38802 # Transaction distribution -system.membus.trans_dist::Writeback 1578732 # Transaction distribution -system.membus.trans_dist::CleanEvict 418759 # Transaction distribution -system.membus.trans_dist::UpgradeReq 328366 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314759 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149960 # Transaction distribution -system.membus.trans_dist::ReadExReq 1611572 # Transaction distribution -system.membus.trans_dist::ReadExResp 1341565 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 478790 # Transaction distribution +system.membus.trans_dist::Writeback 1577882 # Transaction distribution +system.membus.trans_dist::CleanEvict 244930 # Transaction distribution +system.membus.trans_dist::UpgradeReq 328773 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314660 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150374 # Transaction distribution +system.membus.trans_dist::ReadExReq 1610566 # Transaction distribution +system.membus.trans_dist::ReadExResp 1341014 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 484124 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6809742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7156615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6497230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6647450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344319 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 344319 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6991769 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210336476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 210547473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210588188 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 210799185 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 217946321 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 218198033 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4958639 # Request fanout histogram +system.membus.snoop_fanout::samples 4791150 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4958639 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4791150 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4958639 # Request fanout histogram +system.membus.snoop_fanout::total 4791150 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1561,35 +1573,41 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 11435399 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5875226 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1762842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 121928 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 112531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 9397 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3716153 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3715978 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2758639 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2438361 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 330513 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317480 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 647993 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2216600 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2216600 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3634020 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9937165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8498931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18436096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301383709 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 250013636 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 551397345 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117333 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11932192 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009692 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.097969 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 2753989 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1064741 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330496 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317473 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647969 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2216979 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2216979 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3633845 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9232436 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7825750 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17058186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301171869 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249940932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 551112801 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1989284 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13543939 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.291452 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.455956 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11816548 99.03% 99.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115644 0.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9605923 70.92% 70.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3928619 29.01% 99.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 9397 0.07% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11932192 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13543939 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 47d983423..ca87afb21 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 921297 # Simulator instruction rate (inst/s) -host_op_rate 1082675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47826467843 # Simulator tick rate (ticks/s) -host_mem_usage 712064 # Number of bytes of host memory used -host_seconds 1068.68 # Real time elapsed on the host +host_inst_rate 1157716 # Simulator instruction rate (inst/s) +host_op_rate 1360507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60099512933 # Simulator tick rate (ticks/s) +host_mem_usage 720388 # Number of bytes of host memory used +host_seconds 850.44 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -414,9 +414,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1722572 # number of replacements system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor @@ -439,8 +439,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits @@ -554,12 +554,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks system.cpu.l2cache.writebacks::total 1503689 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution @@ -569,28 +575,28 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram +system.cpu.toL2Bus.snoops 1954373 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -708,7 +714,7 @@ system.membus.trans_dist::ReadResp 525878 # Tr system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution system.membus.trans_dist::Writeback 1610320 # Transaction distribution -system.membus.trans_dist::CleanEvict 228940 # Transaction distribution +system.membus.trans_dist::CleanEvict 225581 # Transaction distribution system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution @@ -720,11 +726,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) @@ -734,17 +740,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3922914 # Request fanout histogram +system.membus.snoop_fanout::samples 3921686 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3922914 # Request fanout histogram +system.membus.snoop_fanout::total 3921686 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 05fb68c75..468bf5591 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.456680 # Number of seconds simulated -sim_ticks 47456679626500 # Number of ticks simulated -final_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.474700 # Number of seconds simulated +sim_ticks 47474700369500 # Number of ticks simulated +final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 503190 # Simulator instruction rate (inst/s) -host_op_rate 591944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27602071667 # Simulator tick rate (ticks/s) -host_mem_usage 755208 # Number of bytes of host memory used -host_seconds 1719.32 # Real time elapsed on the host -sim_insts 865142471 # Number of instructions simulated -sim_ops 1017738631 # Number of ops (including micro ops) simulated +host_inst_rate 631720 # Simulator instruction rate (inst/s) +host_op_rate 743100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34016391858 # Simulator tick rate (ticks/s) +host_mem_usage 766400 # Number of bytes of host memory used +host_seconds 1395.64 # Real time elapsed on the host +sim_insts 881655060 # Number of instructions simulated +sim_ops 1037101350 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 51904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 48448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2877620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38342664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 11776896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 153536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 163840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2826616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 16120336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11259712 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory -system.physmem.bytes_read::total 84057220 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2877620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2826616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5704236 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70891776 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 127360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 143744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3459124 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40376840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12078528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 91584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 86464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2488056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17058000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14991744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 410816 # Number of bytes read from this memory +system.physmem.bytes_read::total 91312260 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3459124 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2488056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5947180 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77042688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 70912360 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85370 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 599117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 184014 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2560 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44254 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 251893 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 175933 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1353915 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1107684 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77063272 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2246 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 94456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 630901 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 188727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 38964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 266544 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 234246 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6419 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1467275 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1203792 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1110258 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 60637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 807951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 248161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 339685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 237263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1771241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 60637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 120199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493821 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1206366 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 72862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 850492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 254420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 359307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 315784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1923388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 72862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 125271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1622816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1494255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 60637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 808384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 248161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 339685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 237263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3265496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1353915 # Number of read requests accepted -system.physmem.writeReqs 1110258 # Number of write requests accepted -system.physmem.readBursts 1353915 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1110258 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86619200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue -system.physmem.bytesWritten 70911104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84057220 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70912360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1623249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1622816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 72862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 850925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 254420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 359307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 315784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3546637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1467275 # Number of read requests accepted +system.physmem.writeReqs 1206366 # Number of write requests accepted +system.physmem.readBursts 1467275 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1206366 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 93873920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31680 # Total number of bytes read from write queue +system.physmem.bytesWritten 77062336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 91312260 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 77063272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 495 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 220771 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83838 # Per bank write bursts -system.physmem.perBankRdBursts::1 89540 # Per bank write bursts -system.physmem.perBankRdBursts::2 77326 # Per bank write bursts -system.physmem.perBankRdBursts::3 81695 # Per bank write bursts -system.physmem.perBankRdBursts::4 84097 # Per bank write bursts -system.physmem.perBankRdBursts::5 94926 # Per bank write bursts -system.physmem.perBankRdBursts::6 83322 # Per bank write bursts -system.physmem.perBankRdBursts::7 86179 # Per bank write bursts -system.physmem.perBankRdBursts::8 76741 # Per bank write bursts -system.physmem.perBankRdBursts::9 125350 # Per bank write bursts -system.physmem.perBankRdBursts::10 75788 # Per bank write bursts -system.physmem.perBankRdBursts::11 81366 # Per bank write bursts -system.physmem.perBankRdBursts::12 76482 # Per bank write bursts -system.physmem.perBankRdBursts::13 81797 # Per bank write bursts -system.physmem.perBankRdBursts::14 77630 # Per bank write bursts -system.physmem.perBankRdBursts::15 77348 # Per bank write bursts -system.physmem.perBankWrBursts::0 68540 # Per bank write bursts -system.physmem.perBankWrBursts::1 72321 # Per bank write bursts -system.physmem.perBankWrBursts::2 65671 # Per bank write bursts -system.physmem.perBankWrBursts::3 69464 # Per bank write bursts -system.physmem.perBankWrBursts::4 70371 # Per bank write bursts -system.physmem.perBankWrBursts::5 77894 # Per bank write bursts -system.physmem.perBankWrBursts::6 70312 # Per bank write bursts -system.physmem.perBankWrBursts::7 72647 # Per bank write bursts -system.physmem.perBankWrBursts::8 65746 # Per bank write bursts -system.physmem.perBankWrBursts::9 72323 # Per bank write bursts -system.physmem.perBankWrBursts::10 65450 # Per bank write bursts -system.physmem.perBankWrBursts::11 68291 # Per bank write bursts -system.physmem.perBankWrBursts::12 65769 # Per bank write bursts -system.physmem.perBankWrBursts::13 69040 # Per bank write bursts -system.physmem.perBankWrBursts::14 66651 # Per bank write bursts -system.physmem.perBankWrBursts::15 67496 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 220616 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 87562 # Per bank write bursts +system.physmem.perBankRdBursts::1 88840 # Per bank write bursts +system.physmem.perBankRdBursts::2 82797 # Per bank write bursts +system.physmem.perBankRdBursts::3 92927 # Per bank write bursts +system.physmem.perBankRdBursts::4 90148 # Per bank write bursts +system.physmem.perBankRdBursts::5 93986 # Per bank write bursts +system.physmem.perBankRdBursts::6 87799 # Per bank write bursts +system.physmem.perBankRdBursts::7 94269 # Per bank write bursts +system.physmem.perBankRdBursts::8 90753 # Per bank write bursts +system.physmem.perBankRdBursts::9 132105 # Per bank write bursts +system.physmem.perBankRdBursts::10 81290 # Per bank write bursts +system.physmem.perBankRdBursts::11 92144 # Per bank write bursts +system.physmem.perBankRdBursts::12 81361 # Per bank write bursts +system.physmem.perBankRdBursts::13 87555 # Per bank write bursts +system.physmem.perBankRdBursts::14 92182 # Per bank write bursts +system.physmem.perBankRdBursts::15 91062 # Per bank write bursts +system.physmem.perBankWrBursts::0 71771 # Per bank write bursts +system.physmem.perBankWrBursts::1 74672 # Per bank write bursts +system.physmem.perBankWrBursts::2 72652 # Per bank write bursts +system.physmem.perBankWrBursts::3 78055 # Per bank write bursts +system.physmem.perBankWrBursts::4 74620 # Per bank write bursts +system.physmem.perBankWrBursts::5 78875 # Per bank write bursts +system.physmem.perBankWrBursts::6 73591 # Per bank write bursts +system.physmem.perBankWrBursts::7 76891 # Per bank write bursts +system.physmem.perBankWrBursts::8 77107 # Per bank write bursts +system.physmem.perBankWrBursts::9 78277 # Per bank write bursts +system.physmem.perBankWrBursts::10 71128 # Per bank write bursts +system.physmem.perBankWrBursts::11 78119 # Per bank write bursts +system.physmem.perBankWrBursts::12 70456 # Per bank write bursts +system.physmem.perBankWrBursts::13 74533 # Per bank write bursts +system.physmem.perBankWrBursts::14 76600 # Per bank write bursts +system.physmem.perBankWrBursts::15 76752 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 47456676566000 # Total gap between requests +system.physmem.numWrRetry 39 # Number of times write queue was full causing retry +system.physmem.totGap 47474697259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1310690 # Read request sizes (log2) +system.physmem.readPktSize::6 1424050 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1107684 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1123748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 74620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 20472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 14951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 158 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1203792 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1195881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 91231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 23675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 20974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14619 # 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What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,165 +188,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 19352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 71245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 72329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 71228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 69249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 64601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 238 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 850568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.205557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 113.971853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.835447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 513606 60.38% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 167161 19.65% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 54824 6.45% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28166 3.31% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18449 2.17% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11525 1.35% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9338 1.10% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9545 1.12% 95.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37954 4.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 850568 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62842 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.536775 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 323.180031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 62840 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18047 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 76571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 72953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 70532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 940579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.734800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 113.091903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 237.596263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 569137 60.51% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 185879 19.76% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61156 6.50% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 31438 3.34% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21576 2.29% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13250 1.41% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9973 1.06% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9805 1.04% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38365 4.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 940579 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 68336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.464104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 309.922160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 68334 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62842 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.631298 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.120021 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.777595 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 59398 94.52% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1045 1.66% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 473 0.75% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 210 0.33% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 336 0.53% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 469 0.75% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 106 0.17% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 34 0.05% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 31 0.05% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.04% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.06% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 34 0.05% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 449 0.71% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 44 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 47 0.07% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 32 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 68336 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 68336 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.620273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.104093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.841865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64690 94.66% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1540 2.25% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 239 0.35% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 282 0.41% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 82 0.12% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 291 0.43% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 162 0.24% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 86 0.13% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 81 0.12% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 117 0.17% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 30 0.04% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 46 0.07% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 391 0.57% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 42 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.06% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 142 0.21% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62842 # Writes before turning the bus around for reads -system.physmem.totQLat 31787428314 # Total ticks spent queuing -system.physmem.totMemAccLat 57164147064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6767125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23486.66 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 68336 # Writes before turning the bus around for reads +system.physmem.totQLat 37142962355 # Total ticks spent queuing +system.physmem.totMemAccLat 64645087355 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7333900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25322.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42236.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44072.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.28 # Average write queue length when enqueuing -system.physmem.readRowHits 1086313 # Number of row buffer hits during reads -system.physmem.writeRowHits 524528 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.34 # Row buffer hit rate for writes -system.physmem.avgGap 19258662.67 # Average gap between requests -system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3335290560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1819851000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5311160400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3675585600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1204726391325 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27417225862500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31735733267865 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.730691 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45610216470982 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584682580000 # Time in different power states +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing +system.physmem.readRowHits 1168360 # Number of row buffer hits during reads +system.physmem.writeRowHits 561939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 46.67 # Row buffer hit rate for writes +system.physmem.avgGap 17756571.38 # Average gap between requests +system.physmem.pageHitRate 64.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3585949920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1956619500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5602958400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3895302960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1230768339570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27405197149500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31751822762730 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.815694 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45589938065590 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585284480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 261780130518 # Time in different power states +system.physmem_0.memoryStateTime::ACT 299474968160 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3095003520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1688742000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5245507800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3504163680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1191482148060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27428843611500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31733498303040 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683596 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45629577337540 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584682580000 # Time in different power states +system.physmem_1.actEnergy 3524827320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1923268875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5837886600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3907258560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1224297828675 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27410873036250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31751180549160 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.802167 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45599398366763 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585284480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242414504460 # Time in different power states +system.physmem_1.memoryStateTime::ACT 290016828237 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -410,71 +407,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 105954 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 105954 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10115 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80576 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 105928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.169927 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 55.305347 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 105927 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 105928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 87482 96.43% 96.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2786 3.07% 99.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 233 0.26% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 145 0.16% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 15 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 6 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 19 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 9139568088 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.172115 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -1573058396 -17.21% -17.21% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 10712626484 117.21% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 9139568088 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80577 88.85% 88.85% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10115 11.15% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90692 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105954 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 101051 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 101051 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8300 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 78014 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 101044 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 101044 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 101044 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 86321 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84871 98.32% 98.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 161 0.19% 98.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1103 1.28% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 57 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 86321 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1368339312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.519630 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2079369704 151.96% 151.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -711030392 -51.96% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1368339312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 78015 90.38% 90.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8300 9.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 86315 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101051 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105954 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90692 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101051 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 86315 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90692 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 196646 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 86315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 187366 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80457124 # DTB read hits -system.cpu0.dtb.read_misses 79863 # DTB read misses -system.cpu0.dtb.write_hits 72637408 # DTB write hits -system.cpu0.dtb.write_misses 26091 # DTB write misses +system.cpu0.dtb.read_hits 83039604 # DTB read hits +system.cpu0.dtb.read_misses 74585 # DTB read misses +system.cpu0.dtb.write_hits 76137695 # DTB write hits +system.cpu0.dtb.write_misses 26466 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34410 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37690 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3731 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4076 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8741 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80536987 # DTB read accesses -system.cpu0.dtb.write_accesses 72663499 # DTB write accesses +system.cpu0.dtb.perms_faults 10173 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83114189 # DTB read accesses +system.cpu0.dtb.write_accesses 76164161 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 153094532 # DTB hits -system.cpu0.dtb.misses 105954 # DTB misses -system.cpu0.dtb.accesses 153200486 # DTB accesses +system.cpu0.dtb.hits 159177299 # DTB hits +system.cpu0.dtb.misses 101051 # DTB misses +system.cpu0.dtb.accesses 159278350 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,240 +496,238 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53482 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53482 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 578 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47523 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 53482 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53482 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53482 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 48101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 45094 93.75% 93.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2542 5.28% 99.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 133 0.28% 99.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 277 0.58% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 5 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 6 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 18 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 2 0.00% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 48101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 47523 98.80% 98.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 578 1.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48101 # Table walker page sizes translated +system.cpu0.itb.walker.walks 61250 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61250 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 499 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55525 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 61250 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61250 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61250 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 56024 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 54387 97.08% 97.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.07% 97.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1384 2.47% 99.62% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 41 0.07% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 72 0.13% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 22 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 55 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 56024 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1978837204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1978837204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1978837204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55525 99.11% 99.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 499 0.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56024 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53482 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53482 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61250 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61250 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48101 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48101 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 101583 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 428491503 # ITB inst hits -system.cpu0.itb.inst_misses 53482 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56024 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56024 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117274 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 441205116 # ITB inst hits +system.cpu0.itb.inst_misses 61250 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24315 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26202 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 428544985 # ITB inst accesses -system.cpu0.itb.hits 428491503 # DTB hits -system.cpu0.itb.misses 53482 # DTB misses -system.cpu0.itb.accesses 428544985 # DTB accesses -system.cpu0.numCycles 94913359253 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 441266366 # ITB inst accesses +system.cpu0.itb.hits 441205116 # DTB hits +system.cpu0.itb.misses 61250 # DTB misses +system.cpu0.itb.accesses 441266366 # DTB accesses +system.cpu0.numCycles 94949400739 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 428232691 # Number of instructions committed -system.cpu0.committedOps 502476550 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 461534262 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 406829 # Number of float alu accesses -system.cpu0.num_func_calls 25466680 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64818437 # number of instructions that are conditional controls -system.cpu0.num_int_insts 461534262 # number of integer instructions -system.cpu0.num_fp_insts 406829 # number of float instructions -system.cpu0.num_int_register_reads 668961319 # number of times the integer registers were read -system.cpu0.num_int_register_writes 366250009 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 674435 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 305880 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 111832425 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 111484776 # number of times the CC registers were written -system.cpu0.num_mem_refs 153083738 # number of memory refs -system.cpu0.num_load_insts 80450777 # Number of load instructions -system.cpu0.num_store_insts 72632961 # Number of store instructions -system.cpu0.num_idle_cycles 93826651579.898026 # Number of idle cycles -system.cpu0.num_busy_cycles 1086707673.101977 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011449 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988551 # Percentage of idle cycles -system.cpu0.Branches 95423987 # Number of branches fetched +system.cpu0.committedInsts 440958495 # Number of instructions committed +system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 531836 # Number of float alu accesses +system.cpu0.num_func_calls 26928397 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 66358328 # number of instructions that are conditional controls +system.cpu0.num_int_insts 478066113 # number of integer instructions +system.cpu0.num_fp_insts 531836 # number of float instructions +system.cpu0.num_int_register_reads 691558601 # number of times the integer registers were read +system.cpu0.num_int_register_writes 378884875 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 853461 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 460304 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113354931 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113143261 # number of times the CC registers were written +system.cpu0.num_mem_refs 159167445 # number of memory refs +system.cpu0.num_load_insts 83034076 # Number of load instructions +system.cpu0.num_store_insts 76133369 # Number of store instructions +system.cpu0.num_idle_cycles 93735186324.296036 # Number of idle cycles +system.cpu0.num_busy_cycles 1214214414.703974 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012788 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987212 # Percentage of idle cycles +system.cpu0.Branches 98314010 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 348470598 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 1120076 0.22% 69.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 60052 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 44021 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::MemRead 80450777 16.00% 85.55% # Class of executed instruction -system.cpu0.op_class::MemWrite 72632961 14.45% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 359396375 69.13% 69.13% # Class of executed instruction +system.cpu0.op_class::IntMult 1169846 0.23% 69.36% # Class of executed instruction +system.cpu0.op_class::IntDiv 59621 0.01% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 75402 0.01% 69.38% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction +system.cpu0.op_class::MemRead 83034076 15.97% 85.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 502778486 # Class of executed instruction +system.cpu0.op_class::total 519868732 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15090 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5233253 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5233765 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.202863 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3987157000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.798924 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.939060 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.939060 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 7168 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5565465 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5565977 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.554484 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 6293402000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.695844 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983781 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983781 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 429 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 311404737 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 311404737 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 74943991 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 74943991 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68564818 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68564818 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 176894 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 176894 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135340 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 135340 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1719391 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1719391 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1677698 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1677698 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 143508809 # 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number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188945 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 188945 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4119923 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4119923 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4721512 # number of overall misses -system.cpu0.dcache.overall_misses::total 4721512 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41012776500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41012776500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24489617000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24489617000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46337666000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 46337666000 # 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number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 77784150 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77784150 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 69844582 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 69844582 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 778483 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 778483 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894112 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 894112 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1868280 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1868280 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1866643 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1866643 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 147628732 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 147628732 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 148407215 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 148407215 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036513 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036513 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018323 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772771 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772771 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.848632 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.848632 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101222 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101222 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027907 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027907 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031815 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1898641 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897041 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1897041 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153604701 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153604701 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154429826 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154429826 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037538 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037538 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018700 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018700 # 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average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15898.936339 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13873.181621 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,157 +736,157 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3560219 # number of writebacks -system.cpu0.dcache.writebacks::total 3560219 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30162 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 30162 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21215 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21215 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39917 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39917 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 51377 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 51377 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 51377 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 51377 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2809997 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2809997 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1258549 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1258549 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595949 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 595949 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 758772 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 758772 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188945 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 188945 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4068546 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4068546 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4664495 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4664495 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 26231 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 51684 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36991828000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36991828000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22707525500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22707525500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12844611500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12844611500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45578894000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45578894000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1445565000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1445565000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3885534000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3885534000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2787000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2787000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 59699353500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 59699353500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 72543965000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 72543965000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4455810500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4455810500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4073355500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4073355500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8529166000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8529166000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036126 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765526 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765526 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.848632 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.848632 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058327 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058327 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101222 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101222 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027559 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027559 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031430 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031430 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3771246 # number of writebacks +system.cpu0.dcache.writebacks::total 3771246 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 38597 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 38597 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21414 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21414 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46766 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46766 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 60011 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 60011 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 60011 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 60011 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2975645 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2975645 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1349413 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1349413 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 629920 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 629920 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 782263 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 782263 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121291 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121291 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197269 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 197269 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4325058 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4325058 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4954978 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4954978 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17296 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35915 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46589316500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46589316500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30941514500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30941514500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17872150500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17872150500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64919038500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64919038500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795061500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795061500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4668993000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4668993000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77530831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 77530831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 95402981500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 95402981500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2879350000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2879350000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3091479000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3091479000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5970829000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5970829000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037057 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037057 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763424 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763424 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.861665 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.861665 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063883 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063883 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028157 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028157 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032086 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032086 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4666970 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.880807 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 423824020 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4667482 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 90.803568 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42558943000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.880807 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999767 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999767 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 5319178 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.824621 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 435885421 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5319690 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 81.938124 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 59948153000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.824621 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999657 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999657 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 861650489 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 861650489 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 423824020 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 423824020 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 423824020 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 423824020 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 423824020 # number of overall hits -system.cpu0.icache.overall_hits::total 423824020 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4667483 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4667483 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4667483 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4667483 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4667483 # number of overall misses -system.cpu0.icache.overall_misses::total 4667483 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48694088500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 48694088500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 48694088500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 48694088500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 48694088500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 48694088500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 428491503 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 428491503 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 428491503 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 428491503 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 428491503 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 428491503 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010893 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010893 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010893 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010893 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010893 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010893 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10432.622572 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10432.622572 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 887729927 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 887729927 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 435885421 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 435885421 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 435885421 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 435885421 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 435885421 # number of overall hits +system.cpu0.icache.overall_hits::total 435885421 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5319695 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5319695 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5319695 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5319695 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5319695 # number of overall misses +system.cpu0.icache.overall_misses::total 5319695 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 59521353000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 59521353000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 59521353000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 59521353000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 59521353000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 59521353000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 441205116 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 441205116 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 441205116 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 441205116 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 441205116 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 441205116 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012057 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012057 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012057 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012057 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012057 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012057 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11188.865715 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11188.865715 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -905,252 +895,252 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4667483 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4667483 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4667483 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4667483 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4667483 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4667483 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5319695 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5319695 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5319695 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5319695 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5319695 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5319695 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 46360347000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 46360347000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 46360347000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 46360347000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 46360347000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 46360347000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010893 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010893 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010893 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.622572 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 56861505500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 56861505500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 56861505500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 56861505500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 56861505500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 56861505500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5953877000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 5953877000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012057 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012057 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012057 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7039817 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7039817 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7344223 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7344239 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 925071 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2212798 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.904175 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 16304400 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2228972 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.314762 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 38965596000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7022.512638 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.899316 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.792978 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3705.081021 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4185.062005 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1103.556217 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.428620 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003833 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226140 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.255436 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.067356 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985163 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1459 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 603 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 957 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4495 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089050 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 335472623 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 335472623 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224520 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122258 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 346778 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3560218 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3560218 # 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average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223348 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 548810 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8811478 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 25453 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 6868539 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 8637410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 769123 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 445989 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 473125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1446257 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1069406 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4667483 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5564741 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 864337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 757609 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14087759 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16981197 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 288818 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 540500 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 31898274 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 298891412 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 527370978 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1032672 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1867144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 829162206 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9613339 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30204161 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.324614 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.468231 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 22509328 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11536373 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 848 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 485130 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 485124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 537841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9675681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18620 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18619 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 5107009 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 8757288 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 798537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 405076 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363715 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 481157 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 40 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1220841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1155337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5319695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4658319 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 788798 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 781028 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16044388 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17944373 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 336960 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 515556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34841277 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 340632980 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 559762054 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1230712 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1770072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 903395818 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5410368 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27976627 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.025738 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.158355 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 20399459 67.54% 67.54% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 9804702 32.46% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 27256564 97.43% 97.43% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 720057 2.57% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30204161 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14006094999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 27976627 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 15196832497 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 188261483 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 183439903 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7044349500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 8022667500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7482254107 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7935130422 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 159734000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 183121000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 307107000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 294297000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1399,68 +1395,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 101352 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 101352 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8872 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77968 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 101349 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.078935 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 25.129292 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 101348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 101349 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 86843 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 85298 98.22% 98.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1315 1.51% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 45 0.05% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 84 0.10% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 70 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 111674 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 111674 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10360 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85053 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 111653 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.241821 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 61.696123 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 111651 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 111653 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 95434 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 94629 99.16% 99.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 150 0.16% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 551 0.58% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 86843 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -857364308 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -0.833676 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1572128036 183.37% 183.37% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 714763728 -83.37% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -857364308 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 77968 89.78% 89.78% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8872 10.22% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 86840 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 95434 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 10744163364 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.061708 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -663005280 -6.17% -6.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 11407168644 106.17% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 10744163364 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85053 89.14% 89.14% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10360 10.86% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 95413 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 111674 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101352 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86840 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 111674 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95413 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86840 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 188192 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95413 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 207087 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82714274 # DTB read hits -system.cpu1.dtb.read_misses 74721 # DTB read misses -system.cpu1.dtb.write_hits 75460503 # DTB write hits -system.cpu1.dtb.write_misses 26631 # DTB write misses +system.cpu1.dtb.read_hits 82869257 # DTB read hits +system.cpu1.dtb.read_misses 83659 # DTB read misses +system.cpu1.dtb.write_hits 74681159 # DTB write hits +system.cpu1.dtb.write_misses 28015 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 38549 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37721 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4418 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4459 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10567 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 82788995 # DTB read accesses -system.cpu1.dtb.write_accesses 75487134 # DTB write accesses +system.cpu1.dtb.perms_faults 10437 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82952916 # DTB read accesses +system.cpu1.dtb.write_accesses 74709174 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 158174777 # DTB hits -system.cpu1.dtb.misses 101352 # DTB misses -system.cpu1.dtb.accesses 158276129 # DTB accesses +system.cpu1.dtb.hits 157550416 # DTB hits +system.cpu1.dtb.misses 111674 # DTB misses +system.cpu1.dtb.accesses 157662090 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1490,242 +1487,235 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60693 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60693 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 593 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54830 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60693 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60693 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60693 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55423 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 49924 90.08% 90.08% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3716 6.70% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 553 1.00% 97.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 965 1.74% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.06% 99.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 86 0.16% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 15 0.03% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 45 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 26 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55423 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1656015036 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1656015036 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1656015036 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54830 98.93% 98.93% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 593 1.07% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55423 # Table walker page sizes translated +system.cpu1.itb.walker.walks 54727 # Table walker walks requested +system.cpu1.itb.walker.walksLong 54727 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 669 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48424 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 54727 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 54727 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 54727 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49093 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 48315 98.42% 98.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 33 0.07% 98.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 627 1.28% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 24 0.05% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49093 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1309982220 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1309982220 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1309982220 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 48424 98.64% 98.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 669 1.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49093 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60693 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60693 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54727 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54727 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55423 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55423 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 116116 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 437193188 # ITB inst hits -system.cpu1.itb.inst_misses 60693 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49093 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49093 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 103820 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441006552 # ITB inst hits +system.cpu1.itb.inst_misses 54727 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 27130 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26047 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 437253881 # ITB inst accesses -system.cpu1.itb.hits 437193188 # DTB hits -system.cpu1.itb.misses 60693 # DTB misses -system.cpu1.itb.accesses 437253881 # DTB accesses -system.cpu1.numCycles 94913359253 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441061279 # ITB inst accesses +system.cpu1.itb.hits 441006552 # DTB hits +system.cpu1.itb.misses 54727 # DTB misses +system.cpu1.itb.accesses 441061279 # DTB accesses +system.cpu1.numCycles 94949400719 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 436909780 # Number of instructions committed -system.cpu1.committedOps 515262081 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474007520 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 488695 # Number of float alu accesses -system.cpu1.num_func_calls 26553696 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66234119 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474007520 # number of integer instructions -system.cpu1.num_fp_insts 488695 # number of float instructions -system.cpu1.num_int_register_reads 687449190 # number of times the integer registers were read -system.cpu1.num_int_register_writes 375811208 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 781283 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 430208 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 112572477 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 112287439 # number of times the CC registers were written -system.cpu1.num_mem_refs 158166235 # number of memory refs -system.cpu1.num_load_insts 82712263 # Number of load instructions -system.cpu1.num_store_insts 75453972 # Number of store instructions -system.cpu1.num_idle_cycles 93876093406.586029 # Number of idle cycles -system.cpu1.num_busy_cycles 1037265846.413978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010929 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989071 # Percentage of idle cycles -system.cpu1.Branches 97493416 # Number of branches fetched +system.cpu1.committedInsts 440696565 # Number of instructions committed +system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 365483 # Number of float alu accesses +system.cpu1.num_func_calls 25816030 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67531060 # number of instructions that are conditional controls +system.cpu1.num_int_insts 474820793 # number of integer instructions +system.cpu1.num_fp_insts 365483 # number of float instructions +system.cpu1.num_int_register_reads 694878928 # number of times the integer registers were read +system.cpu1.num_int_register_writes 377300064 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 605102 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 276864 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 116712375 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 116303175 # number of times the CC registers were written +system.cpu1.num_mem_refs 157542729 # number of memory refs +system.cpu1.num_load_insts 82867724 # Number of load instructions +system.cpu1.num_store_insts 74675005 # Number of store instructions +system.cpu1.num_idle_cycles 93871458813.181076 # Number of idle cycles +system.cpu1.num_busy_cycles 1077941905.818921 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011353 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988647 # Percentage of idle cycles +system.cpu1.Branches 98303933 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 356171607 69.09% 69.09% # Class of executed instruction -system.cpu1.op_class::IntMult 1079497 0.21% 69.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 59940 0.01% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 68277 0.01% 69.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.32% # Class of executed instruction -system.cpu1.op_class::MemRead 82712263 16.04% 85.36% # Class of executed instruction -system.cpu1.op_class::MemWrite 75453972 14.64% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 359137164 69.35% 69.35% # Class of executed instruction +system.cpu1.op_class::IntMult 1056908 0.20% 69.56% # Class of executed instruction +system.cpu1.op_class::IntDiv 59454 0.01% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 36204 0.01% 69.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu1.op_class::MemRead 82867724 16.00% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 515545598 # Class of executed instruction +system.cpu1.op_class::total 517832459 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 7070 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5176711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5177218 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.515202 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8391490917000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.282743 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893130 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.893130 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 321544722 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 321544722 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 77092949 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 77092949 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71608224 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71608224 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188155 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188155 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 187532 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 187532 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684198 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1684198 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1657450 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1657450 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 148701173 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 148701173 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 148889328 # number of overall hits -system.cpu1.dcache.overall_hits::total 148889328 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2950342 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2950342 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1305907 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1305907 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 613815 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 613815 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 479868 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 479868 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172330 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 172330 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 197330 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 197330 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4256249 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4256249 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4870064 # number of overall misses -system.cpu1.dcache.overall_misses::total 4870064 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42135771000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 42135771000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22153910000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 22153910000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 15218762000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 15218762000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2580362000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2580362000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4225919000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4225919000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2953000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2953000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 64289681000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 64289681000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 64289681000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 64289681000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80043291 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80043291 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72914131 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72914131 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 801970 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 801970 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 667400 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 667400 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1856528 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1856528 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1854780 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1854780 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 152957422 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 152957422 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 153759392 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 153759392 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036859 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036859 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017910 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765384 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765384 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.719011 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.719011 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092824 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092824 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106390 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106390 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027826 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031673 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031673 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 14490 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5147651 # number of replacements +system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5148159 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.564853 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8409197794000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 420.489425 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.821268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.821268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 443 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 320234661 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 320234661 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 77182580 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 77182580 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 70763723 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 70763723 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181716 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 181716 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197136 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 197136 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768276 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1768276 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1725683 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1725683 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 147946303 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 147946303 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148128019 # number of overall hits +system.cpu1.dcache.overall_hits::total 148128019 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2911211 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2911211 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1304261 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1304261 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 646630 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 646630 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 461157 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 461157 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158092 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158092 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198973 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 198973 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4215472 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4215472 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4862102 # number of overall misses +system.cpu1.dcache.overall_misses::total 4862102 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46228111000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46228111000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27445585000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 27445585000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22477695000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 22477695000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2400515000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2400515000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4867748500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4867748500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2101500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2101500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 73673696000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 73673696000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 73673696000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 73673696000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 80093791 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 80093791 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72067984 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72067984 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828346 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 828346 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 658293 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 658293 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1926368 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1926368 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1924656 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1924656 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 152161775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 152161775 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152990121 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152990121 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036348 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036348 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018098 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018098 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780628 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780628 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.700535 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.700535 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082067 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082067 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103381 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103381 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027704 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027704 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031780 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031780 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1734,158 +1724,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3350646 # number of writebacks -system.cpu1.dcache.writebacks::total 3350646 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17552 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 17552 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 421 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 421 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45020 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45020 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 17973 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 17973 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 17973 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 17973 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932790 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2932790 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1305486 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1305486 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 613815 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 613815 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 479868 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 479868 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 197330 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 197330 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4238276 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4238276 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4852091 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4852091 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 12503 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25653 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38342874000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38342874000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20834838000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20834838000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12333914500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12333914500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14738894000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14738894000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690256500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690256500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4028650000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4028650000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2892000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2892000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59177712000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 59177712000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71511626500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 71511626500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2070021000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2070021000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2282534000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2282534000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4352555000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4352555000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036640 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036640 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017904 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017904 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765384 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765384 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.719011 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.719011 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068574 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068574 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106390 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106390 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027709 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027709 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031556 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031556 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3396408 # number of writebacks +system.cpu1.dcache.writebacks::total 3396408 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16912 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16912 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 462 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 462 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41725 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41725 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 17374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 17374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 17374 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 17374 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2894299 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2894299 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1303799 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1303799 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 646630 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 646630 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 461157 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 461157 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198973 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 198973 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4198098 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4198098 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4844728 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4844728 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20770 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40100 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41851387000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41851387000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26109084500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26109084500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14515592000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14515592000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 22016538000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 22016538000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587242500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587242500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4668803500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4668803500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2073500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2073500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67960471500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 67960471500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 82476063500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 82476063500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3614060000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3614060000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3361466500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3361466500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975526500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6975526500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780628 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780628 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.700535 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.700535 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103381 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103381 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027590 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031667 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031667 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5209177 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.272261 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 431983494 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5209689 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 82.919248 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8391463454000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.272261 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969282 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969282 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4679241 # number of replacements +system.cpu1.icache.tags.tagsinuse 495.918258 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436326798 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4679753 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 93.237143 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8409166313000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.918258 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968590 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968590 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 440 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 879596070 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 879596070 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 431983494 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 431983494 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 431983494 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 431983494 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 431983494 # number of overall hits -system.cpu1.icache.overall_hits::total 431983494 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5209694 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5209694 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5209694 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5209694 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5209694 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 437193188 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 437193188 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011916 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011916 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011916 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011916 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011916 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011916 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10363.248014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10363.248014 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 886692857 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 886692857 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436326798 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436326798 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436326798 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436326798 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436326798 # number of overall hits +system.cpu1.icache.overall_hits::total 436326798 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4679754 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4679754 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4679754 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4679754 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4679754 # number of overall misses +system.cpu1.icache.overall_misses::total 4679754 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52951180000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 52951180000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 52951180000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 52951180000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 52951180000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 52951180000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 441006552 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 441006552 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 441006552 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 441006552 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 441006552 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 441006552 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010612 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.010612 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010612 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.010612 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010612 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.010612 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11314.949461 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11314.949461 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1894,251 +1884,255 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5209694 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5209694 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5209694 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5209694 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5209694 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5209694 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4679754 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4679754 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4679754 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4679754 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4679754 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4679754 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51384504000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 51384504000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51384504000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 51384504000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51384504000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 51384504000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9739500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9739500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9739500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9739500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011916 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011916 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011916 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9863.248014 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50611303500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 50611303500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50611303500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 50611303500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50611303500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 50611303500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14521500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14521500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14521500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 14521500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010612 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.010612 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.010612 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7168932 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7168932 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7337880 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7337888 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 888356 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2018400 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13471.145620 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17736817 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2034046 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.719968 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9876432033500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5731.708202 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.533292 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 100.125774 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3516.826700 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3218.371115 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 832.580536 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.349836 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004366 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006111 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.214650 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196434 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050817 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.822213 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1631 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2682 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6101 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5119 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099548 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 350300692 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 350300692 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 208719 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141350 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 350069 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3350644 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3350644 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65287 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 65287 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34260 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 34260 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 879078 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 879078 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4680645 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4680645 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3650143 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8680857 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10729 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9390 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20119 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 125786 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 125786 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 163059 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 163059 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # 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number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3427875000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2800500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2800500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9388085997 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9388085997 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15677246500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15677246500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28842829500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28842829500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 12565083500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 12565083500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 428489500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 413569000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15677246500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 38230915497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 54750220497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 428489500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 413569000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15677246500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 38230915497 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 54750220497 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 219448 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150740 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 370188 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3350644 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3350644 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 191073 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 191073 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 197319 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 197319 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # 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number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150740 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5209694 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4790060 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10369942 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 219448 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150740 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5209694 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4790060 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10369942 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.062293 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.054348 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.658314 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.658314 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826373 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826373 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 899040 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2034185 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13437.783654 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 16644740 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2049737 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.120427 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9820320151000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 6510.894270 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.649917 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 96.755911 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2809.884427 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3040.183540 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 908.415590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.397393 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004373 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005906 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2599 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5864 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5395 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 332457854 # 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mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.162488 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.190132 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.190132 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109572 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247950 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247950 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578186 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578186 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167683 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224856 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.237575 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 557907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9467454 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 13150 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 6658964 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 9333240 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 797552 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 400874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 357340 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 454404 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1816504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1125838 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5209694 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5632852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 585123 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 478395 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15628224 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16712375 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332083 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 514043 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33186725 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333420856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 527793939 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205920 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1755584 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 864176299 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 9912470 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 31389750 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.322129 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.467292 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 20369965 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10454543 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 477453 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 477447 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 508237 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 8929000 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 19330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 19330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4444983 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 8042862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 852297 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 366971 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 446864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1185291 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1125998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4679754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4554667 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 467005 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 459760 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14038440 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16622497 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 296146 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 569967 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 31527050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 299504632 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 528992733 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1062248 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1967800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 831527413 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5090691 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25485456 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.028305 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.165844 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 21278201 67.79% 67.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 10111549 32.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 24764094 97.17% 97.17% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 721356 2.83% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 31389750 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14234291993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 25485456 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 13733891999 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 190598993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 167318993 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7814651000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7019739500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7637949368 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7617418010 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 181343000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 163365000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 294595499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 323992499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40360 # Transaction distribution -system.iobus.trans_dist::ReadResp 40360 # Transaction distribution -system.iobus.trans_dist::WriteReq 136623 # Transaction distribution -system.iobus.trans_dist::WriteResp 136623 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40317 # Transaction distribution +system.iobus.trans_dist::ReadResp 40317 # Transaction distribution +system.iobus.trans_dist::WriteReq 136619 # Transaction distribution +system.iobus.trans_dist::WriteResp 136619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47666 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2377,13 +2383,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353872 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2398,13 +2404,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36194000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2432,71 +2438,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569839842 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565735913 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92712000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115629 # number of replacements -system.iocache.tags.tagsinuse 11.301329 # Cycle average of tags in use +system.iocache.tags.replacements 115577 # number of replacements +system.iocache.tags.tagsinuse 11.281807 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115645 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9148621285000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.403816 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.897512 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462739 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243595 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706333 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9206321837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.831702 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.450105 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239481 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465632 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705113 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041045 # Number of tag accesses -system.iocache.tags.data_accesses 1041045 # Number of data accesses +system.iocache.tags.tag_accesses 1040721 # Number of tag accesses +system.iocache.tags.data_accesses 1040721 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses -system.iocache.demand_misses::total 8944 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses +system.iocache.demand_misses::total 8908 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8904 # number of overall misses -system.iocache.overall_misses::total 8944 # number of overall misses +system.iocache.overall_misses::realview.ide 8868 # number of overall misses +system.iocache.overall_misses::total 8908 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1656855076 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1662050076 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1668103306 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1673298306 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12632251766 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12632251766 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13929903607 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13929903607 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1656855076 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1662419076 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1668103306 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1673667306 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1656855076 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1662419076 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1668103306 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1673667306 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2511,54 +2517,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185890.848451 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187905.480741 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185869.753578 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187883.622137 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185869.753578 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32671 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187883.622137 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33272 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3491 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.525073 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.530793 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1211655076 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1215000076 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224703306 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1228048306 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7295851766 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7295851766 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8593503607 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8593503607 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1211655076 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1215219076 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1224703306 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1228267306 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1211655076 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1215219076 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1224703306 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1228267306 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2573,612 +2579,612 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1275038 # number of replacements -system.l2c.tags.tagsinuse 63572.316878 # Cycle average of tags in use -system.l2c.tags.total_refs 4892898 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1334308 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.666993 # Average number of references to valid blocks. +system.l2c.tags.replacements 1400633 # number of replacements +system.l2c.tags.tagsinuse 63705.794368 # Cycle average of tags in use +system.l2c.tags.total_refs 5028924 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1460176 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.444053 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18943.726739 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 66.506889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 88.082899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3576.388780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7769.332592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6333.160086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 237.192415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 333.040502 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3918.032205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9111.997525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.289058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.118551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.096636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003619 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059784 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.139038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.201338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.970037 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10413 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 223 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48634 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 260 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 499 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1442 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42029 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.158890 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003403 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.742096 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 61952788 # Number of tag accesses -system.l2c.tags.data_accesses 61952788 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2200570 # number of Writeback hits -system.l2c.Writeback_hits::total 2200570 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 25702 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 29550 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 55252 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5421 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6216 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11637 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145994 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 170556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 316550 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4694 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3455 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 439478 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 496055 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 255928 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5679 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4922 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 484783 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 520043 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283587 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2498624 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 439478 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 642049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 255928 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5679 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4922 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 484783 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 690599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 283587 # number of demand (read+write) hits -system.l2c.demand_hits::total 2815174 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4694 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits -system.l2c.overall_hits::cpu0.inst 439478 # number of overall hits -system.l2c.overall_hits::cpu0.data 642049 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 255928 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5679 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4922 # number of overall hits -system.l2c.overall_hits::cpu1.inst 484783 # number of overall hits -system.l2c.overall_hits::cpu1.data 690599 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 283587 # number of overall hits -system.l2c.overall_hits::total 2815174 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 41366 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 45574 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86940 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9742 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11031 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 20773 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 487808 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 146598 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 634406 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 811 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 757 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 42366 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 114531 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2560 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 44266 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 108963 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 676832 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 811 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 42366 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 602339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2399 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2560 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 44266 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 255561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) misses -system.l2c.demand_misses::total 1311238 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 811 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 757 # number of overall misses -system.l2c.overall_misses::cpu0.inst 42366 # number of overall misses -system.l2c.overall_misses::cpu0.data 602339 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 184040 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2399 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2560 # number of overall misses -system.l2c.overall_misses::cpu1.inst 44266 # number of overall misses -system.l2c.overall_misses::cpu1.data 255561 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 176139 # number of overall misses -system.l2c.overall_misses::total 1311238 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 225555000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 234735000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 460290000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48941500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54202000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 103143500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 40891325500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 11909713000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 52801038500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 72944500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 67955000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3540995500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 10155548500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 211977500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 227366000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3707983000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 9711131500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 68879114830 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 72944500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 67955000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3540995500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 51046874000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 211977500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 227366000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3707983000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 21620844500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 121680153330 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 72944500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 67955000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3540995500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 51046874000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 211977500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 227366000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3707983000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 21620844500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of overall miss cycles -system.l2c.overall_miss_latency::total 121680153330 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2200570 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2200570 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 67068 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 75124 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 142192 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15163 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 17247 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 32410 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 633802 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 317154 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 950956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5505 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4212 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 481844 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 610586 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 439968 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8078 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7482 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 529049 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 629006 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 459726 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3175456 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5505 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4212 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 481844 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1244388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 439968 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8078 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9239.567296 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.288824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002554 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067572 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.178797 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173037 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003515 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.039901 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.071185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140985 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.972073 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10769 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48480 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 409 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1411 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41942 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.164322 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.739746 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 64230359 # Number of tag accesses +system.l2c.tags.data_accesses 64230359 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2314762 # number of Writeback hits +system.l2c.Writeback_hits::total 2314762 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 28623 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 30874 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59497 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6079 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5789 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.317697 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.317697 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.615086 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.572832 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.594259 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.634456 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.634302 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.634381 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.748823 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534986 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.678415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.230236 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162772 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235093 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.334105 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.334105 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 81967 # Transaction distribution -system.membus.trans_dist::ReadResp 767450 # Transaction distribution -system.membus.trans_dist::WriteReq 38603 # Transaction distribution -system.membus.trans_dist::WriteResp 38603 # Transaction distribution -system.membus.trans_dist::Writeback 1107684 # Transaction distribution -system.membus.trans_dist::CleanEvict 202348 # Transaction distribution -system.membus.trans_dist::UpgradeReq 391044 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 311393 # Transaction distribution -system.membus.trans_dist::UpgradeResp 114065 # Transaction distribution -system.membus.trans_dist::ReadExReq 650749 # Transaction distribution -system.membus.trans_dist::ReadExResp 628057 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 685483 # Transaction distribution +system.membus.trans_dist::ReadReq 81299 # Transaction distribution +system.membus.trans_dist::ReadResp 868698 # Transaction distribution +system.membus.trans_dist::WriteReq 37949 # Transaction distribution +system.membus.trans_dist::WriteResp 37949 # Transaction distribution +system.membus.trans_dist::Writeback 1203792 # Transaction distribution +system.membus.trans_dist::CleanEvict 220565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 376258 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321655 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113911 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 660250 # Transaction distribution +system.membus.trans_dist::ReadExResp 639853 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 787399 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122600 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4735959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4885501 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5228030 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5071225 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5218123 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341689 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341689 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5559812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155707 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147705452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 147915041 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7264128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 155179169 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613936 # Total snoops (count) -system.membus.snoop_fanout::samples 3578377 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 161136300 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 161340623 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7239232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7239232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 168579855 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 607627 # Total snoops (count) +system.membus.snoop_fanout::samples 3798608 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3578377 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3798608 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3578377 # Request fanout histogram -system.membus.reqLayer0.occupancy 101272500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3798608 # Request fanout histogram +system.membus.reqLayer0.occupancy 101169498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 23177500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20972999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7575699049 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8203462570 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7326536131 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7924808506 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229377455 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 230064369 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3232,46 +3238,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 81969 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4074898 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38603 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3308322 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1226405 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 439947 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 323030 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 762977 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1086983 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1086983 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4000171 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 10304168 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5242935 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1823032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 155703 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 143721 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11982 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 81301 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4203748 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37949 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37949 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3518592 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1268318 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 429580 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333523 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 763103 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 68 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1086913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1086913 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4129694 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7169000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6360157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13529157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 219530790 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185908027 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 405438817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3048406 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11669556 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.129089 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.335298 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7476293 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6448186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13924479 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230559242 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190965829 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 421525071 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3161630 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12055300 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.328437 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.471756 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10163148 87.09% 87.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1506408 12.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8107870 67.26% 67.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3935448 32.64% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11982 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11669556 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7690985653 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12055300 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7945670452 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2550000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2561165 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4244781764 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4404072117 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3859650249 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3899520231 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index f9e8bd96f..5ecc0e3a9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.832459 # Number of seconds simulated -sim_ticks 51832458543500 # Number of ticks simulated -final_tick 51832458543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811426 # Number of seconds simulated +sim_ticks 51811426272500 # Number of ticks simulated +final_tick 51811426272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536175 # Simulator instruction rate (inst/s) -host_op_rate 630049 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31477440084 # Simulator tick rate (ticks/s) -host_mem_usage 712068 # Number of bytes of host memory used -host_seconds 1646.65 # Real time elapsed on the host -sim_insts 882895003 # Number of instructions simulated -sim_ops 1037473525 # Number of ops (including micro ops) simulated +host_inst_rate 673469 # Simulator instruction rate (inst/s) +host_op_rate 791455 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42067688868 # Simulator tick rate (ticks/s) +host_mem_usage 720644 # Number of bytes of host memory used +host_seconds 1231.62 # Real time elapsed on the host +sim_insts 829457901 # Number of instructions simulated +sim_ops 974772546 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 255168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 250176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5270964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 81048392 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 390144 # Number of bytes read from this memory -system.physmem.bytes_read::total 87214844 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5270964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5270964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75813760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 136896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 149440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4672052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65294216 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 405248 # Number of bytes read from this memory +system.physmem.bytes_read::total 70657852 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4672052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4672052 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61426304 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 75834340 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122766 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1266394 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6096 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1403152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1184590 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61446884 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 113408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1020235 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6332 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1144449 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 959786 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1187163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1563661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1682630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1462670 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 962359 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 2884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 90174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1260228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1363750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1185574 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1463067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1462670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1564058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3145697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1403152 # Number of read requests accepted -system.physmem.writeReqs 1187163 # Number of write requests accepted -system.physmem.readBursts 1403152 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1187163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 89743360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 58368 # Total number of bytes read from write queue -system.physmem.bytesWritten 75832768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 87214844 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75834340 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 912 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 142509 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84707 # Per bank write bursts -system.physmem.perBankRdBursts::1 87220 # Per bank write bursts -system.physmem.perBankRdBursts::2 81347 # Per bank write bursts -system.physmem.perBankRdBursts::3 82774 # Per bank write bursts -system.physmem.perBankRdBursts::4 86841 # Per bank write bursts -system.physmem.perBankRdBursts::5 98270 # Per bank write bursts -system.physmem.perBankRdBursts::6 81495 # Per bank write bursts -system.physmem.perBankRdBursts::7 83122 # Per bank write bursts -system.physmem.perBankRdBursts::8 79285 # Per bank write bursts -system.physmem.perBankRdBursts::9 129613 # Per bank write bursts -system.physmem.perBankRdBursts::10 85444 # Per bank write bursts -system.physmem.perBankRdBursts::11 88159 # Per bank write bursts -system.physmem.perBankRdBursts::12 83519 # Per bank write bursts -system.physmem.perBankRdBursts::13 84779 # Per bank write bursts -system.physmem.perBankRdBursts::14 82284 # Per bank write bursts -system.physmem.perBankRdBursts::15 83381 # Per bank write bursts -system.physmem.perBankWrBursts::0 72521 # Per bank write bursts -system.physmem.perBankWrBursts::1 74576 # Per bank write bursts -system.physmem.perBankWrBursts::2 72526 # Per bank write bursts -system.physmem.perBankWrBursts::3 74694 # Per bank write bursts -system.physmem.perBankWrBursts::4 74615 # Per bank write bursts -system.physmem.perBankWrBursts::5 83452 # Per bank write bursts -system.physmem.perBankWrBursts::6 71356 # Per bank write bursts -system.physmem.perBankWrBursts::7 73404 # Per bank write bursts -system.physmem.perBankWrBursts::8 69434 # Per bank write bursts -system.physmem.perBankWrBursts::9 76014 # Per bank write bursts -system.physmem.perBankWrBursts::10 73389 # Per bank write bursts -system.physmem.perBankWrBursts::11 75855 # Per bank write bursts -system.physmem.perBankWrBursts::12 72723 # Per bank write bursts -system.physmem.perBankWrBursts::13 74909 # Per bank write bursts -system.physmem.perBankWrBursts::14 71861 # Per bank write bursts -system.physmem.perBankWrBursts::15 73558 # Per bank write bursts +system.physmem.bw_write::total 1185972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1185574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 2884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1260625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2549722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1144449 # Number of read requests accepted +system.physmem.writeReqs 962359 # Number of write requests accepted +system.physmem.readBursts 1144449 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 962359 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 73193536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51200 # Total number of bytes read from write queue +system.physmem.bytesWritten 61446016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70657852 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 61446884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 800 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 140011 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69107 # Per bank write bursts +system.physmem.perBankRdBursts::1 74090 # Per bank write bursts +system.physmem.perBankRdBursts::2 73242 # Per bank write bursts +system.physmem.perBankRdBursts::3 69271 # Per bank write bursts +system.physmem.perBankRdBursts::4 67156 # Per bank write bursts +system.physmem.perBankRdBursts::5 73972 # Per bank write bursts +system.physmem.perBankRdBursts::6 66324 # Per bank write bursts +system.physmem.perBankRdBursts::7 66322 # Per bank write bursts +system.physmem.perBankRdBursts::8 69640 # Per bank write bursts +system.physmem.perBankRdBursts::9 111279 # Per bank write bursts +system.physmem.perBankRdBursts::10 69249 # Per bank write bursts +system.physmem.perBankRdBursts::11 69472 # Per bank write bursts +system.physmem.perBankRdBursts::12 65127 # Per bank write bursts +system.physmem.perBankRdBursts::13 68635 # Per bank write bursts +system.physmem.perBankRdBursts::14 67352 # Per bank write bursts +system.physmem.perBankRdBursts::15 63411 # Per bank write bursts +system.physmem.perBankWrBursts::0 57809 # Per bank write bursts +system.physmem.perBankWrBursts::1 62464 # Per bank write bursts +system.physmem.perBankWrBursts::2 62675 # Per bank write bursts +system.physmem.perBankWrBursts::3 60788 # Per bank write bursts +system.physmem.perBankWrBursts::4 58616 # Per bank write bursts +system.physmem.perBankWrBursts::5 63580 # Per bank write bursts +system.physmem.perBankWrBursts::6 58138 # Per bank write bursts +system.physmem.perBankWrBursts::7 59016 # Per bank write bursts +system.physmem.perBankWrBursts::8 60306 # Per bank write bursts +system.physmem.perBankWrBursts::9 62192 # Per bank write bursts +system.physmem.perBankWrBursts::10 60798 # Per bank write bursts +system.physmem.perBankWrBursts::11 61491 # Per bank write bursts +system.physmem.perBankWrBursts::12 56659 # Per bank write bursts +system.physmem.perBankWrBursts::13 60390 # Per bank write bursts +system.physmem.perBankWrBursts::14 59031 # Per bank write bursts +system.physmem.perBankWrBursts::15 56141 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 51832455911500 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times write queue was full causing retry +system.physmem.totGap 51811423590500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1360036 # Read request sizes (log2) +system.physmem.readPktSize::6 1101333 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1184590 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1369724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.writePktSize::6 959786 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1115953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,162 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 68862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 70049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 70008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 69966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 69777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 71661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 71703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 72226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 69733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 69498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 68867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 564142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 293.500232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.709934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.462784 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 227896 40.40% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 137874 24.44% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50148 8.89% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27962 4.96% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20021 3.55% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14110 2.50% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11549 2.05% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10920 1.94% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63662 11.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 564142 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 68197 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.561359 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 299.455370 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 68195 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 13692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 56950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 56683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 57911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 63120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 58684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 58229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 56389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 55725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 55034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 451899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.940982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.093990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.963355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 180364 39.91% 39.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 110273 24.40% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39544 8.75% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23126 5.12% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15873 3.51% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11951 2.64% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9990 2.21% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8720 1.93% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 52058 11.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 451899 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54067 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.152052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.366692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 54065 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 68197 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 68197 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.374474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.924162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.358180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 65696 96.33% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 133 0.20% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 441 0.65% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 195 0.29% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 359 0.53% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 498 0.73% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 123 0.18% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.04% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 34 0.05% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.04% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.06% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 22 0.03% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 434 0.64% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 41 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 54067 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54067 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.757486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.129918 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.530147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51801 95.81% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 269 0.50% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 70 0.13% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 325 0.60% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 45 0.08% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 331 0.61% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 216 0.40% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 22 0.04% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 68 0.13% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 136 0.25% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 36 0.07% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 464 0.86% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 28 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.05% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 146 0.27% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 68197 # Writes before turning the bus around for reads -system.physmem.totQLat 16916842552 # Total ticks spent queuing -system.physmem.totMemAccLat 43208842552 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7011200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12064.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 21 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54067 # Writes before turning the bus around for reads +system.physmem.totQLat 14370740504 # Total ticks spent queuing +system.physmem.totMemAccLat 35814159254 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5718245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12565.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30814.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31315.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing -system.physmem.readRowHits 1132918 # Number of row buffer hits during reads -system.physmem.writeRowHits 890066 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes -system.physmem.avgGap 20010097.58 # Average gap between requests -system.physmem.pageHitRate 78.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2149066080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1172605500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5349013800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3869493120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308122393760 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951995045500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34658101361520 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.656420 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49827055945457 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730799460000 # Time in different power states +system.physmem.avgWrQLen 27.25 # Average write queue length when enqueuing +system.physmem.readRowHits 921781 # Number of row buffer hits during reads +system.physmem.writeRowHits 730062 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.04 # Row buffer hit rate for writes +system.physmem.avgGap 24592380.32 # Average gap between requests +system.physmem.pageHitRate 78.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1754978400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 957577500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4363975200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3130397280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1298615760765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947715800500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34640608612845 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.590209 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49820119093739 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730097200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 274602731543 # Time in different power states +system.physmem_0.memoryStateTime::ACT 261204441261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2115847440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1154480250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5588419200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3808574640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1306419956235 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29953488411750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34658019433275 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.654839 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49829529145116 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730799460000 # Time in different power states +system.physmem_1.actEnergy 1661378040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 906505875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4556448000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3091011840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1293042304755 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29952604797000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34639932568710 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.577161 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49828251258491 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730097200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 272122791134 # Time in different power states +system.physmem_1.memoryStateTime::ACT 253077157009 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -368,76 +366,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 207675 # Table walker walks requested -system.cpu.dtb.walker.walksLong 207675 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15981 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 160171 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 207653 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.182998 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 62.840123 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 207651 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 184770 # Table walker walks requested +system.cpu.dtb.walker.walksLong 184770 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12350 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144149 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 184753 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.216505 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.872440 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 184751 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 207653 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 176174 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 111064 63.04% 63.04% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 63199 35.87% 98.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 999 0.57% 99.48% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 662 0.38% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 15 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 88 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 50 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 52 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 13 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 176174 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -781821628 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.029012 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.167839 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -759139796 97.10% 97.10% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -22681832 2.90% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -781821628 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 160172 90.93% 90.93% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15981 9.07% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 176153 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 207675 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 184753 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 156516 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24678.339595 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20707.909662 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17878.729982 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 155309 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1041 0.67% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 36 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 39 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 156516 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -8954848740 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.174586 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1563388704 -17.46% -17.46% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -10518237444 117.46% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -8954848740 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 144150 92.11% 92.11% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12350 7.89% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 156500 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 184770 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 207675 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 176153 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 184770 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156500 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 176153 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 383828 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156500 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 341270 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 165829611 # DTB read hits -system.cpu.dtb.read_misses 153241 # DTB read misses -system.cpu.dtb.write_hits 150793131 # DTB write hits -system.cpu.dtb.write_misses 54434 # DTB write misses +system.cpu.dtb.read_hits 156218154 # DTB read hits +system.cpu.dtb.read_misses 137197 # DTB read misses +system.cpu.dtb.write_hits 141774250 # DTB write hits +system.cpu.dtb.write_misses 47573 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 75015 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 70344 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8164 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7209 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19719 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 165982852 # DTB read accesses -system.cpu.dtb.write_accesses 150847565 # DTB write accesses +system.cpu.dtb.perms_faults 18555 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 156355351 # DTB read accesses +system.cpu.dtb.write_accesses 141821823 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316622742 # DTB hits -system.cpu.dtb.misses 207675 # DTB misses -system.cpu.dtb.accesses 316830417 # DTB accesses +system.cpu.dtb.hits 297992404 # DTB hits +system.cpu.dtb.misses 184770 # DTB misses +system.cpu.dtb.accesses 298177174 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,233 +458,235 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 122431 # Table walker walks requested -system.cpu.itb.walker.walksLong 122431 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1128 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 110257 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 122431 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 122431 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 122431 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 111385 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28118.386677 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109197 98.04% 98.04% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1895 1.70% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 129 0.12% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 51 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 111385 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -887504296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -887504296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -887504296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 110257 98.99% 98.99% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1128 1.01% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 111385 # Table walker page sizes translated +system.cpu.itb.walker.walks 119016 # Table walker walks requested +system.cpu.itb.walker.walksLong 119016 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107588 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 119016 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 119016 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 119016 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108698 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28702.878618 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24805.101383 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21517.827982 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107219 98.64% 98.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1293 1.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 35 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 66 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 38 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108698 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1449242704 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1449242704 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1449242704 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 107588 98.98% 98.98% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1110 1.02% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108698 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122431 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 122431 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119016 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 119016 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111385 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 111385 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 233816 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 883439249 # ITB inst hits -system.cpu.itb.inst_misses 122431 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108698 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108698 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 227714 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829969192 # ITB inst hits +system.cpu.itb.inst_misses 119016 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53485 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 50385 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 883561680 # ITB inst accesses -system.cpu.itb.hits 883439249 # DTB hits -system.cpu.itb.misses 122431 # DTB misses -system.cpu.itb.accesses 883561680 # DTB accesses -system.cpu.numCycles 103664917087 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 830088208 # ITB inst accesses +system.cpu.itb.hits 829969192 # DTB hits +system.cpu.itb.misses 119016 # DTB misses +system.cpu.itb.accesses 830088208 # DTB accesses +system.cpu.numCycles 103622852545 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 882895003 # Number of instructions committed -system.cpu.committedOps 1037473525 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 952709754 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 896425 # Number of float alu accesses -system.cpu.num_func_calls 52419949 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 134729686 # number of instructions that are conditional controls -system.cpu.num_int_insts 952709754 # number of integer instructions -system.cpu.num_fp_insts 896425 # number of float instructions -system.cpu.num_int_register_reads 1388360502 # number of times the integer registers were read -system.cpu.num_int_register_writes 755717952 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1444442 # number of times the floating registers were read -system.cpu.num_fp_register_writes 761348 # number of times the floating registers were written -system.cpu.num_cc_register_reads 231664947 # number of times the CC registers were read -system.cpu.num_cc_register_writes 231068644 # number of times the CC registers were written -system.cpu.num_mem_refs 316605789 # number of memory refs -system.cpu.num_load_insts 165822487 # Number of load instructions -system.cpu.num_store_insts 150783302 # Number of store instructions -system.cpu.num_idle_cycles 100487560505.254059 # Number of idle cycles -system.cpu.num_busy_cycles 3177356581.745939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030650 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969350 # Percentage of idle cycles -system.cpu.Branches 197184546 # Number of branches fetched +system.cpu.committedInsts 829457901 # Number of instructions committed +system.cpu.committedOps 974772546 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 896189211 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 901491 # Number of float alu accesses +system.cpu.num_func_calls 49868985 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 125722281 # number of instructions that are conditional controls +system.cpu.num_int_insts 896189211 # number of integer instructions +system.cpu.num_fp_insts 901491 # number of float instructions +system.cpu.num_int_register_reads 1296374406 # number of times the integer registers were read +system.cpu.num_int_register_writes 710181687 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1455753 # number of times the floating registers were read +system.cpu.num_fp_register_writes 759888 # number of times the floating registers were written +system.cpu.num_cc_register_reads 214623564 # number of times the CC registers were read +system.cpu.num_cc_register_writes 214015228 # number of times the CC registers were written +system.cpu.num_mem_refs 297970911 # number of memory refs +system.cpu.num_load_insts 156208355 # Number of load instructions +system.cpu.num_store_insts 141762556 # Number of store instructions +system.cpu.num_idle_cycles 100538268245.312057 # Number of idle cycles +system.cpu.num_busy_cycles 3084584299.687941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029767 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970233 # Percentage of idle cycles +system.cpu.Branches 185080610 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 719043510 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2202813 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 97927 0.01% 69.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110813 0.01% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 165822487 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 150783302 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 675027682 69.21% 69.21% # Class of executed instruction +system.cpu.op_class::IntMult 2118642 0.22% 69.43% # Class of executed instruction +system.cpu.op_class::IntDiv 97301 0.01% 69.44% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu.op_class::MemRead 156208355 16.02% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 141762556 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1038060895 # Class of executed instruction +system.cpu.op_class::total 975326961 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 19158 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10067650 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 306351638 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10068162 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.427762 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.966034 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999934 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 18851 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 9274254 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288519025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9274766 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.107957 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942797 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276220350 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276220350 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 154968992 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 154968992 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 143085243 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 143085243 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 390390 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 390390 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335374 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335374 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3613361 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3613361 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5695270000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11526622000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11526622000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014853 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014853 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.764158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.764158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785684 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785684 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058739 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058739 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024169 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024169 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028175 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028175 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18290.325552 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 7273356 # number of writebacks +system.cpu.dcache.writebacks::total 7273356 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23715 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 23715 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21271 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21271 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68399 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 68399 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44986 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44986 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44986 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44986 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4819360 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 4819360 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1949995 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1949995 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1108464 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1108464 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1222439 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1222439 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216177 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 216177 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 6769355 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6769355 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 7877819 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 7877819 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 77027858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 77027858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 64047484500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 64047484500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21144827000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21144827000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72088738500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72088738500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970895000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970895000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141075343000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 141075343000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162220170000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 162220170000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5832027500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5832027500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5823842500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5823842500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11655870000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11655870000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031889 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031889 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014275 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014275 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.748279 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.748279 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786652 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786652 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060501 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060501 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023527 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023527 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027239 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027239 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15983.005731 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15983.005731 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32844.948064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32844.948064 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19075.790463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19075.790463 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 58971.235784 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 58971.235784 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13742.881990 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13742.881990 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81333.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81333.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20840.293204 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20840.293204 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20592.015379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20592.015379 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173046.925998 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173046.925998 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172773.303073 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.303073 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172910.102359 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172910.102359 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13898073 # number of replacements -system.cpu.icache.tags.tagsinuse 511.854844 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 869540659 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13898585 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62.563251 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 43284980500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.854844 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999716 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13424392 # number of replacements +system.cpu.icache.tags.tagsinuse 511.782428 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816544283 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13424904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.823100 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 61690343500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.782428 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 897337839 # Number of tag accesses -system.cpu.icache.tags.data_accesses 897337839 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 869540659 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 869540659 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 869540659 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 869540659 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 869540659 # number of overall hits -system.cpu.icache.overall_hits::total 869540659 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13898590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13898590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13898590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13898590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13898590 # number of overall misses -system.cpu.icache.overall_misses::total 13898590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186400133500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186400133500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186400133500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186400133500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186400133500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186400133500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 883439249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 883439249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 883439249 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 883439249 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 883439249 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 883439249 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015732 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015732 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015732 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015732 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015732 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015732 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13411.441988 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13411.441988 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13411.441988 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13411.441988 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13411.441988 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166777 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166777 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036387 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036387 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392330 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392330 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009514 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.027986 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009514 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.027986 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126699.821189 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70659.111016 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70659.111016 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120988.049380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120988.049380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122155.290102 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122155.290102 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123117.622326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123117.622326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120223.655129 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120223.655129 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160546.925998 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134174.118474 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161273.303073 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161273.303073 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160910.146862 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 142438.101054 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1048560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21674258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8945109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 16396444 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45067 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45068 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2112473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2112473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13898590 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6735107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1336151 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1229487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41779933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30429687 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 620392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 972976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 73802988 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 889682260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062595910 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2036024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2937088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1957251282 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1844105 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 50552964 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.048758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.215362 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 45918929 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23219248 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1752 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 973260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20543031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8233173 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15585132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 41659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 41662 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1908339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1908339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13424909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6152877 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1329103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1222439 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40358865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28042657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 851524 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69854144 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 859366676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 981090094 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1963488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2486024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1844906282 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1578062 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 47683915 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010174 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100353 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 48088105 95.12% 95.12% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2464859 4.88% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 47198764 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 485151 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 50552964 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32307276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 47683915 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 30513690500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1324500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1602380 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20891010000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20180488500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13945928913 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12761129471 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 365889000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 355662000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 605840000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 540771000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40329 # Transaction distribution -system.iobus.trans_dist::ReadResp 40329 # Transaction distribution +system.iobus.trans_dist::ReadReq 40324 # Transaction distribution +system.iobus.trans_dist::ReadResp 40324 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1284,11 +1283,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231016 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1305,11 +1304,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334496 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334496 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492416 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1338,71 +1337,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568778648 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565894582 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147776000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115490 # number of replacements -system.iocache.tags.tagsinuse 10.455215 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.446961 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13165278431000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510021 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945193 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434075 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653451 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183666451000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511449 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935511 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433469 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039929 # Number of tag accesses -system.iocache.tags.data_accesses 1039929 # Number of data accesses +system.iocache.tags.tag_accesses 1039884 # Number of tag accesses +system.iocache.tags.data_accesses 1039884 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8844 # number of demand (read+write) misses -system.iocache.demand_misses::total 8884 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses +system.iocache.demand_misses::total 8879 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8844 # number of overall misses -system.iocache.overall_misses::total 8884 # number of overall misses +system.iocache.overall_misses::realview.ide 8839 # number of overall misses +system.iocache.overall_misses::total 8879 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1566099238 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1571168238 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1643284102 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1648353102 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12612607410 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12612607410 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13826197480 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13826197480 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1566099238 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1571519238 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1643284102 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1648704102 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1566099238 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1571519238 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1643284102 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1648704102 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8844 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8884 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8844 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8884 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1417,54 +1416,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 176913.437451 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185912.897613 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185709.002028 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118246.150623 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129623.841971 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129623.841971 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 176893.205538 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185685.786913 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 176893.205538 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29516 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185685.786913 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32536 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3281 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.996038 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.637441 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8844 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8884 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8844 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8884 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1123899238 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1127118238 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201334102 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1204553102 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279407410 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7279407410 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8492997480 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8492997480 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1123899238 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1127319238 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1201334102 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1204754102 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1123899238 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1127319238 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1201334102 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1204754102 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1479,72 +1478,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135912.897613 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135709.002028 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79623.841971 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79623.841971 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 446450 # Transaction distribution -system.membus.trans_dist::WriteReq 33710 # Transaction distribution -system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::Writeback 1184590 # Transaction distribution -system.membus.trans_dist::CleanEvict 190005 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35851 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35852 # Transaction distribution -system.membus.trans_dist::ReadExReq 993855 # Transaction distribution -system.membus.trans_dist::ReadExResp 993855 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 369619 # Transaction distribution +system.membus.trans_dist::ReadReq 76827 # Transaction distribution +system.membus.trans_dist::ReadResp 384060 # Transaction distribution +system.membus.trans_dist::WriteReq 33708 # Transaction distribution +system.membus.trans_dist::WriteResp 33708 # Transaction distribution +system.membus.trans_dist::Writeback 959786 # Transaction distribution +system.membus.trans_dist::CleanEvict 158940 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33352 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33355 # Transaction distribution +system.membus.trans_dist::ReadExReq 797298 # Transaction distribution +system.membus.trans_dist::ReadExResp 797298 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 307233 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4133679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4263383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340829 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340829 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4604212 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3354625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3484317 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3825690 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155834656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 156004506 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7214528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7214528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 163219034 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3445 # Total snoops (count) -system.membus.snoop_fanout::samples 2994110 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124875168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 125044994 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7229568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 132274562 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3206 # Total snoops (count) +system.membus.snoop_fanout::samples 2476492 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2994110 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2476492 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2994110 # Request fanout histogram -system.membus.reqLayer0.occupancy 107330000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2476492 # Request fanout histogram +system.membus.reqLayer0.occupancy 107338500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5385500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5425000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7724756059 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6302386470 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7445249237 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6068941451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228975298 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228333558 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 25d466362..4162ec223 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 916811 # Simulator instruction rate (inst/s) -host_op_rate 1077403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47593586653 # Simulator tick rate (ticks/s) -host_mem_usage 712068 # Number of bytes of host memory used -host_seconds 1073.91 # Real time elapsed on the host +host_inst_rate 1150787 # Simulator instruction rate (inst/s) +host_op_rate 1352364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59739798990 # Simulator tick rate (ticks/s) +host_mem_usage 722184 # Number of bytes of host memory used +host_seconds 855.56 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -788,9 +788,9 @@ system.iocache.writebacks::total 106631 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 1722562 # number of replacements system.l2c.tags.tagsinuse 65341.862549 # Cycle average of tags in use -system.l2c.tags.total_refs 47050546 # Total number of references to valid blocks. +system.l2c.tags.total_refs 47048799 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1785858 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.346185 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 26.345207 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 37097.979539 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460552 # Average occupied blocks per requestor @@ -821,8 +821,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 4910 # system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426855693 # Number of tag accesses -system.l2c.tags.data_accesses 426855693 # Number of data accesses +system.l2c.tags.tag_accesses 426841717 # Number of tag accesses +system.l2c.tags.data_accesses 426841717 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits @@ -1001,7 +1001,7 @@ system.membus.trans_dist::ReadResp 525866 # Tr system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution system.membus.trans_dist::Writeback 1610322 # Transaction distribution -system.membus.trans_dist::CleanEvict 228928 # Transaction distribution +system.membus.trans_dist::CleanEvict 225569 # Transaction distribution system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution @@ -1013,11 +1013,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5530845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5660037 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6006542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5529617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5658809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6003183 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) @@ -1027,17 +1027,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 220300218 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3922896 # Request fanout histogram +system.membus.snoop_fanout::samples 3921668 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3922896 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3921668 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3922896 # Request fanout histogram +system.membus.snoop_fanout::total 3921668 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1090,12 +1090,18 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 52477792 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26568978 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution system.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution @@ -1105,27 +1111,27 @@ system.toL2Bus.trans_dist::ReadCleanReq 14296158 # Tr system.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42974207 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35074075 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42972629 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35073906 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80535624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80533877 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 2159735666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 116338 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 53337224 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.025483 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.157587 # Request fanout histogram +system.toL2Bus.snoops 1954363 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 55175249 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011169 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105093 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 51978032 97.45% 97.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1359192 2.55% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54558983 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 616266 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 53337224 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 55175249 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 17066f3b8..100a686ad 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,191 +1,191 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.276903 # Number of seconds simulated -sim_ticks 51276903265000 # Number of ticks simulated -final_tick 51276903265000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.357853 # Number of seconds simulated +sim_ticks 51357853367000 # Number of ticks simulated +final_tick 51357853367000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195122 # Simulator instruction rate (inst/s) -host_op_rate 229284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11700811305 # Simulator tick rate (ticks/s) -host_mem_usage 723460 # Number of bytes of host memory used -host_seconds 4382.34 # Real time elapsed on the host -sim_insts 855091424 # Number of instructions simulated -sim_ops 1004800608 # Number of ops (including micro ops) simulated +host_inst_rate 254475 # Simulator instruction rate (inst/s) +host_op_rate 295745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14267482520 # Simulator tick rate (ticks/s) +host_mem_usage 733332 # Number of bytes of host memory used +host_seconds 3599.64 # Real time elapsed on the host +sim_insts 916019679 # Number of instructions simulated +sim_ops 1064576900 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 83904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2486836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43860424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 20800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 20224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 650944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 6302784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 33152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 28032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1597440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 8824832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 59456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1836416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 15839168 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 414400 # Number of bytes read from this memory -system.physmem.bytes_read::total 82215292 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2486836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 650944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1597440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1836416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6571636 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69835456 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 95168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2358260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43599240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 19200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 20160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 451648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5774336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 28864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 24640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1511104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 8165824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 62272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 59136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1907392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 14522560 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 410688 # Number of bytes read from this memory +system.physmem.bytes_read::total 79096764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2358260 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 451648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1511104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1907392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6228404 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67268864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69856036 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1311 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 79264 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 685332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 316 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 98481 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 24960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 137888 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 28694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 247487 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6475 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1325034 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1091179 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67289444 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1487 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 77255 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 681251 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 90224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 23611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 127591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 29803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 226915 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6417 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1276307 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1051076 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1093752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 48498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 855364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 122917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 31153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 172102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 308895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1603359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 48498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 31153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128160 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1361928 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1053649 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 848930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 112433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 29423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 158999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 37139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 282772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1540110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 29423 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 37139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1309807 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1362329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1361928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 48498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 855765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 122917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 31153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 172102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 308895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2965689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 552891 # Number of read requests accepted -system.physmem.writeReqs 477788 # Number of write requests accepted -system.physmem.readBursts 552891 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 477788 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 35353984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue -system.physmem.bytesWritten 30577024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 35385024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 30578432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65706 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 34049 # Per bank write bursts -system.physmem.perBankRdBursts::1 38611 # Per bank write bursts -system.physmem.perBankRdBursts::2 36089 # Per bank write bursts -system.physmem.perBankRdBursts::3 33688 # Per bank write bursts -system.physmem.perBankRdBursts::4 32444 # Per bank write bursts -system.physmem.perBankRdBursts::5 38213 # Per bank write bursts -system.physmem.perBankRdBursts::6 33143 # Per bank write bursts -system.physmem.perBankRdBursts::7 35180 # Per bank write bursts -system.physmem.perBankRdBursts::8 30999 # Per bank write bursts -system.physmem.perBankRdBursts::9 38487 # Per bank write bursts -system.physmem.perBankRdBursts::10 32534 # Per bank write bursts -system.physmem.perBankRdBursts::11 34124 # Per bank write bursts -system.physmem.perBankRdBursts::12 34391 # Per bank write bursts -system.physmem.perBankRdBursts::13 36689 # Per bank write bursts -system.physmem.perBankRdBursts::14 30748 # Per bank write bursts -system.physmem.perBankRdBursts::15 33017 # Per bank write bursts -system.physmem.perBankWrBursts::0 28228 # Per bank write bursts -system.physmem.perBankWrBursts::1 31813 # Per bank write bursts -system.physmem.perBankWrBursts::2 30334 # Per bank write bursts -system.physmem.perBankWrBursts::3 30276 # Per bank write bursts -system.physmem.perBankWrBursts::4 29074 # Per bank write bursts -system.physmem.perBankWrBursts::5 32329 # Per bank write bursts -system.physmem.perBankWrBursts::6 29378 # Per bank write bursts -system.physmem.perBankWrBursts::7 31367 # Per bank write bursts -system.physmem.perBankWrBursts::8 28134 # Per bank write bursts -system.physmem.perBankWrBursts::9 32950 # Per bank write bursts -system.physmem.perBankWrBursts::10 28173 # Per bank write bursts -system.physmem.perBankWrBursts::11 29809 # Per bank write bursts -system.physmem.perBankWrBursts::12 29393 # Per bank write bursts -system.physmem.perBankWrBursts::13 31102 # Per bank write bursts -system.physmem.perBankWrBursts::14 26687 # Per bank write bursts -system.physmem.perBankWrBursts::15 28719 # Per bank write bursts +system.physmem.bw_write::total 1310207 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1309807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 849331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 112433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 29423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 158999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 37139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 282772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2850318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 512711 # Number of read requests accepted +system.physmem.writeReqs 445331 # Number of write requests accepted +system.physmem.readBursts 512711 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 445331 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 32795328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue +system.physmem.bytesWritten 28499456 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 32813504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28501184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 68360 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 31469 # Per bank write bursts +system.physmem.perBankRdBursts::1 33714 # Per bank write bursts +system.physmem.perBankRdBursts::2 32400 # Per bank write bursts +system.physmem.perBankRdBursts::3 32794 # Per bank write bursts +system.physmem.perBankRdBursts::4 31510 # Per bank write bursts +system.physmem.perBankRdBursts::5 36975 # Per bank write bursts +system.physmem.perBankRdBursts::6 32126 # Per bank write bursts +system.physmem.perBankRdBursts::7 32020 # Per bank write bursts +system.physmem.perBankRdBursts::8 29401 # Per bank write bursts +system.physmem.perBankRdBursts::9 33672 # Per bank write bursts +system.physmem.perBankRdBursts::10 31630 # Per bank write bursts +system.physmem.perBankRdBursts::11 33204 # Per bank write bursts +system.physmem.perBankRdBursts::12 32821 # Per bank write bursts +system.physmem.perBankRdBursts::13 30845 # Per bank write bursts +system.physmem.perBankRdBursts::14 28756 # Per bank write bursts +system.physmem.perBankRdBursts::15 29090 # Per bank write bursts +system.physmem.perBankWrBursts::0 26343 # Per bank write bursts +system.physmem.perBankWrBursts::1 28031 # Per bank write bursts +system.physmem.perBankWrBursts::2 27542 # Per bank write bursts +system.physmem.perBankWrBursts::3 28584 # Per bank write bursts +system.physmem.perBankWrBursts::4 28467 # Per bank write bursts +system.physmem.perBankWrBursts::5 30964 # Per bank write bursts +system.physmem.perBankWrBursts::6 28168 # Per bank write bursts +system.physmem.perBankWrBursts::7 28820 # Per bank write bursts +system.physmem.perBankWrBursts::8 26688 # Per bank write bursts +system.physmem.perBankWrBursts::9 29870 # Per bank write bursts +system.physmem.perBankWrBursts::10 27026 # Per bank write bursts +system.physmem.perBankWrBursts::11 28792 # Per bank write bursts +system.physmem.perBankWrBursts::12 28018 # Per bank write bursts +system.physmem.perBankWrBursts::13 26681 # Per bank write bursts +system.physmem.perBankWrBursts::14 25511 # Per bank write bursts +system.physmem.perBankWrBursts::15 25799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 51275902957500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 51356853146000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 552891 # Read request sizes (log2) +system.physmem.readPktSize::6 512711 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 477788 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 390834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 101245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 445331 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 362263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 95120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -198,189 +198,184 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 19132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 26278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 27645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 27593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 28722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 30518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 30394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 29969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 28250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 28349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 27090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.439605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.938897 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.109659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 125716 45.85% 45.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 68438 24.96% 70.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25021 9.12% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12508 4.56% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9258 3.38% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5639 2.06% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4828 1.76% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3908 1.43% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18894 6.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274210 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 26911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.526067 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 11.794562 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 24375 90.58% 90.58% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 2332 8.67% 99.24% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 174 0.65% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 18 0.07% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-191 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-799 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 26911 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 26911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.753558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.172751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.257743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.03% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 13 0.05% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 46 0.17% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 25176 93.55% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 431 1.60% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 320 1.19% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 165 0.61% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 117 0.43% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 198 0.74% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 59 0.22% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.07% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.08% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.06% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 22 0.08% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 188 0.70% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 14 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 18 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.05% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 18279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 21711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 24541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 25822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 26638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 26611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 27355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 29988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 27429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 27483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 29137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 26033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 24834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 259364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.325041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.327680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.441771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 119855 46.21% 46.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 64854 25.01% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23816 9.18% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11723 4.52% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8762 3.38% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5465 2.11% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4497 1.73% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3594 1.39% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16798 6.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 259364 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 24808 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.654708 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 12.973882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 22443 90.47% 90.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 2162 8.71% 99.18% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 162 0.65% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 16 0.06% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 10 0.04% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-191 3 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 3 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::544-575 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::608-639 2 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 24808 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 24808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.950016 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.268943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.650949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 27 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 16 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 10 0.04% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 35 0.14% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 23050 92.91% 93.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 468 1.89% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 156 0.63% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 288 1.16% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 65 0.26% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 175 0.71% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 65 0.26% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 18 0.07% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 53 0.21% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 60 0.24% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 15 0.06% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.05% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 191 0.77% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 12 0.05% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.05% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 46 0.19% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 26911 # Writes before turning the bus around for reads -system.physmem.totQLat 11450608424 # Total ticks spent queuing -system.physmem.totMemAccLat 21808220924 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2762030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20728.61 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 24808 # Writes before turning the bus around for reads +system.physmem.totQLat 10667534010 # Total ticks spent queuing +system.physmem.totMemAccLat 20275540260 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2562135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20817.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39478.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39567.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.42 # Average write queue length when enqueuing -system.physmem.readRowHits 422970 # Number of row buffer hits during reads -system.physmem.writeRowHits 332991 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.69 # Row buffer hit rate for writes -system.physmem.avgGap 49749633.94 # Average gap between requests -system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1067305680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 580820625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2194982400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1573337520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1179597405240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30106177853250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34601718457755 # Total energy per rank (pJ) -system.physmem_0.averagePower 666.680244 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48870107005920 # Time in different power states -system.physmem_0.memoryStateTime::REF 1692498340000 # Time in different power states +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 389460 # Number of row buffer hits during reads +system.physmem.writeRowHits 308905 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.37 # Row buffer hit rate for writes +system.physmem.avgGap 53606056.05 # Average gap between requests +system.physmem.pageHitRate 72.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1011233160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 550085250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051392200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1470435120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1181011387995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30447742538250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34948731846855 # Total energy per rank (pJ) +system.physmem_0.averagePower 666.034408 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48934758214122 # Time in different power states +system.physmem_0.memoryStateTime::REF 1694731480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 123346652830 # Time in different power states +system.physmem_0.memoryStateTime::ACT 123339078628 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1005699240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 547226625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2113714200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1522586160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1176042513600 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29757652392000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34249410884865 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.428862 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48875263841452 # Time in different power states -system.physmem_1.memoryStateTime::REF 1692498340000 # Time in different power states +system.physmem_1.actEnergy 949558680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 516544875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1945468200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1415134800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177770817440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29706179302500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34203671601375 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.620773 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48939527598915 # Time in different power states +system.physmem_1.memoryStateTime::REF 1694731480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 118168635298 # Time in different power states +system.physmem_1.memoryStateTime::ACT 118558226835 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -440,47 +435,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 90619 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 90619 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 90619 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 90619 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 90619 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.505623 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -198113446712 -50.56% -50.56% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 589933953000 150.56% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 391820506288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 66457 84.78% 84.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11934 15.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90619 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 89680 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 89680 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 89680 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 89680 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 89680 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.578670 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -221375171178 -57.87% -57.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 603933894750 157.87% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 382558723572 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 65458 84.89% 84.89% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11653 15.11% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 77111 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 89680 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90619 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 89680 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77111 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 169010 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77111 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 166791 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64357240 # DTB read hits -system.cpu0.dtb.read_misses 68494 # DTB read misses -system.cpu0.dtb.write_hits 58282336 # DTB write hits -system.cpu0.dtb.write_misses 22125 # DTB write misses -system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 70228403 # DTB read hits +system.cpu0.dtb.read_misses 67978 # DTB read misses +system.cpu0.dtb.write_hits 59109334 # DTB write hits +system.cpu0.dtb.write_misses 21702 # DTB write misses +system.cpu0.dtb.flush_tlb 1217 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42200 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40606 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2748 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2912 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7647 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64425734 # DTB read accesses -system.cpu0.dtb.write_accesses 58304461 # DTB write accesses +system.cpu0.dtb.perms_faults 7556 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 70296381 # DTB read accesses +system.cpu0.dtb.write_accesses 59131036 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 122639576 # DTB hits -system.cpu0.dtb.misses 90619 # DTB misses -system.cpu0.dtb.accesses 122730195 # DTB accesses +system.cpu0.dtb.hits 129337737 # DTB hits +system.cpu0.dtb.misses 89680 # DTB misses +system.cpu0.dtb.accesses 129427417 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -510,695 +505,697 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53743 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53743 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53743 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53743 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53743 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.505732 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -198156351712 -50.57% -50.57% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 589976858000 150.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 391820506288 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46842 94.98% 94.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2476 5.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 49318 # Table walker page sizes translated +system.cpu0.itb.walker.walks 52945 # Table walker walks requested +system.cpu0.itb.walker.walksLong 52945 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 52945 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 52945 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 52945 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.578782 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -221418129178 -57.88% -57.88% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 603976852750 157.88% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 382558723572 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46017 94.83% 94.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2511 5.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 48528 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53743 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52945 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52945 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49318 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49318 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 103061 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 342266306 # ITB inst hits -system.cpu0.itb.inst_misses 53743 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48528 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48528 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 101473 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 364915659 # ITB inst hits +system.cpu0.itb.inst_misses 52945 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1217 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29888 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28384 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 342320049 # ITB inst accesses -system.cpu0.itb.hits 342266306 # DTB hits -system.cpu0.itb.misses 53743 # DTB misses -system.cpu0.itb.accesses 342320049 # DTB accesses -system.cpu0.numCycles 413032183 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 364968604 # ITB inst accesses +system.cpu0.itb.hits 364915659 # DTB hits +system.cpu0.itb.misses 52945 # DTB misses +system.cpu0.itb.accesses 364968604 # DTB accesses +system.cpu0.numCycles 436289438 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 342117440 # Number of instructions committed -system.cpu0.committedOps 402438329 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 369654139 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 360090 # Number of float alu accesses -system.cpu0.num_func_calls 20604842 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52004192 # number of instructions that are conditional controls -system.cpu0.num_int_insts 369654139 # number of integer instructions -system.cpu0.num_fp_insts 360090 # number of float instructions -system.cpu0.num_int_register_reads 540778381 # number of times the integer registers were read -system.cpu0.num_int_register_writes 293614649 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 575012 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 316800 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89609832 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89403726 # number of times the CC registers were written -system.cpu0.num_mem_refs 122714331 # number of memory refs -system.cpu0.num_load_insts 64415463 # Number of load instructions -system.cpu0.num_store_insts 58298868 # Number of store instructions -system.cpu0.num_idle_cycles 403076556.915137 # Number of idle cycles -system.cpu0.num_busy_cycles 9955626.084863 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024104 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975896 # Percentage of idle cycles -system.cpu0.Branches 76323262 # Number of branches fetched +system.cpu0.committedInsts 364774665 # Number of instructions committed +system.cpu0.committedOps 425727567 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 388492427 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 355504 # Number of float alu accesses +system.cpu0.num_func_calls 20838410 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 59397900 # number of instructions that are conditional controls +system.cpu0.num_int_insts 388492427 # number of integer instructions +system.cpu0.num_fp_insts 355504 # number of float instructions +system.cpu0.num_int_register_reads 563346906 # number of times the integer registers were read +system.cpu0.num_int_register_writes 307286794 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 569525 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 310180 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 98350677 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 98136627 # number of times the CC registers were written +system.cpu0.num_mem_refs 129410259 # number of memory refs +system.cpu0.num_load_insts 70285041 # Number of load instructions +system.cpu0.num_store_insts 59125218 # Number of store instructions +system.cpu0.num_idle_cycles 425895176.866435 # Number of idle cycles +system.cpu0.num_busy_cycles 10394261.133565 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023824 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976176 # Percentage of idle cycles +system.cpu0.Branches 85458268 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 278992555 69.28% 69.28% # Class of executed instruction -system.cpu0.op_class::IntMult 883395 0.22% 69.50% # Class of executed instruction -system.cpu0.op_class::IntDiv 42520 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 46836 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 64415463 16.00% 85.52% # Class of executed instruction -system.cpu0.op_class::MemWrite 58298868 14.48% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 295583613 69.39% 69.39% # Class of executed instruction +system.cpu0.op_class::IntMult 876793 0.21% 69.60% # Class of executed instruction +system.cpu0.op_class::IntDiv 40797 0.01% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 48752 0.01% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::MemRead 70285041 16.50% 86.12% # Class of executed instruction +system.cpu0.op_class::MemWrite 59125218 13.88% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 402679638 # Class of executed instruction +system.cpu0.op_class::total 425960214 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 19432 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9760108 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 295125268 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9760620 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.236324 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 19395 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9657229 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 312286694 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9657741 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 32.335377 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.144128 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.012482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 7.237282 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.605825 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.967078 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.011743 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.014135 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.836076 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.401672 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.084857 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.677113 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970383 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008597 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009931 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.011088 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1250683612 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1250683612 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60097226 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 19336059 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26622949 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 45749144 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 151805378 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55100568 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17719150 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23754745 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 38783251 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135357714 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 162930 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47086 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80309 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113101 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403426 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133083 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44114 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 53448 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 99458 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 330103 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1446448 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 433739 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 576979 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 973119 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3430285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1540849 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 470550 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 624581 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1118875 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3754855 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 115197794 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 37055209 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 50377694 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 84532395 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 287163092 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 115360724 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 37102295 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 50458003 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 84645496 # number of overall hits -system.cpu0.dcache.overall_hits::total 287566518 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2087825 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 630392 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 947372 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3467801 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7133390 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 834937 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 250601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 634589 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3517753 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5237880 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 509202 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 138531 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 204192 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 336844 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1188769 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 666802 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 108292 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 153513 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 298278 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1226885 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 95086 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37006 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47829 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 182134 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 362055 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2922762 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 880993 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1581961 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 6985554 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 12371270 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3431964 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1019524 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1786153 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 7322398 # number of overall misses -system.cpu0.dcache.overall_misses::total 13560039 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9653717000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15011038000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 51609854500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 76274609500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6907191500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17274882500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96691175707 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 120873249707 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2640856500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4379642000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10567870242 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 17588368742 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 538982000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 669036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2261145500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3469163500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 130000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 16560908500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 32285920500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 148301030207 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 197147859207 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 16560908500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 32285920500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 148301030207 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 197147859207 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 62185051 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 19966451 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 27570321 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 49216945 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 158938768 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 55935505 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 17969751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 24389334 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 42301004 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 140595594 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 672132 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 185617 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 284501 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 449945 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3792340 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1540849 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 470550 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 624581 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1118878 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3754858 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 118120556 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 37936202 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 51959655 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 91517949 # 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miss rate for StoreCondReq accesses +system.cpu0.dcache.tags.tag_accesses 1318802850 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1318802850 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 66114410 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 21101681 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 29024806 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 53770773 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 170011670 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55935115 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17375745 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 22998325 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 38100786 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134409971 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159119 # 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number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3389483 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1521761 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 483660 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 621712 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1080020 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3707153 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 122049525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 38477426 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 52023131 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 91871559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 304421641 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 122208644 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 38524357 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 52099680 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 91984857 # number of overall hits +system.cpu0.dcache.overall_hits::total 304817538 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2010257 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 646801 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 1011664 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3491455 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7160177 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 846558 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 254963 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 597011 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 3430913 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5129445 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 467844 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 148258 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 206108 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 346909 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1169119 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 678893 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 111170 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 148628 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu3.data 287890 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1226581 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 90398 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38264 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47866 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 181381 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 357909 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2856815 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 901764 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1608675 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 6922368 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 12289622 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3324659 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1050022 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1814783 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 7269277 # number of overall misses +system.cpu0.dcache.overall_misses::total 13458741 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10543203000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17532852000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 61974045500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 90050100500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9377516000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22074229500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 115413229590 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 146864975090 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3621904000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 5139897000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 11619226144 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 20381027144 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 545937500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 715302000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2408045500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3669285000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 124500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 124500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 19920719000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 39607081500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 177387275090 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 236915075590 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 19920719000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 39607081500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 177387275090 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 236915075590 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 68124667 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 21748482 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 30036470 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 57262228 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177171847 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 56781673 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 17630708 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 23595336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 41531699 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 139539416 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 626963 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 195189 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 282657 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 460207 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1565016 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 804426 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 155557 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 209541 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 385920 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1555444 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1522475 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 483889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 621973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1119055 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3747392 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1521762 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 483660 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 621712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1080024 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3707158 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 124906340 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 39379190 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 53631806 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 98793927 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 316711263 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 125533303 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 39574379 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 53914463 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 99254134 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 318276279 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029509 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.029740 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.033681 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.060973 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040414 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014909 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014461 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025302 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082610 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.036760 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.746207 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.759561 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.729181 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.753811 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747033 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843947 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714658 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.709303 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.745984 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788573 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059376 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079076 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.162084 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095509 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024744 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023223 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030446 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076330 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026744 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034189 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.079619 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045031 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15313.831711 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15844.924697 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14882.588274 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.617325 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27562.505736 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27222.158752 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27486.630161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23076.750461 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24386.441288 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 28529.453532 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35429.600044 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14335.792468 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14564.719235 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.082544 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12414.735854 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9581.868777 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 43333.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 43333.333333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18798.002368 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20408.796740 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21229.673438 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15935.943457 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16243.765228 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18075.674648 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20253.068763 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14538.885855 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 12171442 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 9970 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 893773 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 243 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.618046 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 41.028807 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.022872 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.022900 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.029995 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.070069 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.038804 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026484 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026533 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.033660 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.073239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.042286 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.536023 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17330.706638 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17750.206003 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12576.518779 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36779.909242 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36974.577520 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33639.217780 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28631.747702 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32579.868670 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34582.292704 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 40359.950481 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16616.128200 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14267.653669 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14943.843229 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13276.172808 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10252.005398 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 31125 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24900 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22090.834187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24620.934309 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25625.230425 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19277.653584 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18971.715831 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21824.692815 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24402.327094 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17603.063733 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14691366 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 44925 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 885387 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 409 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.593158 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 109.841076 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7547308 # number of writebacks -system.cpu0.dcache.writebacks::total 7547308 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3607 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 105383 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1896936 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2005926 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2163 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 278391 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2919937 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3200491 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 20 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2253 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2273 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8701 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10746 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 111791 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 131238 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 5770 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 383774 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4816873 # 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number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4916699 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5947 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4621 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4770 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15338 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5383 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4193 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4437 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14013 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 11330 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8814 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2410482500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3025654000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 5045013000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10481149500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2532564500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4225854500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10181517242 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 16939936242 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 374149000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 474867500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 928593000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1777609500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 127000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 127000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15532280000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21649405000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 41077993973 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 78259678973 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 17942762500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24675059000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 46123006973 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 88740828473 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1021104000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 786468000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 830220000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2637792000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943050500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 717793000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 802384000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2463227500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1964154500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1504261000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1632604000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5101019500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031392 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030540 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031917 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013825 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014605 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014132 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008553 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745136 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.717351 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.738337 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.423697 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.710549 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.741652 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.744275 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358262 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060128 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059351 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060890 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035791 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 7514109 # number of writebacks +system.cpu0.dcache.writebacks::total 7514109 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2771 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 136848 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1941751 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2081370 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4940 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 264787 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2848230 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3117957 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 24 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2140 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 2164 # 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number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 690720 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 111170 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 148604 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 285750 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 545524 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29958 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 37474 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 69665 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137097 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 894053 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 1207040 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 2132387 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4233480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1041921 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 1410394 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 2471885 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4924200 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 7255 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6503 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6617 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20375 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6735 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6076 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6212 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19023 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13990 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12579 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12829 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39398 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9707145500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13944833000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26713310000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50365288500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 8910990000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 11750433500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21146117703 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 41807541203 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2949361000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4314932000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6455391500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13719684500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3510734000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4990147500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 11205262644 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 19706144144 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 391502000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 499495000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 988057000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1879054000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 120500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 120500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 18618135500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25695266500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47859427703 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 92172829703 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 21567496500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 30010198500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54314819203 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 105892514203 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354782000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1199064500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1204617000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3758463500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1285148500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1145187000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1151844463 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3582179963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2639930500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2344251500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2356461463 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7340643463 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029613 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.027063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017320 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014181 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014080 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014030 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008348 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.757563 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.719437 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.737707 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.441350 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714658 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.709188 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.740438 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.350719 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061911 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060250 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.062253 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036585 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023071 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023060 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023697 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026587 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026841 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027193 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016328 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14277.502652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14787.180118 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15118.454800 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14853.283235 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26498.987675 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25824.855839 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28987.083773 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27536.284170 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17428.114381 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14825.314694 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15186.170837 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15536.651655 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23386.441288 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 27531.252240 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34394.112801 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30368.649257 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13218.477301 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12805.530836 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13200.929730 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13096.562318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 42333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 42333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17746.654281 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18068.469279 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18941.464408 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18448.373449 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17703.185293 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17596.460464 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18442.622462 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18048.863368 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171700.689423 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170194.330232 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174050.314465 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171977.572043 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 175190.507152 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171188.409254 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180839.305837 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175781.595661 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173358.737864 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170667.233946 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177322.037580 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173793.720827 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.022704 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.022506 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.021584 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.013367 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026328 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026160 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.024905 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.015471 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15072.505163 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15940.304018 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17237.685390 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16413.383683 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35640.681057 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35369.008560 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36290.946712 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35888.457850 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19945.904455 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 21218.820382 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19014.519968 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19862.874247 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31579.868670 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33580.169444 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 39213.517564 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36123.331226 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13068.362374 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13329.108182 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14182.975669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13706.018367 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 30125 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30125 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20824.420364 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21287.833460 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22444.062782 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21772.355061 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20699.742591 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21277.882989 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 21973.036449 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21504.511231 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186737.698139 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184386.360141 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 182048.813662 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184464.466258 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190816.406830 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188477.123107 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 185422.482775 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188307.835935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 188701.250893 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 186362.310200 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 183682.396368 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186320.205670 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15787116 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.974790 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 559161583 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15787628 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.417707 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10320304500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.137124 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.371284 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 26.901455 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 10.564927 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.920190 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006585 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.052542 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.020635 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 15725711 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971450 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 600346119 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48525407500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58117116880 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 128052814880 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017853 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017853 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017853 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12467.557789 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 362383 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 362383 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 362383 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 362383 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 362383 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 362383 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1673429 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3871552 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4622807 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10167788 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1673429 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3871552 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4622807 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10167788 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1673429 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3871552 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4622807 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10167788 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 20937483000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49389922000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59308516343 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 129635921343 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 20937483000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49389922000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59308516343 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 129635921343 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 20937483000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49389922000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59308516343 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 129635921343 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014485 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052037 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.075118 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016495 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014485 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052037 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.075118 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016495 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014485 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052037 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.075118 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016495 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12511.724728 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12757.137706 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12829.546278 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12749.668005 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12511.724728 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12757.137706 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12829.546278 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12749.668005 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12511.724728 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12757.137706 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12829.546278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12749.668005 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1229,68 +1226,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 32157 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 32157 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4670 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23647 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32152 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 32152 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32152 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 28322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24465.680390 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21462.893478 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 12624.124225 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18193 64.24% 64.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9967 35.19% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 97 0.34% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 42 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 3 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 28322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -3003382012 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.339073 # Table walker pending requests distribution +system.cpu1.dtb.walker.walks 31829 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31829 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4517 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23366 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31825 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1.131186 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 163.233809 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 31823 99.99% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31825 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27887 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24957.507082 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21503.440195 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16346.397027 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 27726 99.42% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.01% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 135 0.48% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 12 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27887 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2390831336 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.421124 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1018364500 -33.91% -33.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -4021746512 133.91% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -3003382012 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 23647 83.51% 83.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4670 16.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 28317 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32157 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::0 1006835500 -42.11% -42.11% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3397666836 142.11% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2390831336 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23366 83.80% 83.80% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4517 16.20% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27883 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31829 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32157 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28317 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31829 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27883 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28317 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 60474 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27883 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 59712 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20628760 # DTB read hits -system.cpu1.dtb.read_misses 24754 # DTB read misses -system.cpu1.dtb.write_hits 18600606 # DTB write hits -system.cpu1.dtb.write_misses 7403 # DTB write misses -system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 22434815 # DTB read hits +system.cpu1.dtb.read_misses 24397 # DTB read misses +system.cpu1.dtb.write_hits 18279230 # DTB write hits +system.cpu1.dtb.write_misses 7432 # DTB write misses +system.cpu1.dtb.flush_tlb 1208 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 17774 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 18079 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 948 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 971 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2501 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20653514 # DTB read accesses -system.cpu1.dtb.write_accesses 18608009 # DTB write accesses +system.cpu1.dtb.perms_faults 2561 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 22459212 # DTB read accesses +system.cpu1.dtb.write_accesses 18286662 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 39229366 # DTB hits -system.cpu1.dtb.misses 32157 # DTB misses -system.cpu1.dtb.accesses 39261523 # DTB accesses +system.cpu1.dtb.hits 40714045 # DTB hits +system.cpu1.dtb.misses 31829 # DTB misses +system.cpu1.dtb.accesses 40745874 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1320,134 +1318,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20715 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 930 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18416 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 19346 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27414.659361 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24764.281979 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13419.535342 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 9905 51.20% 51.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 9256 47.84% 99.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 65 0.34% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 99 0.51% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 7 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 19346 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20237 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20237 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 921 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17876 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20237 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20237 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20237 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18797 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28270.362292 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25022.223556 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18368.247187 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 18619 99.05% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.01% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 152 0.81% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 5 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18797 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 18416 95.19% 95.19% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 930 4.81% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 19346 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17876 95.10% 95.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 921 4.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18797 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20237 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20237 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19346 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19346 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 40061 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 109170509 # ITB inst hits -system.cpu1.itb.inst_misses 20715 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18797 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18797 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 39034 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 115530405 # ITB inst hits +system.cpu1.itb.inst_misses 20237 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1208 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13293 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13570 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 109191224 # ITB inst accesses -system.cpu1.itb.hits 109170509 # DTB hits -system.cpu1.itb.misses 20715 # DTB misses -system.cpu1.itb.accesses 109191224 # DTB accesses -system.cpu1.numCycles 1180099422 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 115550642 # ITB inst accesses +system.cpu1.itb.hits 115530405 # DTB hits +system.cpu1.itb.misses 20237 # DTB misses +system.cpu1.itb.accesses 115550642 # DTB accesses +system.cpu1.numCycles 1208095250 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 109095321 # Number of instructions committed -system.cpu1.committedOps 128047126 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 117680197 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 117915 # Number of float alu accesses -system.cpu1.num_func_calls 6450893 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16554916 # number of instructions that are conditional controls -system.cpu1.num_int_insts 117680197 # number of integer instructions -system.cpu1.num_fp_insts 117915 # number of float instructions -system.cpu1.num_int_register_reads 169047923 # number of times the integer registers were read -system.cpu1.num_int_register_writes 93200008 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 191658 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96888 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 28194465 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 28098874 # number of times the CC registers were written -system.cpu1.num_mem_refs 39226015 # number of memory refs -system.cpu1.num_load_insts 20627300 # Number of load instructions -system.cpu1.num_store_insts 18598715 # Number of store instructions -system.cpu1.num_idle_cycles 1154150302.947621 # Number of idle cycles -system.cpu1.num_busy_cycles 25949119.052379 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021989 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978011 # Percentage of idle cycles -system.cpu1.Branches 24363890 # Number of branches fetched +system.cpu1.committedInsts 115450057 # Number of instructions committed +system.cpu1.committedOps 134166441 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 122283306 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 117326 # Number of float alu accesses +system.cpu1.num_func_calls 6388598 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 19121650 # number of instructions that are conditional controls +system.cpu1.num_int_insts 122283306 # number of integer instructions +system.cpu1.num_fp_insts 117326 # number of float instructions +system.cpu1.num_int_register_reads 174904532 # number of times the integer registers were read +system.cpu1.num_int_register_writes 96587788 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 193112 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90280 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 31170492 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 31100176 # number of times the CC registers were written +system.cpu1.num_mem_refs 40711221 # number of memory refs +system.cpu1.num_load_insts 22433949 # Number of load instructions +system.cpu1.num_store_insts 18277272 # Number of store instructions +system.cpu1.num_idle_cycles 1181365230.793780 # Number of idle cycles +system.cpu1.num_busy_cycles 26730019.206220 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022126 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977874 # Percentage of idle cycles +system.cpu1.Branches 27316623 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 88601672 69.15% 69.15% # Class of executed instruction -system.cpu1.op_class::IntMult 269277 0.21% 69.36% # Class of executed instruction -system.cpu1.op_class::IntDiv 11730 0.01% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 13579 0.01% 69.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction -system.cpu1.op_class::MemRead 20627300 16.10% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 18598715 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 93240195 69.45% 69.45% # Class of executed instruction +system.cpu1.op_class::IntMult 272528 0.20% 69.66% # Class of executed instruction +system.cpu1.op_class::IntDiv 10833 0.01% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 11970 0.01% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu1.op_class::MemRead 22433949 16.71% 86.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 18277272 13.61% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 128122314 # Class of executed instruction +system.cpu1.op_class::total 134246789 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 40464780 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28154198 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1978898 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 29418306 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20974527 # Number of BTB hits +system.cpu2.branchPred.lookups 43822181 # Number of BP lookups +system.cpu2.branchPred.condPredicted 31010848 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2006659 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 32869256 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 23105809 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.297535 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4946229 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 331686 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.296112 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4850903 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329695 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1477,64 +1472,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 93767 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93767 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6983 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29518 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93767 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93767 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93767 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36501 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 24922.262404 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22135.996220 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 12304.178118 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 23409 64.13% 64.13% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12906 35.36% 99.49% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-98303 87 0.24% 99.73% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::98304-131071 74 0.20% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 7 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36501 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000228500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000228500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000228500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29518 80.87% 80.87% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6983 19.13% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36501 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93767 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 93863 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93863 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6661 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29634 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93863 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93863 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93863 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 36295 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24894.765119 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 21575.810526 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 16144.893393 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 36098 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 162 0.45% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 6 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 14 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 36295 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000225500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000225500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000225500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 29634 81.65% 81.65% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 6661 18.35% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 36295 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93863 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93767 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36501 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93863 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36295 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36501 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130268 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36295 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 130158 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28765084 # DTB read hits -system.cpu2.dtb.read_misses 78268 # DTB read misses -system.cpu2.dtb.write_hits 25322239 # DTB write hits -system.cpu2.dtb.write_misses 15499 # DTB write misses -system.cpu2.dtb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 31221716 # DTB read hits +system.cpu2.dtb.read_misses 78321 # DTB read misses +system.cpu2.dtb.write_hits 24527548 # DTB write hits +system.cpu2.dtb.write_misses 15542 # DTB write misses +system.cpu2.dtb.flush_tlb 1208 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22277 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 76 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2199 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 21789 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2014 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3811 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28843352 # DTB read accesses -system.cpu2.dtb.write_accesses 25337738 # DTB write accesses +system.cpu2.dtb.perms_faults 3746 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 31300037 # DTB read accesses +system.cpu2.dtb.write_accesses 24543090 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 54087323 # DTB hits -system.cpu2.dtb.misses 93767 # DTB misses -system.cpu2.dtb.accesses 54181090 # DTB accesses +system.cpu2.dtb.hits 55749264 # DTB hits +system.cpu2.dtb.misses 93863 # DTB misses +system.cpu2.dtb.accesses 55843127 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1564,85 +1555,85 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27119 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27119 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1817 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22640 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27119 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27119 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27119 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24457 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28043.607147 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25574.105463 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 12475.611214 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 11681 47.76% 47.76% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 12550 51.31% 99.08% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 85 0.35% 99.42% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 123 0.50% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24457 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000202500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000202500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000202500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22640 92.57% 92.57% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1817 7.43% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24457 # Table walker page sizes translated +system.cpu2.itb.walker.walks 27202 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27202 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1812 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22525 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27202 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27202 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27202 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24337 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28096.416978 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 24969.362897 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 17267.916673 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12983 53.35% 53.35% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11116 45.68% 99.02% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 182 0.75% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 36 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 10 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 4 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24337 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 22525 92.55% 92.55% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1812 7.45% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24337 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27119 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27119 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27202 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27202 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24457 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24457 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51576 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70111472 # ITB inst hits -system.cpu2.itb.inst_misses 27119 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24337 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24337 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51539 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 74458235 # ITB inst hits +system.cpu2.itb.inst_misses 27202 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1208 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16886 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16288 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 56888 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 55804 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70138591 # ITB inst accesses -system.cpu2.itb.hits 70111472 # DTB hits -system.cpu2.itb.misses 27119 # DTB misses -system.cpu2.itb.accesses 70138591 # DTB accesses -system.cpu2.numCycles 6662793368 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 74485437 # ITB inst accesses +system.cpu2.itb.hits 74458235 # DTB hits +system.cpu2.itb.misses 27202 # DTB misses +system.cpu2.itb.accesses 74485437 # DTB accesses +system.cpu2.numCycles 6814615454 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 148437005 # Number of instructions committed -system.cpu2.committedOps 174093973 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 14341019 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1575 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95890004718 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 44.886337 # CPI: cycles per instruction -system.cpu2.ipc 0.022278 # IPC: instructions per cycle +system.cpu2.committedInsts 154831636 # Number of instructions committed +system.cpu2.committedOps 179800875 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 13497272 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1503 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95900032594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 44.013069 # CPI: cycles per instruction +system.cpu2.ipc 0.022721 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 276177864 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6386615504 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 74718826 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50589890 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3325419 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50396966 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 36328478 # Number of BTB hits +system.cpu2.tickCycles 289096275 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6525519179 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 86474104 # Number of BP lookups +system.cpu3.branchPred.condPredicted 60464005 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3334878 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 62765880 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 44403586 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 72.084653 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9777895 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 104949 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 70.744784 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9643745 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 102837 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1672,91 +1663,86 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 514773 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 514773 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8632 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50765 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 320483 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 194290 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2154.802100 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 11919.135471 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-32767 190271 97.93% 97.93% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-65535 2868 1.48% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-98303 495 0.25% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-131071 352 0.18% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-163839 145 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::229376-262143 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::360448-393215 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 194290 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 239173 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 21856.421921 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 17938.758794 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.793116 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 234615 98.09% 98.09% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4213 1.76% 99.86% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 180 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 137 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 239173 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -26483974220 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.370007 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -27038933220 102.10% 102.10% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 309842500 -1.17% 100.93% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 102710000 -0.39% 100.54% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66075500 -0.25% 100.29% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 25941500 -0.10% 100.19% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 14268000 -0.05% 100.14% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 12970500 -0.05% 100.09% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 19273500 -0.07% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 3639000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 190500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 29000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 8000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 11000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -26483974220 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 50765 85.47% 85.47% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8632 14.53% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 59397 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 514773 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 507978 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 507978 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8239 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50131 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 318118 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 189860 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2312.543453 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 14225.767965 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 188735 99.41% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 609 0.32% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 339 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 67 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 60 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 13 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 189860 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 237967 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22746.445936 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18445.918313 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 18699.946785 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 233152 97.98% 97.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3733 1.57% 99.55% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 782 0.33% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 40 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 78 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 40 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 237967 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -31430994140 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.113026 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -32002753640 101.82% 101.82% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 312906500 -1.00% 100.82% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 109321000 -0.35% 100.48% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 69521000 -0.22% 100.25% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 26278000 -0.08% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 15239000 -0.05% 100.12% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14010000 -0.04% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 20193000 -0.06% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 4061500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 204000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 20000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 1500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -31430994140 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50131 85.88% 85.88% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8239 14.12% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 58370 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 507978 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 514773 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59397 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 507978 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58370 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59397 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 574170 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58370 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 566348 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58948022 # DTB read hits -system.cpu3.dtb.read_misses 349619 # DTB read misses -system.cpu3.dtb.write_hits 46411302 # DTB write hits -system.cpu3.dtb.write_misses 165154 # DTB write misses -system.cpu3.dtb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 67144172 # DTB read hits +system.cpu3.dtb.read_misses 346038 # DTB read misses +system.cpu3.dtb.write_hits 45597024 # DTB write hits +system.cpu3.dtb.write_misses 161940 # DTB write misses +system.cpu3.dtb.flush_tlb 1207 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29239 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 5206 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 30283 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 31663 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 59297641 # DTB read accesses -system.cpu3.dtb.write_accesses 46576456 # DTB write accesses +system.cpu3.dtb.perms_faults 33322 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 67490210 # DTB read accesses +system.cpu3.dtb.write_accesses 45758964 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 105359324 # DTB hits -system.cpu3.dtb.misses 514773 # DTB misses -system.cpu3.dtb.accesses 105874097 # DTB accesses +system.cpu3.dtb.hits 112741196 # DTB hits +system.cpu3.dtb.misses 507978 # DTB misses +system.cpu3.dtb.accesses 113249174 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1786,384 +1772,392 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 60795 # Table walker walks requested -system.cpu3.itb.walker.walksLong 60795 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1936 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41390 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8352 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 52443 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1489.417081 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 8610.325599 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 51982 99.12% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 282 0.54% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 109 0.21% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 37 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 52443 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 51678 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 27642.962189 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 23739.857132 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 16715.530485 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 50770 98.24% 98.24% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 774 1.50% 99.74% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 83 0.16% 99.90% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 35 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 9 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 51678 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -30778988516 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.762645 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.421863 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -7265808116 23.61% 23.61% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -23547141900 76.50% 100.11% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 29216500 -0.09% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 4017500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 490000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 170000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 67500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -30778988516 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 41390 95.53% 95.53% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1936 4.47% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 43326 # Table walker page sizes translated +system.cpu3.itb.walker.walks 60738 # Table walker walks requested +system.cpu3.itb.walker.walksLong 60738 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1986 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42002 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8255 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 52483 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1658.003544 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 10682.399901 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 51962 99.01% 99.01% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 312 0.59% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 51 0.10% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 81 0.15% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 17 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::393216-425983 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 52483 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 52243 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 29328.072660 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 24939.652289 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 21269.473767 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 27773 53.16% 53.16% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 23452 44.89% 98.05% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 257 0.49% 98.54% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 44 0.08% 98.63% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 455 0.87% 99.50% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 157 0.30% 99.80% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 13 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 52243 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -31433784640 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.872286 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.329149 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -3971528800 12.63% 12.63% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -27500486840 87.49% 100.12% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 33846500 -0.11% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 4000500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 384000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -31433784640 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 42002 95.49% 95.49% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1986 4.51% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 43988 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60795 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60795 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60738 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60738 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43326 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43326 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 104121 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 53907663 # ITB inst hits -system.cpu3.itb.inst_misses 60795 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43988 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43988 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 104726 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 61673296 # ITB inst hits +system.cpu3.itb.inst_misses 60738 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1180 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1207 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22179 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 23902 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 120136 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 114610 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 53968458 # ITB inst accesses -system.cpu3.itb.hits 53907663 # DTB hits -system.cpu3.itb.misses 60795 # DTB misses -system.cpu3.itb.accesses 53968458 # DTB accesses -system.cpu3.numCycles 361864421 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 61734034 # ITB inst accesses +system.cpu3.itb.hits 61673296 # DTB hits +system.cpu3.itb.misses 60738 # DTB misses +system.cpu3.itb.accesses 61734034 # DTB accesses +system.cpu3.numCycles 387266719 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 140139481 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 332397649 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 74718826 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 46106373 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 200741121 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7544543 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1439697 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 5770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2171 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 3065576 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 88539 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 4142 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 53769751 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2045312 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 24414 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 349258578 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.114486 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.357052 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 147097588 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 357588328 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 86474104 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 54047331 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 217420350 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7531775 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1493858 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 6577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1847 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2904102 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 100892 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 5652 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 61540793 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2049174 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 24233 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 372796591 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.109243 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.309692 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 267245928 76.52% 76.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10321823 2.96% 79.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10331128 2.96% 82.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7716473 2.21% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15764851 4.51% 89.15% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5041778 1.44% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5511234 1.58% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4828224 1.38% 93.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 22497139 6.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 281372813 75.48% 75.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 14372234 3.86% 79.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10265019 2.75% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7499968 2.01% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 21772422 5.84% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5084969 1.36% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5491693 1.47% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4844554 1.30% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 22092919 5.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 349258578 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.206483 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.918570 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 114369930 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 164038042 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 60584469 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7298385 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2965812 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11163267 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 817702 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 363461294 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2524053 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2965812 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 118569176 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 12281642 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 132557510 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 63592874 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 19289346 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 354946625 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 42029 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1018488 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 787978 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 8985547 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 1997 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 338843996 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 543179256 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 419420785 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 479701 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 284856001 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 53987990 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 8148289 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 7010381 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 40518568 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 57083242 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 48761213 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7628593 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8153720 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 337135094 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8186679 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 336664947 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 479828 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 45100588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 28943367 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 197497 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 349258578 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.963942 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.678060 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 372796591 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.223293 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.923364 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 121849508 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 170403265 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 70427838 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7160823 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2953176 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 13216170 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 824708 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 387980290 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2540688 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 2953176 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 125989175 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14295648 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 134676071 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73352513 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 21527795 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 379587949 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 66831 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1271643 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 1003345 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 11147601 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2215 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 363999702 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 575721975 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 441176724 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 501598 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 310075973 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 53923724 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7927696 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6812130 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39656771 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65059563 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 47956782 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7328499 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8072218 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 362054747 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7911785 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 361524933 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 476222 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 45084510 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 28958350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 197452 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 372796591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.969765 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.646815 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 218381855 62.53% 62.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 54040442 15.47% 78.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24694063 7.07% 85.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17645756 5.05% 90.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 13020798 3.73% 93.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9160873 2.62% 96.47% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6234653 1.79% 98.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3637468 1.04% 99.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2442670 0.70% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 227072164 60.91% 60.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 63499277 17.03% 77.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 26503560 7.11% 85.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 19490025 5.23% 90.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 15060105 4.04% 94.32% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9087170 2.44% 96.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6095598 1.64% 98.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3610933 0.97% 99.36% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2377759 0.64% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 349258578 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 372796591 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1713190 25.96% 25.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16354 0.25% 26.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1162 0.02% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2637813 39.97% 66.19% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2231741 33.81% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1687705 25.88% 25.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 16239 0.25% 26.13% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1469 0.02% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2644056 40.55% 66.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2171786 33.30% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 228589817 67.90% 67.90% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 839294 0.25% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 38427 0.01% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 187 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 41560 0.01% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 60136646 17.86% 86.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 47019015 13.97% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 246126710 68.08% 68.08% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 787460 0.22% 68.30% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40199 0.01% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 173 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 43036 0.01% 68.32% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 68327195 18.90% 87.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 46200141 12.78% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 336664947 # Type of FU issued -system.cpu3.iq.rate 0.930362 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6600260 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019605 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1029031717 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 390494788 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 324869188 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 636843 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 315952 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 284328 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 342924564 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 340642 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2686629 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 361524933 # Type of FU issued +system.cpu3.iq.rate 0.933530 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6521255 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.018038 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1102172941 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 415098174 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 349515725 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 670993 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 333176 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 300023 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 367687576 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 358593 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2643676 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9062852 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11957 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 394369 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4946237 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9059982 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11985 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 386621 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4959688 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2102231 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 3983237 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2122346 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4168343 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2965812 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8240311 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 3183987 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 345400316 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1015101 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 57083242 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 48761213 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6857312 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 127001 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3008020 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 394369 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1508943 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1318655 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2827598 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 332842425 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58939894 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3314806 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 2953176 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9025973 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 4011376 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 370041408 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1020577 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65059563 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 47956782 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6665282 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 121223 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3842845 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 386621 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1507009 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1322517 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2829526 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 357707316 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 67134694 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3315560 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 78543 # number of nop insts executed -system.cpu3.iew.exec_refs 105350305 # number of memory reference insts executed -system.cpu3.iew.exec_branches 61793426 # Number of branches executed -system.cpu3.iew.exec_stores 46410411 # Number of stores executed -system.cpu3.iew.exec_rate 0.919799 # Inst execution rate -system.cpu3.iew.wb_sent 325835982 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 325153516 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 160610684 # num instructions producing a value -system.cpu3.iew.wb_consumers 278606679 # num instructions consuming a value +system.cpu3.iew.exec_nop 74876 # number of nop insts executed +system.cpu3.iew.exec_refs 112730172 # number of memory reference insts executed +system.cpu3.iew.exec_branches 73596465 # Number of branches executed +system.cpu3.iew.exec_stores 45595478 # Number of stores executed +system.cpu3.iew.exec_rate 0.923672 # Inst execution rate +system.cpu3.iew.wb_sent 350496089 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 349815748 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 170914672 # num instructions producing a value +system.cpu3.iew.wb_consumers 300090920 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.898551 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576478 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.903294 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.569543 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 45121096 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7989182 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2518769 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 341571330 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.878941 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.873545 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 45110535 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7714333 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2522004 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 365126198 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.889780 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.821639 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 232593389 68.10% 68.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 52799684 15.46% 83.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18973015 5.55% 89.11% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8542771 2.50% 91.61% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6283805 1.84% 93.45% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3713979 1.09% 94.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3487678 1.02% 95.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2200102 0.64% 96.20% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12976907 3.80% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 241067877 66.02% 66.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 60177968 16.48% 82.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 23030537 6.31% 88.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 12678452 3.47% 92.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6124253 1.68% 93.96% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3724103 1.02% 94.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3468414 0.95% 95.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2157144 0.59% 96.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12697450 3.48% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 341571330 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 255441658 # Number of instructions committed -system.cpu3.commit.committedOps 300221180 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 365126198 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 280963321 # Number of instructions committed +system.cpu3.commit.committedOps 324882017 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91835365 # Number of memory references committed -system.cpu3.commit.loads 48020389 # Number of loads committed -system.cpu3.commit.membars 2080926 # Number of memory barriers committed -system.cpu3.commit.branches 57030615 # Number of branches committed -system.cpu3.commit.fp_insts 272912 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 275960484 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7595427 # Number of function calls committed. +system.cpu3.commit.refs 98996674 # Number of memory references committed +system.cpu3.commit.loads 55999580 # Number of loads committed +system.cpu3.commit.membars 1980658 # Number of memory barriers committed +system.cpu3.commit.branches 68831058 # Number of branches committed +system.cpu3.commit.fp_insts 288600 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 294637419 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7471816 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 207669074 69.17% 69.17% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 652533 0.22% 69.39% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 28496 0.01% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.40% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 35712 0.01% 69.41% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 48020389 16.00% 85.41% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 43814976 14.59% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 225203928 69.32% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 613924 0.19% 69.51% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 30363 0.01% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 37128 0.01% 69.53% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 55999580 17.24% 86.77% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 42997094 13.23% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 300221180 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12976907 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 671801943 # The number of ROB reads -system.cpu3.rob.rob_writes 698382232 # The number of ROB writes -system.cpu3.timesIdled 2359266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 12605843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98651627369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 255441658 # Number of Instructions Simulated -system.cpu3.committedOps 300221180 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.416623 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.416623 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.705904 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.705904 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 392429814 # number of integer regfile reads -system.cpu3.int_regfile_writes 232475172 # number of integer regfile writes -system.cpu3.fp_regfile_reads 557185 # number of floating regfile reads -system.cpu3.fp_regfile_writes 341168 # number of floating regfile writes -system.cpu3.cc_regfile_reads 70618800 # number of cc regfile reads -system.cpu3.cc_regfile_writes 71286741 # number of cc regfile writes -system.cpu3.misc_regfile_reads 655702130 # number of misc regfile reads -system.cpu3.misc_regfile_writes 8023774 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40266 # Transaction distribution -system.iobus.trans_dist::ReadResp 40266 # Transaction distribution +system.cpu3.commit.op_class_0::total 324882017 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12697450 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 720404728 # The number of ROB reads +system.cpu3.rob.rob_writes 747667993 # The number of ROB writes +system.cpu3.timesIdled 2347863 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 14470128 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98704132703 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 280963321 # Number of Instructions Simulated +system.cpu3.committedOps 324882017 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.378353 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.378353 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.725503 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.725503 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 414317420 # number of integer regfile reads +system.cpu3.int_regfile_writes 245959017 # number of integer regfile writes +system.cpu3.fp_regfile_reads 580593 # number of floating regfile reads +system.cpu3.fp_regfile_writes 365724 # number of floating regfile writes +system.cpu3.cc_regfile_reads 82484676 # number of cc regfile reads +system.cpu3.cc_regfile_writes 83140356 # number of cc regfile writes +system.cpu3.misc_regfile_reads 708702435 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7780128 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40264 # Transaction distribution +system.iobus.trans_dist::ReadResp 40264 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2182,11 +2176,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353606 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2203,21 +2197,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13439000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 27822000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) @@ -2228,70 +2218,72 @@ system.iobus.reqLayer16.occupancy 4000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 9713000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 10208000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18683000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 237657786 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 258644416 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 43053000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 58071000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 55076000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 75528000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.421040 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.429241 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13087689445509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.547391 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.873649 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221712 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651315 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089149965509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.541829 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.887412 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221364 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430463 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651828 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses +system.iocache.demand_misses::total 8851 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 399236664 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 399236664 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 5327578122 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5327578122 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 399236664 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 399236664 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 399236664 # number of overall miss cycles -system.iocache.overall_miss_latency::total 399236664 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8811 # number of overall misses +system.iocache.overall_misses::total 8851 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1063595797 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1063595797 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 6255460619 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6255460619 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1063595797 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1063595797 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1063595797 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1063595797 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2305,504 +2297,504 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 45300.880971 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 45111.487458 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 49947.293576 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 49947.293576 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 45096.200610 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 45096.200610 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7536 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120712.268414 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120207.481578 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58646.409463 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58646.409463 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120712.268414 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120166.737883 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120712.268414 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120166.737883 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 21718 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 866 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.702079 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.521263 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 2210 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 2210 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 45088 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 45088 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 2210 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 2210 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 2210 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 2210 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 288736664 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 288736664 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3073178122 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3073178122 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 288736664 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 288736664 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 288736664 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 288736664 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.249718 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.422711 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.422711 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.249633 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.249633 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130650.074208 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130650.074208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68159.557355 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68159.557355 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130650.074208 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130650.074208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130650.074208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130650.074208 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 5692 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5692 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 48208 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 48208 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 5692 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 5692 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 5692 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 5692 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 778995797 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 778995797 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3845060619 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3845060619 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 778995797 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 778995797 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 778995797 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 778995797 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.643309 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.451961 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.451961 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.643091 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.643091 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136858.010717 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136858.010717 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79759.803746 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79759.803746 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136858.010717 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136858.010717 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136858.010717 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136858.010717 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1184273 # number of replacements -system.l2c.tags.tagsinuse 65309.557565 # Cycle average of tags in use -system.l2c.tags.total_refs 47546139 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1247279 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.119891 # Average number of references to valid blocks. +system.l2c.tags.replacements 1132465 # number of replacements +system.l2c.tags.tagsinuse 65345.559033 # Cycle average of tags in use +system.l2c.tags.total_refs 47267039 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1194837 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.559404 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36497.090356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 128.195847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 207.365343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3477.103411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10892.259737 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.622029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 64.439339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 663.388118 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2525.804190 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.130985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 52.876796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2102.725425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2793.262675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 102.733184 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 141.240216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2056.053767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 3525.266147 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.556901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003164 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.166203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000983 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.038541 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.042622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.031373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.053791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996545 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 327 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62679 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53967 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004990 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.956406 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 421248793 # Number of tag accesses -system.l2c.tags.data_accesses 421248793 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 162889 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 111955 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 57699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 43341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 155107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 59126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 295251 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 109680 # number of ReadReq hits -system.l2c.ReadReq_hits::total 995048 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7547308 # number of Writeback hits -system.l2c.Writeback_hits::total 7547308 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3780 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1173 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2840 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9365 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 632256 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 192717 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 281149 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 476183 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1582305 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5480649 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1714018 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3866218 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4626735 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15687620 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2570779 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 762751 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1043289 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1899052 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6275871 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 287062 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 90395 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 123163 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 231327 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 731947 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 162889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 111955 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5480649 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3203035 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 57699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 43341 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1714018 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 955468 # 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mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.092213 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.017326 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.017326 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 77417.632099 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20654.547501 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20753.964059 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20748.769685 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20729.583785 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 46000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 46000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70601.953858 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71311.158103 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88007.118763 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 79267.714322 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73752.099458 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72693.790988 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73643.538987 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78775.181390 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76023.759050 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69397.608538 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78042.152984 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97872.175338 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88033.309719 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159200.689423 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157693.140013 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161550.314465 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159477.213457 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163690.507152 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159670.164560 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169338.517016 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 164275.886677 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161333.848191 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158633.651010 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165303.573368 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161768.236176 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.777603 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.784687 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.782907 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.460163 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.189909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.185515 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.171073 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.103849 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.004217 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006099 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006447 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003845 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.031469 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.038400 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.039760 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022668 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.162751 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.166018 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.179556 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.076830 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007425 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.067776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002985 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.006771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.071572 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003301 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008127 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006447 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.069512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.016506 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007425 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.067776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002985 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.006771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071572 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003301 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008127 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006447 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.069512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.016506 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127435 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127687.301587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 127083.148559 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 128323.376623 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 129259.506680 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 126622.294372 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 127819.444444 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70652.580572 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70748.090955 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70756.261228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70730.586571 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 72000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121182.109143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122421.302905 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136798.395569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129026.681942 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124416.316642 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123670.088543 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124921.835244 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130791.787725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127817.814428 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120805.864146 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129234.810101 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145863.890621 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 136683.359554 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127435 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127687.301587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122072.584105 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 127083.148559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128323.376623 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123460.407997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 129259.506680 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126622.294372 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134141.067640 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 127918.422302 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127687.301587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122072.584105 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 127083.148559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128323.376623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123460.407997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 129259.506680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126622.294372 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134141.067640 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 127918.422302 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174237.698139 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 171885.668153 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169548.511410 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171964.147239 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179316.406830 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 176961.405530 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173916.934965 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 176801.004048 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 176682.666190 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 174337.387710 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171663.769585 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 174299.583735 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76737 # Transaction distribution -system.membus.trans_dist::ReadResp 455193 # Transaction distribution -system.membus.trans_dist::WriteReq 33647 # Transaction distribution -system.membus.trans_dist::WriteResp 33647 # Transaction distribution -system.membus.trans_dist::Writeback 1091179 # Transaction distribution -system.membus.trans_dist::CleanEvict 208864 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34786 # Transaction distribution +system.membus.trans_dist::ReadReq 76740 # Transaction distribution +system.membus.trans_dist::ReadResp 434267 # Transaction distribution +system.membus.trans_dist::WriteReq 33649 # Transaction distribution +system.membus.trans_dist::WriteResp 33649 # Transaction distribution +system.membus.trans_dist::Writeback 1051076 # Transaction distribution +system.membus.trans_dist::CleanEvict 194214 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34391 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34788 # Transaction distribution -system.membus.trans_dist::ReadExReq 906494 # Transaction distribution -system.membus.trans_dist::ReadExResp 906494 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 378456 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34393 # Transaction distribution +system.membus.trans_dist::ReadExReq 878752 # Transaction distribution +system.membus.trans_dist::ReadExResp 878752 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 357527 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3898162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4027556 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 345368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4372924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3876721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4219049 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144864864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 145034278 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7356288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7356288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 152390566 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 691 # Total snoops (count) -system.membus.snoop_fanout::samples 2837421 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13532 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139182816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 139352250 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7292736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7292736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 146644986 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1691 # Total snoops (count) +system.membus.snoop_fanout::samples 2735655 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2837421 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2735655 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2837421 # Request fanout histogram -system.membus.reqLayer0.occupancy 49386500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2735655 # Request fanout histogram +system.membus.reqLayer0.occupancy 67480499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1639500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1687500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3223716711 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3012404078 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3001422636 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2789968901 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 89214499 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 111926505 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3157,11 +3145,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3200,54 +3188,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 1500754 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23827950 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8025102 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 18108882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43452 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43455 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1996830 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1996830 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15787707 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6541408 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1269700 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1224612 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47446864 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29502710 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 824705 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79515418 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010580372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029542098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2979800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6154816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2049257086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 987636 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 53377948 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039876 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195669 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 51428395 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26044342 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2333 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 1485574 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23674636 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33649 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33649 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7959451 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 17972959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43013 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43018 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1971030 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1971030 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15726300 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6468003 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1272625 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1224417 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47261977 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29193320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 817918 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1719148 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 78992363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006650324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1020855654 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2953520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6072336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2036531834 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1644943 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 53692689 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011673 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.107408 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 51249425 96.01% 96.01% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 2128523 3.99% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 53065946 98.83% 98.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 626743 1.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 53377948 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 20681814986 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 53692689 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 20600677992 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 436500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 830192 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15410337923 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15256484341 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7854888294 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7870736599 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 293722728 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 292647751 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 713107905 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 703926527 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b59b70a33..ec562306e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.241896 # Number of seconds simulated -sim_ticks 51241895910000 # Number of ticks simulated -final_tick 51241895910000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.329008 # Number of seconds simulated +sim_ticks 51329007806000 # Number of ticks simulated +final_tick 51329007806000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95627 # Simulator instruction rate (inst/s) -host_op_rate 112378 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5423934154 # Simulator tick rate (ticks/s) -host_mem_usage 730628 # Number of bytes of host memory used -host_seconds 9447.37 # Real time elapsed on the host -sim_insts 903425057 # Number of instructions simulated -sim_ops 1061671663 # Number of ops (including micro ops) simulated +host_inst_rate 122530 # Simulator instruction rate (inst/s) +host_op_rate 143983 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7088851393 # Simulator tick rate (ticks/s) +host_mem_usage 738964 # Number of bytes of host memory used +host_seconds 7240.81 # Real time elapsed on the host +sim_insts 887219290 # Number of instructions simulated +sim_ops 1042552088 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 165376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 148160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3796224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 45159832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 160832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 148224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3625536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 44632368 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 406656 # Number of bytes read from this memory -system.physmem.bytes_read::total 98243208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3796224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3625536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7421760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83214784 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83235364 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2584 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 59316 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 705630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2316 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 697386 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6354 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1535063 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1300231 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1302804 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 881307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 871013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1917244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 144838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1623960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1624362 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1623960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 881708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 871013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3541605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1535063 # Number of read requests accepted -system.physmem.writeReqs 1302804 # Number of write requests accepted -system.physmem.readBursts 1535063 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1302804 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 98199040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44992 # Total number of bytes read from write queue -system.physmem.bytesWritten 83234496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 98243208 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83235364 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 703 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 144188 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 94050 # Per bank write bursts -system.physmem.perBankRdBursts::1 94624 # Per bank write bursts -system.physmem.perBankRdBursts::2 91446 # Per bank write bursts -system.physmem.perBankRdBursts::3 92243 # Per bank write bursts -system.physmem.perBankRdBursts::4 98717 # Per bank write bursts -system.physmem.perBankRdBursts::5 106707 # Per bank write bursts -system.physmem.perBankRdBursts::6 93934 # Per bank write bursts -system.physmem.perBankRdBursts::7 93123 # Per bank write bursts -system.physmem.perBankRdBursts::8 90055 # Per bank write bursts -system.physmem.perBankRdBursts::9 118648 # Per bank write bursts -system.physmem.perBankRdBursts::10 94680 # Per bank write bursts -system.physmem.perBankRdBursts::11 96202 # Per bank write bursts -system.physmem.perBankRdBursts::12 91550 # Per bank write bursts -system.physmem.perBankRdBursts::13 95334 # Per bank write bursts -system.physmem.perBankRdBursts::14 93205 # Per bank write bursts -system.physmem.perBankRdBursts::15 89842 # Per bank write bursts -system.physmem.perBankWrBursts::0 79067 # Per bank write bursts -system.physmem.perBankWrBursts::1 80858 # Per bank write bursts -system.physmem.perBankWrBursts::2 78439 # Per bank write bursts -system.physmem.perBankWrBursts::3 80901 # Per bank write bursts -system.physmem.perBankWrBursts::4 84568 # Per bank write bursts -system.physmem.perBankWrBursts::5 88799 # Per bank write bursts -system.physmem.perBankWrBursts::6 79324 # Per bank write bursts -system.physmem.perBankWrBursts::7 81423 # Per bank write bursts -system.physmem.perBankWrBursts::8 78366 # Per bank write bursts -system.physmem.perBankWrBursts::9 84879 # Per bank write bursts -system.physmem.perBankWrBursts::10 80434 # Per bank write bursts -system.physmem.perBankWrBursts::11 83122 # Per bank write bursts -system.physmem.perBankWrBursts::12 79318 # Per bank write bursts -system.physmem.perBankWrBursts::13 82355 # Per bank write bursts -system.physmem.perBankWrBursts::14 80105 # Per bank write bursts -system.physmem.perBankWrBursts::15 78581 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 156608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 147648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4011328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41948256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 137216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 124672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3256192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 42225192 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430144 # Number of bytes read from this memory +system.physmem.bytes_read::total 92437256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4011328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3256192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7267520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78326464 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory +system.physmem.bytes_written::total 78347044 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 62677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 655450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1948 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 50878 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 659773 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1444345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1223851 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1226424 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 78149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 817243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 822638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1800878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 78149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1525969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1526370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1525969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 78149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 817243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 823039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3327247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1444345 # Number of read requests accepted +system.physmem.writeReqs 1226424 # Number of write requests accepted +system.physmem.readBursts 1444345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1226424 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 92386688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51392 # Total number of bytes read from write queue +system.physmem.bytesWritten 78346944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 92437256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78347044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 803 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 143260 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 87933 # Per bank write bursts +system.physmem.perBankRdBursts::1 93643 # Per bank write bursts +system.physmem.perBankRdBursts::2 85045 # Per bank write bursts +system.physmem.perBankRdBursts::3 85481 # Per bank write bursts +system.physmem.perBankRdBursts::4 86547 # Per bank write bursts +system.physmem.perBankRdBursts::5 98902 # Per bank write bursts +system.physmem.perBankRdBursts::6 89510 # Per bank write bursts +system.physmem.perBankRdBursts::7 89009 # Per bank write bursts +system.physmem.perBankRdBursts::8 83048 # Per bank write bursts +system.physmem.perBankRdBursts::9 114994 # Per bank write bursts +system.physmem.perBankRdBursts::10 94557 # Per bank write bursts +system.physmem.perBankRdBursts::11 91990 # Per bank write bursts +system.physmem.perBankRdBursts::12 84421 # Per bank write bursts +system.physmem.perBankRdBursts::13 88294 # Per bank write bursts +system.physmem.perBankRdBursts::14 83729 # Per bank write bursts +system.physmem.perBankRdBursts::15 86439 # Per bank write bursts +system.physmem.perBankWrBursts::0 75039 # Per bank write bursts +system.physmem.perBankWrBursts::1 78494 # Per bank write bursts +system.physmem.perBankWrBursts::2 73313 # Per bank write bursts +system.physmem.perBankWrBursts::3 75746 # Per bank write bursts +system.physmem.perBankWrBursts::4 74304 # Per bank write bursts +system.physmem.perBankWrBursts::5 82444 # Per bank write bursts +system.physmem.perBankWrBursts::6 75935 # Per bank write bursts +system.physmem.perBankWrBursts::7 77729 # Per bank write bursts +system.physmem.perBankWrBursts::8 72743 # Per bank write bursts +system.physmem.perBankWrBursts::9 81620 # Per bank write bursts +system.physmem.perBankWrBursts::10 78637 # Per bank write bursts +system.physmem.perBankWrBursts::11 78702 # Per bank write bursts +system.physmem.perBankWrBursts::12 73730 # Per bank write bursts +system.physmem.perBankWrBursts::13 77135 # Per bank write bursts +system.physmem.perBankWrBursts::14 73140 # Per bank write bursts +system.physmem.perBankWrBursts::15 75460 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 26 # Number of times write queue was full causing retry -system.physmem.totGap 51241894805000 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 51329006651000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1535048 # Read request sizes (log2) +system.physmem.readPktSize::6 1444330 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1300231 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 696212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 434080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 231480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 166858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1223851 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 664689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 399415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 215277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 158221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -162,221 +165,221 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 752 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 29697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 77035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 77508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 81035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 83877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 86632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 85119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 87954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 84437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 96180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 104378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 81922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 85007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 77822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 599076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.854983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.463010 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.270126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239456 39.97% 39.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 137779 23.00% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 58288 9.73% 72.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28412 4.74% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23965 4.00% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14114 2.36% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13744 2.29% 86.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10019 1.67% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73299 12.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 599076 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 75110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.428012 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 233.528819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 75106 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::11 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 73660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 75063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 75253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 77353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 77886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 84511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 79729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 90742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 76207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 79989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 72267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.133596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.783036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.925309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 224869 39.92% 39.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 128828 22.87% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55416 9.84% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26482 4.70% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23365 4.15% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12858 2.28% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13591 2.41% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8972 1.59% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 68848 12.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563229 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 70176 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.570010 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 230.699325 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 70171 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::61440-63487 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 75110 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 75110 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.315124 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.869848 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.130210 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 32 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 20 0.03% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 14 0.02% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 62 0.08% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70906 94.40% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1379 1.84% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 596 0.79% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 313 0.42% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 370 0.49% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 506 0.67% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 145 0.19% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.05% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 45 0.06% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 34 0.05% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 32 0.04% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 33 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 412 0.55% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 33 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 44 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 8 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 75110 # Writes before turning the bus around for reads -system.physmem.totQLat 44722536913 # Total ticks spent queuing -system.physmem.totMemAccLat 73491786913 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7671800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29147.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 70176 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 70176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.444297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.915567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.713323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 50 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 20 0.03% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 12 0.02% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 57 0.08% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 66189 94.32% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1492 2.13% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 215 0.31% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 476 0.68% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 85 0.12% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 378 0.54% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 194 0.28% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 38 0.05% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 68 0.10% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 132 0.19% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 30 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 483 0.69% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 27 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 113 0.16% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 70176 # Writes before turning the bus around for reads +system.physmem.totQLat 41972985964 # Total ticks spent queuing +system.physmem.totMemAccLat 69039398464 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7217710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29076.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47897.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47826.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing -system.physmem.readRowHits 1262545 # Number of row buffer hits during reads -system.physmem.writeRowHits 973277 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.84 # Row buffer hit rate for writes -system.physmem.avgGap 18056482.14 # Average gap between requests -system.physmem.pageHitRate 78.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2313095400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1262105625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5965736400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4233895920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235329874865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29661514581750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34257490791960 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.544567 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49344314821819 # Time in different power states -system.physmem_0.memoryStateTime::REF 1711079500000 # Time in different power states +system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.49 # Average write queue length when enqueuing +system.physmem.readRowHits 1185538 # Number of row buffer hits during reads +system.physmem.writeRowHits 918946 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes +system.physmem.avgGap 19218811.75 # Average gap between requests +system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2148975360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1172556000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5585346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3972265920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1240688413800 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29709081656250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34315210484610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.534456 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49423456234980 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713988120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 186501218681 # Time in different power states +system.physmem_0.memoryStateTime::ACT 191563442520 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2215919160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1209082875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6002224800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4193596800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1231628029245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29664761814750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34256882169630 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.532689 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49349717648088 # Time in different power states -system.physmem_1.memoryStateTime::REF 1711079500000 # Time in different power states +system.physmem_1.actEnergy 2109035880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1150763625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5674281600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3960362160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1239780982635 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29709877648500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34315114345680 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.532583 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49424762025236 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713988120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 181098330662 # Time in different power states +system.physmem_1.memoryStateTime::ACT 190257652264 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_read::cpu1.inst 1024 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 2148 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 1088 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 1024 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 2112 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 17 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131237057 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89167205 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5638568 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 88557097 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64192129 # Number of BTB hits +system.cpu0.branchPred.lookups 131402033 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89056413 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5742935 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89027832 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64073858 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.486713 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17175820 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 188370 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.970592 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17186238 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 188408 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,84 +410,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 905525 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 905525 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16897 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 92924 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 558822 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 346703 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2425.430412 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 13757.880539 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 344211 99.28% 99.28% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1816 0.52% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 412 0.12% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 106 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 81 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 346703 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 421563 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22489.281555 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18275.838186 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16656.658640 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 412599 97.87% 97.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7935 1.88% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 523 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 370 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 86 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 421563 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 359417936788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.126321 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.679023 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 358421610788 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 547811500 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 199809500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 118742000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 45429500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 23353000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 23408000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 31953500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 5493500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 315500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 359417936788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 92925 84.61% 84.61% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16897 15.39% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 109822 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 905525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 880195 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 880195 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16466 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89406 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 539518 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 340677 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2766.077546 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 16593.074042 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 337825 99.16% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1415 0.42% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 964 0.28% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 183 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 175 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 39 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 340677 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 406676 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23311.011714 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18634.861317 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20757.119040 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 397195 97.67% 97.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6941 1.71% 99.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1728 0.42% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 125 0.03% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 435 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 140 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 34 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 406676 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 373167653756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.157772 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.693071 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 372147551256 99.73% 99.73% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 557799500 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 204631000 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 121085000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 47750000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 25413500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26015000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 31058000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 5928000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 324500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 31000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 25000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 28000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 7000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::56-59 7000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 373167653756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 89406 84.45% 84.45% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16466 15.55% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 105872 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 880195 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 905525 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109822 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 880195 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105872 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109822 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1015347 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105872 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 986067 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104324024 # DTB read hits -system.cpu0.dtb.read_misses 622142 # DTB read misses -system.cpu0.dtb.write_hits 81549080 # DTB write hits -system.cpu0.dtb.write_misses 283383 # DTB write misses -system.cpu0.dtb.flush_tlb 1078 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104380254 # DTB read hits +system.cpu0.dtb.read_misses 607183 # DTB read misses +system.cpu0.dtb.write_hits 80883417 # DTB write hits +system.cpu0.dtb.write_misses 273012 # DTB write misses +system.cpu0.dtb.flush_tlb 1104 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56138 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9448 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55971 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8743 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 55690 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 104946166 # DTB read accesses -system.cpu0.dtb.write_accesses 81832463 # DTB write accesses +system.cpu0.dtb.perms_faults 56844 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 104987437 # DTB read accesses +system.cpu0.dtb.write_accesses 81156429 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 185873104 # DTB hits -system.cpu0.dtb.misses 905525 # DTB misses -system.cpu0.dtb.accesses 186778629 # DTB accesses +system.cpu0.dtb.hits 185263671 # DTB hits +system.cpu0.dtb.misses 880195 # DTB misses +system.cpu0.dtb.accesses 186143866 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,844 +523,848 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 104491 # Table walker walks requested -system.cpu0.itb.walker.walksLong 104491 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2977 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70833 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14071 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 90420 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1597.942933 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9019.721733 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 89473 98.95% 98.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 526 0.58% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 276 0.31% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 90 0.10% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 22 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 90420 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 87881 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27928.608004 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23671.030961 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18442.594011 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 85773 97.60% 97.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1788 2.03% 99.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 210 0.24% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 87881 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 587048610976 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.928143 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.258729 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 42249088256 7.20% 7.20% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 544740674220 92.79% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 52941500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 5346000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 541000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 587048610976 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 70833 95.97% 95.97% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2977 4.03% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 73810 # Table walker page sizes translated +system.cpu0.itb.walker.walks 105005 # Table walker walks requested +system.cpu0.itb.walker.walksLong 105005 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3046 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71369 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14507 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90498 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1949.556896 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 12931.664385 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89434 98.82% 98.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 551 0.61% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.10% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 107 0.12% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 211 0.23% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 47 0.05% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90498 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 88922 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29750.028115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24620.054553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 24536.459942 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 86625 97.42% 97.42% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 636 0.72% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1404 1.58% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 126 0.14% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 88922 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 300108383224 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.830431 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -249135515800 -83.02% -83.02% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 549170051524 182.99% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 65847000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6561000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 1119000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 120500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 200000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 300108383224 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 71369 95.91% 95.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3046 4.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 74415 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 104491 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 104491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105005 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105005 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 178301 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 93910274 # ITB inst hits -system.cpu0.itb.inst_misses 104491 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74415 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74415 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 179420 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94426208 # ITB inst hits +system.cpu0.itb.inst_misses 105005 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1078 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1104 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41605 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41718 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 209342 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203794 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94014765 # ITB inst accesses -system.cpu0.itb.hits 93910274 # DTB hits -system.cpu0.itb.misses 104491 # DTB misses -system.cpu0.itb.accesses 94014765 # DTB accesses -system.cpu0.numCycles 672837873 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94531213 # ITB inst accesses +system.cpu0.itb.hits 94426208 # DTB hits +system.cpu0.itb.misses 105005 # DTB misses +system.cpu0.itb.accesses 94531213 # DTB accesses +system.cpu0.numCycles 693924076 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 242596168 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 583871358 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131237057 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81367949 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 391672300 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 12912795 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2559887 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21371 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5907 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5496890 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 161597 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2291 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 93683695 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3482115 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41656 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 648972539 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.054070 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.303352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 245365223 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 583481750 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131402033 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81260096 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 404572474 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13127390 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2693259 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 25075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5895 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5426941 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 179188 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 4152 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94205115 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3543246 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41874 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 664835628 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.027383 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.280090 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 504751488 77.78% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18012631 2.78% 80.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 17993966 2.77% 83.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13374247 2.06% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28570124 4.40% 89.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8915108 1.37% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9700378 1.49% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8355653 1.29% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39298944 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 520667894 78.32% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18098994 2.72% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18311074 2.75% 83.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13311384 2.00% 85.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28016067 4.21% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9084552 1.37% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9729872 1.46% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8406845 1.26% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39208946 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 648972539 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.195050 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.867774 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 196814484 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 328839067 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 104545498 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13685712 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5085585 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19454701 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1390261 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 638009836 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4286683 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5085585 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 204391005 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 27392255 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 259209600 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 110517948 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 42373779 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 623249202 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 71579 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1876177 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1615058 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 22749976 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3905 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 596805281 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 963507479 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 737465972 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 746816 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 504819765 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 91985511 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15562034 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13603964 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 76990444 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100130044 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85693466 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13752433 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14485683 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 591325254 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15668453 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 593122197 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 836144 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77301127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 49722084 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 361977 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 648972539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.913940 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.642087 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 664835628 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189361 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.840844 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199358459 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 341820249 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105168047 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13323606 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5162847 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19689498 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1420951 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 636719093 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4377127 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5162847 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 206863652 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 31387432 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259611771 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 110843507 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 50963626 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 621821272 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 119952 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2228381 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1945503 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31637065 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3952 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 595122984 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 956623907 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 735190096 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 738559 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 501301772 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 93821212 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14866038 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12879620 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 74385297 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100195270 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85014336 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13702275 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14674859 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 590272104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14944858 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 591104249 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 830680 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 78609056 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 50293897 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 361003 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 664835628 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.889098 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.627888 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 415433099 64.01% 64.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 99398694 15.32% 79.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43154141 6.65% 85.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30671240 4.73% 90.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22754813 3.51% 94.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15949435 2.46% 96.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10913282 1.68% 98.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6427298 0.99% 99.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4270537 0.66% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 433426304 65.19% 65.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 96952426 14.58% 79.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43294447 6.51% 86.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30849550 4.64% 90.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22862967 3.44% 94.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 15973478 2.40% 96.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10856280 1.63% 98.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6404067 0.96% 99.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4216109 0.63% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 648972539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 664835628 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2981405 25.56% 25.56% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22602 0.19% 25.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2507 0.02% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4779561 40.98% 66.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3875984 33.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3013815 25.84% 25.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22977 0.20% 26.04% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2673 0.02% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4796217 41.12% 67.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3826853 32.81% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 47 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 402622584 67.88% 67.88% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1399505 0.24% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65721 0.01% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 48 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 57538 0.01% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106372763 17.93% 86.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82603986 13.93% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 58 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 401137490 67.86% 67.86% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1467252 0.25% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65623 0.01% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 154 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 57449 0.01% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106450027 18.01% 86.14% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 81926148 13.86% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 593122197 # Type of FU issued -system.cpu0.iq.rate 0.881523 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11662060 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1846708499 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 684493895 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 571889273 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1006638 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 498386 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 446935 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 604246281 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 537929 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4762645 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 591104249 # Type of FU issued +system.cpu0.iq.rate 0.851828 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11662537 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019730 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1858540164 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 684045272 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 569697611 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 997179 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 495349 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 443319 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 602234444 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 532284 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4680430 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15679208 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 19927 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 708487 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8639603 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15887962 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 725982 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8698150 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3917286 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7883426 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3921331 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7846897 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5085585 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15009758 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 10941422 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 607129936 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1704783 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100130044 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85693466 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13307217 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 240581 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10607814 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 708487 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2549086 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2233115 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4782201 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 586634430 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104313037 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5594967 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5162847 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 16668961 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 12768791 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 605350499 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1734594 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100195270 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85014336 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12589274 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 229167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 12454098 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 725982 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2593635 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2277415 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4871050 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 584543415 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104370380 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5693430 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136229 # number of nop insts executed -system.cpu0.iew.exec_refs 185865379 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108795926 # Number of branches executed -system.cpu0.iew.exec_stores 81552342 # Number of stores executed -system.cpu0.iew.exec_rate 0.871881 # Inst execution rate -system.cpu0.iew.wb_sent 573547999 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 572336208 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 282398495 # num instructions producing a value -system.cpu0.iew.wb_consumers 490722197 # num instructions consuming a value +system.cpu0.iew.exec_nop 133537 # number of nop insts executed +system.cpu0.iew.exec_refs 185253232 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108623271 # Number of branches executed +system.cpu0.iew.exec_stores 80882852 # Number of stores executed +system.cpu0.iew.exec_rate 0.842374 # Inst execution rate +system.cpu0.iew.wb_sent 571363680 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 570140930 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 281574536 # num instructions producing a value +system.cpu0.iew.wb_consumers 488934383 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.850630 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575475 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.821619 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575894 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 77341674 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15306476 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4267486 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 635759269 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.833165 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.828636 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 78652927 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14583855 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4341813 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 651404193 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.808420 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.807572 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 440698390 69.32% 69.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 96997007 15.26% 84.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32966862 5.19% 89.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15106149 2.38% 92.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10791866 1.70% 93.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6453132 1.02% 94.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6019295 0.95% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3918041 0.62% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22808527 3.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 458550730 70.39% 70.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 94732366 14.54% 84.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33042086 5.07% 90.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15126484 2.32% 92.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10907840 1.67% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6532170 1.00% 95.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6050361 0.93% 95.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3879708 0.60% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22582448 3.47% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 635759269 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450546917 # Number of instructions committed -system.cpu0.commit.committedOps 529692575 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 651404193 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448281871 # Number of instructions committed +system.cpu0.commit.committedOps 526607906 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 161504698 # Number of memory references committed -system.cpu0.commit.loads 84450835 # Number of loads committed -system.cpu0.commit.membars 3736231 # Number of memory barriers committed -system.cpu0.commit.branches 100681556 # Number of branches committed -system.cpu0.commit.fp_insts 429176 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 486199452 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13322938 # Number of function calls committed. +system.cpu0.commit.refs 160623494 # Number of memory references committed +system.cpu0.commit.loads 84307308 # Number of loads committed +system.cpu0.commit.membars 3712250 # Number of memory barriers committed +system.cpu0.commit.branches 100326253 # Number of branches committed +system.cpu0.commit.fp_insts 425629 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 483420006 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13315515 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 366991615 69.28% 69.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1098704 0.21% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48820 0.01% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 48738 0.01% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84450835 15.94% 85.45% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77053863 14.55% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 364753410 69.26% 69.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1133090 0.22% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 49128 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 48742 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84307308 16.01% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 76316186 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 529692575 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22808527 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1215947592 # The number of ROB reads -system.cpu0.rob.rob_writes 1227300023 # The number of ROB writes -system.cpu0.timesIdled 4042817 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23865334 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 48376378387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 450546917 # Number of Instructions Simulated -system.cpu0.committedOps 529692575 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.493380 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.493380 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.669622 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.669622 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 692384326 # number of integer regfile reads -system.cpu0.int_regfile_writes 408324633 # number of integer regfile writes -system.cpu0.fp_regfile_reads 809160 # number of floating regfile reads -system.cpu0.fp_regfile_writes 477572 # number of floating regfile writes -system.cpu0.cc_regfile_reads 126161613 # number of cc regfile reads -system.cpu0.cc_regfile_writes 127342866 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1198291262 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15447790 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10676503 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983474 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304546323 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10677015 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.523545 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1659069500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 293.453166 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 218.530308 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.573151 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.426817 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 526607906 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22582448 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1230128311 # The number of ROB reads +system.cpu0.rob.rob_writes 1223973004 # The number of ROB writes +system.cpu0.timesIdled 4124129 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 29088448 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 48650709972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 448281871 # Number of Instructions Simulated +system.cpu0.committedOps 526607906 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.547964 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.547964 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.646010 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.646010 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 689327095 # number of integer regfile reads +system.cpu0.int_regfile_writes 407367655 # number of integer regfile writes +system.cpu0.fp_regfile_reads 801695 # number of floating regfile reads +system.cpu0.fp_regfile_writes 483656 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125240184 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126404355 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1208337968 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14686021 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10424389 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.972987 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 299585117 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10424901 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.737454 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 307.327232 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 204.645755 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.600249 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.399699 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1344556090 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1344556090 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79999086 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80528903 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 160527989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67561475 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67996777 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135558252 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 203785 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202222 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 406007 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172640 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153185 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 325825 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1797141 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1773094 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3570235 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2068264 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2042534 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4110798 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147560561 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 148525680 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296086241 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147764346 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 148727902 # number of overall hits -system.cpu0.dcache.overall_hits::total 296492248 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6141795 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6528764 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12670559 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6608479 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6465845 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13074324 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649478 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 677361 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1326839 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 635249 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 605487 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1240736 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 328601 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 329591 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 658192 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 12750274 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 12994609 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 25744883 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13399752 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13671970 # number of overall misses -system.cpu0.dcache.overall_misses::total 27071722 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 94431381500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 100570450000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 195001831500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 229012929937 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 223645956318 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 452658886255 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 33967464475 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 32913724847 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 66881189322 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4162185500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4276509000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 8438694500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 161500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 108000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 269500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 323444311437 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 324216406318 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 647660717755 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 323444311437 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 324216406318 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 647660717755 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86140881 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 87057667 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 173198548 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74169954 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 74462622 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 148632576 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853263 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 879583 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1732846 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 807889 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 758672 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1566561 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2125742 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2102685 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4228427 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2068271 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2042537 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4110808 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160310835 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 161520289 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 321831124 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161164098 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 162399872 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 323563970 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071299 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074994 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073156 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089099 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086833 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087964 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761170 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.770093 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765699 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.786307 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.798088 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792013 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154582 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156748 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.155659 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.tags.tag_accesses 1321394222 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1321394222 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79981443 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78050702 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 158032145 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67196950 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 66097721 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 133294671 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207918 # 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average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15390.152202 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34654.408365 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34588.821155 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34621.972521 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53471.102631 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 54359.094162 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53904.448103 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12666.381113 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12975.199566 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12821.022589 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38710304225 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 78413601977 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10229018500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12106764000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22335782500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 33180093475 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 32187853347 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65367946822 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1698558000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1735409000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3433967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 154500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 105000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 259500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83577052752 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83973988225 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 167551040977 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 93806071252 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96080752225 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 189886823477 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2986588500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2854625000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841213500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2919463491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2774139500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5693602991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5906051991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5628764500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11534816491 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033450 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033139 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014914 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014772 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750542 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752100 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751333 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.781736 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.793751 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787555 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059340 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059791 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.writebacks::writebacks 7991214 # number of writebacks +system.cpu0.dcache.writebacks::total 7991214 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3464471 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3351244 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6815715 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5224362 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5266759 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10491121 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3656 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3377 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 7033 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 205182 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 192160 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 397342 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8688833 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8618003 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17306836 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8688833 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8618003 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17306836 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2836641 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2767999 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5604640 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1065392 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1062052 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2127444 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 627345 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 629314 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1256659 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 608557 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 622046 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1230603 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 121912 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 251270 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3902033 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3830051 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7732084 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4529378 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4459365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8988743 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16634 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33679 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15429 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18268 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32063 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35313 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67376 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995248000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 48172731500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98167979500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 49660180532 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 49261074515 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 98921255047 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12282644500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12531175500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24813820000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 43753423358 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 45991136239 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89744559597 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1882000000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1743297500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3625297500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 146500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 171500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 318000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99655428532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97433806015 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197089234547 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111938073032 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 109964981515 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 221903054547 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2842965000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2999163000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5842128000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2733695000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3088704498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5822399498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5576660000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6087867498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11664527498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032876 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032886 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032881 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014498 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014664 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.740085 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754301 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747137 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.767823 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.808140 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787686 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061871 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024539 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024774 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024657 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028382 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028713 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028548 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15516.323636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15543.345785 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15530.033638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35891.446660 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35534.057006 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35714.120698 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15972.608954 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18301.045751 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17155.716759 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52537.056848 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 53450.703585 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52983.009421 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13465.443706 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13699.155352 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13582.548196 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22071.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21245.925751 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20985.732335 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21114.719316 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20507.636360 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20604.860338 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20556.715733 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174858.811475 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172006.808870 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173453.305024 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161180.560426 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178034.879990 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168974.714082 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167818.941011 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174925.865498 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171213.378026 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024423 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024458 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024440 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028200 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028326 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028262 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17624.806241 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17403.449748 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17515.483510 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46612.120733 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46382.921472 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46497.701019 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19578.771649 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19912.437194 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19745.865824 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71897.001198 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 73935.265622 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72927.304417 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14548.771626 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14299.638264 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14427.896287 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24416.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21437.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22714.285714 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25539.360772 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25439.297287 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25489.794801 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24713.784770 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24659.336366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24686.772616 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170912.889263 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175955.588149 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173465.007868 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177179.013546 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169077.320889 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172786.880078 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173928.203849 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172397.346530 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173125.853390 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16087139 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.947221 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 170921783 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16087651 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.624409 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 16333976500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.838488 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.108732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.538747 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.461150 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999897 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 15972029 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921299 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 168505999 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15972541 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.549730 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 23717372500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 278.025579 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 233.895720 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.543019 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.456828 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 204325556 # 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number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 15972656 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8109390 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 7863266 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 15972656 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103682474880 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 99950191908 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 203632666788 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103682474880 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 99950191908 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 203632666788 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103682474880 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 99950191908 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 203632666788 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960778000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636240000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960778000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636240000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086012 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086012 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086012 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.829424 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132090219 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89757318 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5756723 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89315962 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 64542834 # Number of BTB hits +system.cpu1.branchPred.lookups 127789270 # Number of BP lookups +system.cpu1.branchPred.condPredicted 86858303 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5584682 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87369575 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62601289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.263493 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17132912 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 188342 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.651131 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16643705 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 184713 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1381,87 +1394,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 899065 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 899065 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16912 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92517 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 553507 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 345558 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2400.667905 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13912.564680 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 343096 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1764 0.51% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 399 0.12% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 345558 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 421889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22499.157361 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18375.438889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16484.116423 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 412836 97.85% 97.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8131 1.93% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 432 0.10% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 347 0.08% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 421889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 324784285420 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.056472 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.661085 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 323808973920 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 531761500 0.16% 99.86% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 194206000 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 116904000 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 46719500 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26039000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 24606500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 29193500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5603500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 17000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 324784285420 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92517 84.55% 84.55% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16912 15.45% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 109429 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 899065 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 886728 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 886728 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16477 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90200 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 549590 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 337138 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2560.840071 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15205.071993 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 334698 99.28% 99.28% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1295 0.38% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 786 0.23% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 134 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 132 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 337138 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 413502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23222.124681 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18719.794007 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19687.471539 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 404370 97.79% 97.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6829 1.65% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1627 0.39% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 122 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 359 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 93 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 61 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 23 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 16 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 413502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 343450342184 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.162233 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.725616 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 342433135184 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 558046000 0.16% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 195137000 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 122093500 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 46703500 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 26952500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 27089500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 34276500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6435000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 311500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 102500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 19500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 38500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 343450342184 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 90201 84.55% 84.55% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16477 15.45% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 106678 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886728 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 899065 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109429 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886728 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106678 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109429 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1008494 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106678 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 993406 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105725858 # DTB read hits -system.cpu1.dtb.read_misses 617527 # DTB read misses -system.cpu1.dtb.write_hits 81869169 # DTB write hits -system.cpu1.dtb.write_misses 281538 # DTB write misses -system.cpu1.dtb.flush_tlb 1084 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 101925383 # DTB read hits +system.cpu1.dtb.read_misses 607794 # DTB read misses +system.cpu1.dtb.write_hits 79659263 # DTB write hits +system.cpu1.dtb.write_misses 278934 # DTB write misses +system.cpu1.dtb.flush_tlb 1096 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55091 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8923 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54027 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 180 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8646 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 57008 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106343385 # DTB read accesses -system.cpu1.dtb.write_accesses 82150707 # DTB write accesses +system.cpu1.dtb.perms_faults 55500 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 102533177 # DTB read accesses +system.cpu1.dtb.write_accesses 79938197 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 187595027 # DTB hits -system.cpu1.dtb.misses 899065 # DTB misses -system.cpu1.dtb.accesses 188494092 # DTB accesses +system.cpu1.dtb.hits 181584646 # DTB hits +system.cpu1.dtb.misses 886728 # DTB misses +system.cpu1.dtb.accesses 182471374 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1491,340 +1505,333 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 107064 # Table walker walks requested -system.cpu1.itb.walker.walksLong 107064 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3059 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 73056 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14602 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 92462 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1594.287383 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9428.868117 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 91539 99.00% 99.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 493 0.53% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 272 0.29% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 87 0.09% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 28 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 92462 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28181.123714 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24098.190167 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18325.203286 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 49691 54.78% 54.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 38968 42.96% 97.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 889 0.98% 98.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 845 0.93% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.12% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 103 0.11% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 30 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 24 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 612488746252 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.881369 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.323767 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 72732513396 11.87% 11.87% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 539691898856 88.11% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 57837000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5354000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 885500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 253500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 612488746252 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 73056 95.98% 95.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3059 4.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 76115 # Table walker page sizes translated +system.cpu1.itb.walker.walks 104027 # Table walker walks requested +system.cpu1.itb.walker.walksLong 104027 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2965 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70858 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14434 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 89593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1868.019823 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12006.495125 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 88555 98.84% 98.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 538 0.60% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 104 0.12% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 108 0.12% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 209 0.23% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 38 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 89593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 88257 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29154.191735 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24307.950547 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 23207.189467 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 86230 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 592 0.67% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1228 1.39% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 107 0.12% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 88257 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 296203153428 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.803727 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -237987293372 -80.35% -80.35% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 534122343800 180.32% 99.98% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 59128000 0.02% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 7492500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 1022500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 250000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 210000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 296203153428 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 70858 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2965 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 73823 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 107064 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 107064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104027 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104027 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 76115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 76115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 183179 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 94801988 # ITB inst hits -system.cpu1.itb.inst_misses 107064 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73823 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73823 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 177850 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 91745725 # ITB inst hits +system.cpu1.itb.inst_misses 104027 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1084 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1096 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40979 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40011 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 204318 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204194 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 94909052 # ITB inst accesses -system.cpu1.itb.hits 94801988 # DTB hits -system.cpu1.itb.misses 107064 # DTB misses -system.cpu1.itb.accesses 94909052 # DTB accesses -system.cpu1.numCycles 671476106 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 91849752 # ITB inst accesses +system.cpu1.itb.hits 91745725 # DTB hits +system.cpu1.itb.misses 104027 # DTB misses +system.cpu1.itb.accesses 91849752 # DTB accesses +system.cpu1.numCycles 682447871 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 245366519 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 588017734 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132090219 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81675746 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 387641424 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13138102 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2647355 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 22361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4505 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5327205 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 166052 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2673 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 94574767 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3547562 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 42774 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647746875 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.062629 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.311059 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 237751767 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569981698 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 127789270 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 79244994 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 403874148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12747214 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2621326 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 5452 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5355964 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 162889 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2912 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 91518882 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3441613 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41515 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 656170682 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.017476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.271778 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 502555880 77.59% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18134910 2.80% 80.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18417584 2.84% 83.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13370411 2.06% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28474947 4.40% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9035668 1.39% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9746929 1.50% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8410613 1.30% 93.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39599933 6.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 515442690 78.55% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 17560626 2.68% 81.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 17609646 2.68% 83.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13074345 1.99% 85.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 27836031 4.24% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8626345 1.31% 91.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9437454 1.44% 92.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8134103 1.24% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 38449442 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647746875 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.196716 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.875709 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 199564404 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 323792643 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105578746 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13636228 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5172543 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19679879 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1416500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 642218643 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4358994 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5172543 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 207175837 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 26230498 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 253904637 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 111453983 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 43806880 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 627356682 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 88872 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2222363 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1667701 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24272659 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3825 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 600705753 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 967034808 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 741797210 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 803110 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 507019119 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 93686634 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15251472 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13261267 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76352353 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101066741 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86034098 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13578571 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14575923 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 595450227 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15308226 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 597111513 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 840860 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 78779365 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 50277835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 362203 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647746875 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.921828 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.648992 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 656170682 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.187251 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.835202 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 193456459 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 342166734 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 102287783 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13239744 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5017523 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18910299 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1375576 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 622643781 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4236982 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5017523 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 200842686 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 30883178 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 258887608 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 108004065 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 52532870 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 608141114 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 110721 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2023681 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1854971 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 33287436 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3642 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 582179449 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 939040277 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 719307421 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 813140 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 491677026 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 90502418 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15019602 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13109435 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 74431382 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 97738010 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 83701683 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13087583 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14003001 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 577050532 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15100250 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 578680532 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 823139 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76206595 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 48603059 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352691 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 656170682 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.881905 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.622817 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 413645402 63.86% 63.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 98786426 15.25% 79.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43350634 6.69% 85.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30948406 4.78% 90.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23128317 3.57% 94.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16110243 2.49% 96.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11031117 1.70% 98.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6443224 0.99% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4303106 0.66% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 428729858 65.34% 65.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 96527772 14.71% 80.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 41990375 6.40% 86.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 29917551 4.56% 91.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 22305055 3.40% 94.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15606448 2.38% 96.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10670315 1.63% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6241457 0.95% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4181851 0.64% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647746875 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 656170682 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3034292 25.34% 25.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25435 0.21% 25.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2765 0.02% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4931574 41.19% 66.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3978849 33.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2907149 25.23% 25.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25340 0.22% 25.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2712 0.02% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4700245 40.79% 66.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3886684 33.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 52 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 404756244 67.79% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1480116 0.25% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67236 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 53 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 2 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 71191 0.01% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107813613 18.06% 86.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82922942 13.89% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 392511580 67.83% 67.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1384098 0.24% 68.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66455 0.01% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 76 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 5 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 71678 0.01% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 103950145 17.96% 86.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 80696483 13.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 597111513 # Type of FU issued -system.cpu1.iq.rate 0.889252 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11972916 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020051 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1853695544 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 689699314 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 575118751 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1088133 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 538121 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 485191 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 608503665 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 580712 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4698016 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 578680532 # Type of FU issued +system.cpu1.iq.rate 0.847948 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11522132 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019911 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1824781458 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 668482518 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 557668794 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1095559 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 542505 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 489305 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 589617138 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 585515 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4580122 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15955461 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 21531 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 710912 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8765717 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15421998 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 21561 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 678629 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8522052 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3921205 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8400525 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3766919 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7862357 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5172543 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14653668 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 9919586 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 610892135 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1742457 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101066741 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86034098 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12972500 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 236911 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9594506 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 710912 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2600980 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2287673 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4888653 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 590524927 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105716307 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5700612 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5017523 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16098124 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12731672 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 592283961 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1683866 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 97738010 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 83701683 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12822867 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 226624 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 12419238 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 678629 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2534874 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2203490 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4738364 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 572262856 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 101914202 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5543088 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 133682 # number of nop insts executed -system.cpu1.iew.exec_refs 187585376 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109412564 # Number of branches executed -system.cpu1.iew.exec_stores 81869069 # Number of stores executed -system.cpu1.iew.exec_rate 0.879443 # Inst execution rate -system.cpu1.iew.wb_sent 576824246 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 575603942 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 284399442 # num instructions producing a value -system.cpu1.iew.wb_consumers 494076723 # num instructions consuming a value +system.cpu1.iew.exec_nop 133179 # number of nop insts executed +system.cpu1.iew.exec_refs 181576481 # number of memory reference insts executed +system.cpu1.iew.exec_branches 105801109 # Number of branches executed +system.cpu1.iew.exec_stores 79662279 # Number of stores executed +system.cpu1.iew.exec_rate 0.838544 # Inst execution rate +system.cpu1.iew.wb_sent 559345130 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 558158099 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 275625677 # num instructions producing a value +system.cpu1.iew.wb_consumers 478553206 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.857222 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575618 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.817877 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575956 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 78818099 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14946023 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4359945 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 634288153 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.838703 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.835068 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 76251521 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14747559 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4228324 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 643144454 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.802221 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.802123 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 439406713 69.28% 69.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 96089140 15.15% 84.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33004326 5.20% 89.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15342101 2.42% 92.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10933751 1.72% 93.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6607641 1.04% 94.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6115019 0.96% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3924026 0.62% 96.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22865436 3.60% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 453619473 70.53% 70.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 93903191 14.60% 85.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 31983690 4.97% 90.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 14866669 2.31% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10513323 1.63% 94.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6352313 0.99% 95.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5895751 0.92% 95.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3796111 0.59% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22213933 3.45% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 634288153 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 452878140 # Number of instructions committed -system.cpu1.commit.committedOps 531979088 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 643144454 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 438937419 # Number of instructions committed +system.cpu1.commit.committedOps 515944182 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 162379661 # Number of memory references committed -system.cpu1.commit.loads 85111280 # Number of loads committed -system.cpu1.commit.membars 3699604 # Number of memory barriers committed -system.cpu1.commit.branches 101084293 # Number of branches committed -system.cpu1.commit.fp_insts 466365 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 488261253 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13274874 # Number of function calls committed. +system.cpu1.commit.refs 157495642 # Number of memory references committed +system.cpu1.commit.loads 82316011 # Number of loads committed +system.cpu1.commit.membars 3580111 # Number of memory barriers committed +system.cpu1.commit.branches 97766699 # Number of branches committed +system.cpu1.commit.fp_insts 469643 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 473710297 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12866382 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 368350296 69.24% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1137362 0.21% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50458 0.01% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 357259636 69.24% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1077544 0.21% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49642 0.01% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction @@ -1842,42 +1849,42 @@ system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.46% # system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 61269 0.01% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85111280 16.00% 85.48% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77268381 14.52% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 61718 0.01% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82316011 15.95% 85.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75179631 14.57% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 531979088 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22865436 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1218285123 # The number of ROB reads -system.cpu1.rob.rob_writes 1235075441 # The number of ROB writes -system.cpu1.timesIdled 4119845 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23729231 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52762738169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 452878140 # Number of Instructions Simulated -system.cpu1.committedOps 531979088 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.482686 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.482686 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.674452 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.674452 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 696400049 # number of integer regfile reads -system.cpu1.int_regfile_writes 410875535 # number of integer regfile writes -system.cpu1.fp_regfile_reads 865968 # number of floating regfile reads -system.cpu1.fp_regfile_writes 525416 # number of floating regfile writes -system.cpu1.cc_regfile_reads 127021368 # number of cc regfile reads -system.cpu1.cc_regfile_writes 128126601 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1197743929 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15078416 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40301 # Transaction distribution -system.iobus.trans_dist::ReadResp 40301 # Transaction distribution +system.cpu1.commit.op_class_0::total 515944182 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22213933 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1209227164 # The number of ROB reads +system.cpu1.rob.rob_writes 1197436777 # The number of ROB writes +system.cpu1.timesIdled 3994160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 26277189 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 52630560458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 438937419 # Number of Instructions Simulated +system.cpu1.committedOps 515944182 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.554773 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.554773 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.643181 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.643181 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 675192691 # number of integer regfile reads +system.cpu1.int_regfile_writes 398302134 # number of integer regfile writes +system.cpu1.fp_regfile_reads 877858 # number of floating regfile reads +system.cpu1.fp_regfile_writes 519852 # number of floating regfile writes +system.cpu1.cc_regfile_reads 122926890 # number of cc regfile reads +system.cpu1.cc_regfile_writes 124034847 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1190535376 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14866281 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1896,11 +1903,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1917,11 +1924,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1950,71 +1957,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568866585 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565947735 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147720000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115461 # number of replacements -system.iocache.tags.tagsinuse 10.416117 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.423099 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13093305735000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.549567 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.866551 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221848 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429159 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651007 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13100950743000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.543553 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879545 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221472 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429972 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039677 # Number of tag accesses -system.iocache.tags.data_accesses 1039677 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses -system.iocache.demand_misses::total 8856 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8816 # number of overall misses -system.iocache.overall_misses::total 8856 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629394165 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1634463165 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1678499822 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1683584822 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12612717420 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12612717420 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1629394165 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1634814165 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1629394165 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1634814165 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13828150913 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13828150913 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1678499822 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1683935822 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1678499822 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1683935822 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2028,55 +2035,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184822.387137 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184622.519485 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137432.432432 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190478.872220 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190257.071081 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118247.181992 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118247.181992 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184599.612127 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184599.612127 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31652 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129642.155863 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129642.155863 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135900 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 190478.872220 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190232.243787 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135900 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 190478.872220 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190232.243787 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34183 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.451179 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.800172 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188594165 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1191813165 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237899822 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1241134822 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279517420 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7279517420 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1188594165 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1192014165 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1188594165 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1192014165 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8494950913 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8494950913 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1237899822 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1241335822 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1237899822 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1241335822 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2090,309 +2097,308 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134822.387137 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134622.519485 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87432.432432 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140478.872220 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140257.071081 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68247.181992 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.181992 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79642.155863 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79642.155863 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85900 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 140478.872220 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140232.243787 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85900 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 140478.872220 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140232.243787 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1414414 # number of replacements -system.l2c.tags.tagsinuse 65287.875921 # Cycle average of tags in use -system.l2c.tags.total_refs 50028752 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1477251 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 33.866115 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 15277469000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35504.413846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 175.319867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 252.399214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3604.019001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8668.612883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 168.198781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 249.035174 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3764.497441 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 12901.379713 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.541754 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003851 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.132273 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003800 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.057442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.196859 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996214 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 266 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62571 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2814 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5105 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54035 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004059 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.954758 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 445125308 # Number of tag accesses -system.l2c.tags.data_accesses 445125308 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 529471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 186836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 532880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 194253 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443440 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8163245 # number of Writeback hits -system.l2c.Writeback_hits::total 8163245 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 5159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4935 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10094 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 802127 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 795144 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1597271 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7936245 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 8056010 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15992255 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3437949 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3523138 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6961087 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 361682 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 352463 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 714145 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 529471 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 186836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7936245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4240076 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 532880 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 194253 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8056010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4318282 # number of demand (read+write) hits -system.l2c.demand_hits::total 25994053 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 529471 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 186836 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7936245 # number of overall hits -system.l2c.overall_hits::cpu0.data 4240076 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 532880 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 194253 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8056010 # number of overall hits -system.l2c.overall_hits::cpu1.data 4318282 # number of overall hits -system.l2c.overall_hits::total 25994053 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2596 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2347 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2527 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2344 # number of ReadReq misses -system.l2c.ReadReq_misses::total 9814 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18684 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17988 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36672 # number of UpgradeReq misses +system.l2c.tags.replacements 1325572 # number of replacements +system.l2c.tags.tagsinuse 65300.626435 # Cycle average of tags in use +system.l2c.tags.total_refs 49426863 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1388345 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 35.601283 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 22417690500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35099.515174 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 181.714209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 264.901724 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3752.412980 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11620.218077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 175.372061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 249.085946 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3742.787723 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10214.618542 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.535576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.177310 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002676 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003801 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.057110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.155863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996408 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62464 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 305 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 528 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2753 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54000 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 438866823 # Number of tag accesses +system.l2c.tags.data_accesses 438866823 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 522786 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 189596 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 519108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 186433 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1417923 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7991214 # number of Writeback hits +system.l2c.Writeback_hits::total 7991214 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 5012 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4909 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9921 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 792043 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 793357 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1585400 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 8059683 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7819802 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 15879485 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3433496 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3365802 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6799298 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 362601 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 360924 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 723525 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 522786 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 189596 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 8059683 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4225539 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 519108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 186433 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7819802 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4159159 # number of demand (read+write) hits +system.l2c.demand_hits::total 25682106 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 522786 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 189596 # number of overall hits +system.l2c.overall_hits::cpu0.inst 8059683 # number of overall hits +system.l2c.overall_hits::cpu0.data 4225539 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 519108 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 186433 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7819802 # number of overall hits +system.l2c.overall_hits::cpu1.data 4159159 # number of overall hits +system.l2c.overall_hits::total 25682106 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2462 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2334 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2152 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1980 # number of ReadReq misses +system.l2c.ReadReq_misses::total 8928 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17966 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 17816 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35782 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 286935 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 277647 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 564582 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 46865 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 48510 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 95375 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 149491 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 170842 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 320333 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 269874 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 249734 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 519608 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2596 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 46865 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 436426 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2527 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2344 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 448489 # number of demand (read+write) misses -system.l2c.demand_misses::total 990104 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2596 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2347 # number of overall misses -system.l2c.overall_misses::cpu0.inst 46865 # number of overall misses -system.l2c.overall_misses::cpu0.data 436426 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2527 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2344 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48510 # number of overall misses -system.l2c.overall_misses::cpu1.data 448489 # number of overall misses -system.l2c.overall_misses::total 990104 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 78672.902961 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20744.594252 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20747.192573 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20745.868755 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781878 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.782925 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.404163 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.419779 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.412057 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012020 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.088489 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010339 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005517 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.087611 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034271 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012020 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.088489 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010339 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005517 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.087611 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034271 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 128150.576532 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70748.163197 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70745.790245 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.981695 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90230.134002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90394.673812 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 90311.050476 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75035.324452 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79308.892100 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81323.971199 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80383.585016 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 92550.482818 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97569.105528 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94962.533294 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162358.723653 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159506.658231 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123330.363042 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149593.744824 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166534.109870 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157427.689568 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155788.892678 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162909.658773 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 136384.520105 # average overall mshr uncacheable latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138920.246068 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140077.093490 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 139493.209164 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125277.701278 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130466.805614 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130386.476885 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130427.446037 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145761.630129 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145165.577776 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145454.690403 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158412.829145 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163455.588149 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142425.163332 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165677.684879 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157491.460477 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161239.724605 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161908.742164 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160370.246085 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149627.843017 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54316 # Transaction distribution -system.membus.trans_dist::ReadResp 488581 # Transaction distribution -system.membus.trans_dist::WriteReq 33695 # Transaction distribution -system.membus.trans_dist::WriteResp 33695 # Transaction distribution -system.membus.trans_dist::Writeback 1300231 # Transaction distribution -system.membus.trans_dist::CleanEvict 226932 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37530 # Transaction distribution +system.membus.trans_dist::ReadReq 54325 # Transaction distribution +system.membus.trans_dist::ReadResp 466014 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::Writeback 1223851 # Transaction distribution +system.membus.trans_dist::CleanEvict 214858 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36602 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37532 # Transaction distribution -system.membus.trans_dist::ReadExReq 1083335 # Transaction distribution -system.membus.trans_dist::ReadExResp 1083335 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 434265 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36604 # Transaction distribution +system.membus.trans_dist::ReadExReq 1014814 # Transaction distribution +system.membus.trans_dist::ReadExResp 1014814 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 411689 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4552687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4682321 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5023611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6862 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4279818 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4409460 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4751501 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174247596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174419346 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7230976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7230976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 181650322 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3166 # Total snoops (count) -system.membus.snoop_fanout::samples 3279708 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163529836 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 163701542 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7254464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7254464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 170956006 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2794 # Total snoops (count) +system.membus.snoop_fanout::samples 3098842 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3279708 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3098842 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3279708 # Request fanout histogram -system.membus.reqLayer0.occupancy 114259000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3098842 # Request fanout histogram +system.membus.reqLayer0.occupancy 114250999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5427500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5591500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8793071023 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8287460048 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8222412889 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7742269755 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228888550 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228310464 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2743,57 +2752,63 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 2064834 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25434780 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33695 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33695 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 9463502 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 18825810 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46769 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46779 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2161853 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2161853 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16087782 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7290273 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1340417 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1233753 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48300519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32258677 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 920526 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2543246 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 84022968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1030929280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1127055058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3086240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8539792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2169610370 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2203584 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 57319196 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.063782 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.244364 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 53652655 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27255089 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4361 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2133 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 2023578 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25097341 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 9215084 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 18618130 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45706 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45720 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2093953 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2093953 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15972656 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7109207 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1337267 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1230603 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47955066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31500258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 906342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2489762 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 82851428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1023557760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1100111846 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8372064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2135084414 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2099930 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 56453563 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.014593 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.119915 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 53663256 93.62% 93.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 3655940 6.38% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 55629759 98.54% 98.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 823804 1.46% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 57319196 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 36016999461 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 56453563 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 35456582958 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1117500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1421406 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24175146802 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24004091061 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14858261870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14485026242 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 535144651 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 526450560 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1478603615 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1445956414 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 19287 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 19211 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 0c2ce6f33..15c6a98da 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.832615 # Number of seconds simulated -sim_ticks 51832614542500 # Number of ticks simulated -final_tick 51832614542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811486 # Number of seconds simulated +sim_ticks 51811486345500 # Number of ticks simulated +final_tick 51811486345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536275 # Simulator instruction rate (inst/s) -host_op_rate 630162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31538205227 # Simulator tick rate (ticks/s) -host_mem_usage 713092 # Number of bytes of host memory used -host_seconds 1643.49 # Real time elapsed on the host -sim_insts 881360160 # Number of instructions simulated -sim_ops 1035663034 # Number of ops (including micro ops) simulated +host_inst_rate 646354 # Simulator instruction rate (inst/s) +host_op_rate 759580 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40519578786 # Simulator tick rate (ticks/s) +host_mem_usage 722184 # Number of bytes of host memory used +host_seconds 1278.68 # Real time elapsed on the host +sim_insts 826478524 # Number of instructions simulated +sim_ops 971257944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 134080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2944516 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40297840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 118912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 116992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2475952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 40549336 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 378752 # Number of bytes read from this memory -system.physmem.bytes_read::total 87146876 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2944516 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2475952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5420468 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75611328 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 75631908 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 70534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 629657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 54568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 633593 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5918 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1402090 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1181427 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1184000 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 56808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 777461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 782313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1681314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 56808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 104576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1458760 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1459157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1458760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 56808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 777461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 782710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3140470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1402090 # Number of read requests accepted -system.physmem.writeReqs 1184000 # Number of write requests accepted -system.physmem.readBursts 1402090 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1184000 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 89692096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 41664 # Total number of bytes read from write queue -system.physmem.bytesWritten 75632192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 87146876 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75631908 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 651 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 142152 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 86151 # Per bank write bursts -system.physmem.perBankRdBursts::1 87375 # Per bank write bursts -system.physmem.perBankRdBursts::2 80357 # Per bank write bursts -system.physmem.perBankRdBursts::3 81721 # Per bank write bursts -system.physmem.perBankRdBursts::4 87059 # Per bank write bursts -system.physmem.perBankRdBursts::5 94652 # Per bank write bursts -system.physmem.perBankRdBursts::6 87531 # Per bank write bursts -system.physmem.perBankRdBursts::7 83073 # Per bank write bursts -system.physmem.perBankRdBursts::8 80243 # Per bank write bursts -system.physmem.perBankRdBursts::9 128909 # Per bank write bursts -system.physmem.perBankRdBursts::10 86457 # Per bank write bursts -system.physmem.perBankRdBursts::11 85414 # Per bank write bursts -system.physmem.perBankRdBursts::12 83586 # Per bank write bursts -system.physmem.perBankRdBursts::13 88109 # Per bank write bursts -system.physmem.perBankRdBursts::14 80365 # Per bank write bursts -system.physmem.perBankRdBursts::15 80437 # Per bank write bursts -system.physmem.perBankWrBursts::0 72704 # Per bank write bursts -system.physmem.perBankWrBursts::1 74469 # Per bank write bursts -system.physmem.perBankWrBursts::2 70529 # Per bank write bursts -system.physmem.perBankWrBursts::3 72860 # Per bank write bursts -system.physmem.perBankWrBursts::4 75808 # Per bank write bursts -system.physmem.perBankWrBursts::5 80444 # Per bank write bursts -system.physmem.perBankWrBursts::6 76110 # Per bank write bursts -system.physmem.perBankWrBursts::7 73633 # Per bank write bursts -system.physmem.perBankWrBursts::8 70562 # Per bank write bursts -system.physmem.perBankWrBursts::9 76081 # Per bank write bursts -system.physmem.perBankWrBursts::10 73660 # Per bank write bursts -system.physmem.perBankWrBursts::11 73767 # Per bank write bursts -system.physmem.perBankWrBursts::12 72713 # Per bank write bursts -system.physmem.perBankWrBursts::13 77059 # Per bank write bursts -system.physmem.perBankWrBursts::14 70231 # Per bank write bursts -system.physmem.perBankWrBursts::15 71123 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 67136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 69696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2388444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 32434992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 59968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 68096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2361560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 31996376 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 390912 # Number of bytes read from this memory +system.physmem.bytes_read::total 69837180 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2388444 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2361560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4750004 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 60588032 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 15876 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4704 # Number of bytes written to this memory +system.physmem.bytes_written::total 60608612 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 57981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 506800 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56645 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 499953 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6108 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1131626 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 946688 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1985 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 588 # Number of write requests responded to by this memory +system.physmem.num_writes::total 949261 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 626019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 617554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1347909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1169394 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1169791 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1169394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 626326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 617645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2517700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1131626 # Number of read requests accepted +system.physmem.writeReqs 949261 # Number of write requests accepted +system.physmem.readBursts 1131626 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 949261 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72380992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43072 # Total number of bytes read from write queue +system.physmem.bytesWritten 60608832 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69837180 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 60608612 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 673 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 139894 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 75334 # Per bank write bursts +system.physmem.perBankRdBursts::1 78749 # Per bank write bursts +system.physmem.perBankRdBursts::2 69239 # Per bank write bursts +system.physmem.perBankRdBursts::3 66964 # Per bank write bursts +system.physmem.perBankRdBursts::4 64795 # Per bank write bursts +system.physmem.perBankRdBursts::5 72549 # Per bank write bursts +system.physmem.perBankRdBursts::6 64584 # Per bank write bursts +system.physmem.perBankRdBursts::7 63831 # Per bank write bursts +system.physmem.perBankRdBursts::8 65287 # Per bank write bursts +system.physmem.perBankRdBursts::9 109012 # Per bank write bursts +system.physmem.perBankRdBursts::10 67637 # Per bank write bursts +system.physmem.perBankRdBursts::11 66460 # Per bank write bursts +system.physmem.perBankRdBursts::12 64061 # Per bank write bursts +system.physmem.perBankRdBursts::13 68282 # Per bank write bursts +system.physmem.perBankRdBursts::14 66426 # Per bank write bursts +system.physmem.perBankRdBursts::15 67743 # Per bank write bursts +system.physmem.perBankWrBursts::0 61340 # Per bank write bursts +system.physmem.perBankWrBursts::1 64755 # Per bank write bursts +system.physmem.perBankWrBursts::2 59195 # Per bank write bursts +system.physmem.perBankWrBursts::3 59472 # Per bank write bursts +system.physmem.perBankWrBursts::4 56881 # Per bank write bursts +system.physmem.perBankWrBursts::5 61983 # Per bank write bursts +system.physmem.perBankWrBursts::6 56876 # Per bank write bursts +system.physmem.perBankWrBursts::7 57630 # Per bank write bursts +system.physmem.perBankWrBursts::8 57576 # Per bank write bursts +system.physmem.perBankWrBursts::9 59174 # Per bank write bursts +system.physmem.perBankWrBursts::10 59811 # Per bank write bursts +system.physmem.perBankWrBursts::11 59738 # Per bank write bursts +system.physmem.perBankWrBursts::12 56644 # Per bank write bursts +system.physmem.perBankWrBursts::13 59454 # Per bank write bursts +system.physmem.perBankWrBursts::14 57794 # Per bank write bursts +system.physmem.perBankWrBursts::15 58690 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 31 # Number of times write queue was full causing retry -system.physmem.totGap 51832611910500 # Total gap between requests +system.physmem.numWrRetry 24 # Number of times write queue was full causing retry +system.physmem.totGap 51811483663500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1358974 # Read request sizes (log2) +system.physmem.readPktSize::6 1088510 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1181427 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1369118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 946688 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1104614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,183 +165,181 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 67973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 68856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 68869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 68651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 71263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 74085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 72568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 72467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 69770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 69647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 70062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 67493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 66673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 564759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 292.733658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.256086 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.085017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 228658 40.49% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 138332 24.49% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49531 8.77% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28277 5.01% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20268 3.59% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14095 2.50% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11027 1.95% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10949 1.94% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63622 11.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 564759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 67625 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.723608 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 277.022721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 67622 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 67625 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 67625 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.475091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.957142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.452813 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 76 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 68 0.10% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 65 0.10% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 131 0.19% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 63823 94.38% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 440 0.65% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 742 1.10% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 499 0.74% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 390 0.58% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 489 0.72% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 119 0.18% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.04% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 63 0.09% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 45 0.07% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 39 0.06% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 22 0.03% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 448 0.66% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 23 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 39 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 23 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 67625 # Writes before turning the bus around for reads -system.physmem.totQLat 16718468525 # Total ticks spent queuing -system.physmem.totMemAccLat 42995449775 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7007195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11929.50 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 1575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1350 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 56694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 54836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 55477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 53687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 52944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 52255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 441668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.107402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.680008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.161317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 174892 39.60% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107627 24.37% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38708 8.76% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22457 5.08% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15602 3.53% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11601 2.63% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10181 2.31% 86.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8589 1.94% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 52011 11.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 441668 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.347484 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 294.800530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 52971 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 52978 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.875590 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.137628 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.848761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 99 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 70 0.13% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 74 0.14% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 116 0.22% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49442 93.33% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 558 1.05% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 385 0.73% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 568 1.07% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 120 0.23% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 330 0.62% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 204 0.39% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.05% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 95 0.18% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 130 0.25% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 30 0.06% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 454 0.86% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 21 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 141 0.27% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 29 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 8 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52978 # Writes before turning the bus around for reads +system.physmem.totQLat 13921987827 # Total ticks spent queuing +system.physmem.totMemAccLat 35127356577 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5654765000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12309.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30679.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31059.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.63 # Average write queue length when enqueuing -system.physmem.readRowHits 1132210 # Number of row buffer hits during reads -system.physmem.writeRowHits 886222 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes -system.physmem.avgGap 20042849.21 # Average gap between requests -system.physmem.pageHitRate 78.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2158387560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1177691625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5365768200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3865689360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313258572845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29947583060250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34658863084800 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.669107 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49819671489024 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730804660000 # Time in different power states +system.physmem.avgWrQLen 7.63 # Average write queue length when enqueuing +system.physmem.readRowHits 914287 # Number of row buffer hits during reads +system.physmem.writeRowHits 722010 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.24 # Row buffer hit rate for writes +system.physmem.avgGap 24898749.27 # Average gap between requests +system.physmem.pageHitRate 78.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1737469440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 948024000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4337112000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3098295360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1302776002665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29944103839500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34641074934645 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.598406 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49814086335255 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730099280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 282130972226 # Time in different power states +system.physmem_0.memoryStateTime::ACT 267300073745 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2111190480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1151939250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5565417000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3792070080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1310153724135 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29950306611750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34658534867655 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.662774 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49824215805224 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730804660000 # Time in different power states +system.physmem_1.actEnergy 1601540640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 873856500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4484282400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3038348880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1289689159770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29955583526250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34639344906120 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.565015 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49833230042430 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730099280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 277593670776 # Time in different power states +system.physmem_1.memoryStateTime::ACT 248153702570 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -395,65 +393,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 130428 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 130428 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20426 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94161 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 130414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 130414 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 130414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 114601 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25025.623686 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.133741 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14193.681922 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 113576 99.11% 99.11% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 877 0.77% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 64 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 23 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 116564 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 116564 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17888 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84633 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 116551 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.308878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 85.298018 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 116549 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 116551 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 102534 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24964.241130 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21649.871180 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15929.030690 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 101954 99.43% 99.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 9 0.01% 99.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 497 0.48% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 10 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 114601 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -626546628 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.597966 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.490309 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -251893296 40.20% 40.20% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -374653332 59.80% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -626546628 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94162 82.17% 82.17% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 20426 17.83% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 114588 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 102534 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -4616128984 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.375220 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1732065704 -37.52% -37.52% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -6348194688 137.52% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -4616128984 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84634 82.55% 82.55% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17888 17.45% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 102522 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116564 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130428 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114588 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116564 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102522 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114588 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 245016 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 219086 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 82615908 # DTB read hits -system.cpu0.dtb.read_misses 99897 # DTB read misses -system.cpu0.dtb.write_hits 75294881 # DTB write hits -system.cpu0.dtb.write_misses 30531 # DTB write misses -system.cpu0.dtb.flush_tlb 51838 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 77762076 # DTB read hits +system.cpu0.dtb.read_misses 89597 # DTB read misses +system.cpu0.dtb.write_hits 70744341 # DTB write hits +system.cpu0.dtb.write_misses 26967 # DTB write misses +system.cpu0.dtb.flush_tlb 51819 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 72657 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 68559 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3939 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9875 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 82715805 # DTB read accesses -system.cpu0.dtb.write_accesses 75325412 # DTB write accesses +system.cpu0.dtb.perms_faults 9342 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 77851673 # DTB read accesses +system.cpu0.dtb.write_accesses 70771308 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 157910789 # DTB hits -system.cpu0.dtb.misses 130428 # DTB misses -system.cpu0.dtb.accesses 158041217 # DTB accesses +system.cpu0.dtb.hits 148506417 # DTB hits +system.cpu0.dtb.misses 116564 # DTB misses +system.cpu0.dtb.accesses 148622981 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,280 +486,278 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 77694 # Table walker walks requested -system.cpu0.itb.walker.walksLong 77694 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4299 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67844 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 77694 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 77694 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 77694 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72143 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28108.645329 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25072.463875 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16528.773937 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70985 98.39% 98.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 998 1.38% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 60 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 53 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72143 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -294780296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -294780296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -294780296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67844 94.04% 94.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4299 5.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72143 # Table walker page sizes translated +system.cpu0.itb.walker.walks 74612 # Table walker walks requested +system.cpu0.itb.walker.walksLong 74612 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4209 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 65365 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 74612 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 74612 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74612 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69574 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28527.819300 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25311.121928 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18888.333067 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68887 99.01% 99.01% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.02% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 590 0.85% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 39 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 69574 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 65365 93.95% 93.95% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4209 6.05% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 69574 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77694 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77694 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74612 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74612 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72143 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72143 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 149837 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 440762049 # ITB inst hits -system.cpu0.itb.inst_misses 77694 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69574 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69574 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 144186 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 414226266 # ITB inst hits +system.cpu0.itb.inst_misses 74612 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51838 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51819 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53801 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 50668 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 440839743 # ITB inst accesses -system.cpu0.itb.hits 440762049 # DTB hits -system.cpu0.itb.misses 77694 # DTB misses -system.cpu0.itb.accesses 440839743 # DTB accesses -system.cpu0.numCycles 51832801454 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 414300878 # ITB inst accesses +system.cpu0.itb.hits 414226266 # DTB hits +system.cpu0.itb.misses 74612 # DTB misses +system.cpu0.itb.accesses 414300878 # DTB accesses +system.cpu0.numCycles 51812404725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 440492275 # Number of instructions committed -system.cpu0.committedOps 517776891 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 475595742 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 442272 # Number of float alu accesses -system.cpu0.num_func_calls 26261796 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 67159010 # number of instructions that are conditional controls -system.cpu0.num_int_insts 475595742 # number of integer instructions -system.cpu0.num_fp_insts 442272 # number of float instructions -system.cpu0.num_int_register_reads 692983656 # number of times the integer registers were read -system.cpu0.num_int_register_writes 377245689 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 706646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 389336 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 115273932 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 114990138 # number of times the CC registers were written -system.cpu0.num_mem_refs 157900832 # number of memory refs -system.cpu0.num_load_insts 82612008 # Number of load instructions -system.cpu0.num_store_insts 75288824 # Number of store instructions -system.cpu0.num_idle_cycles 50243492062.967224 # Number of idle cycles -system.cpu0.num_busy_cycles 1589309391.032773 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030662 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969338 # Percentage of idle cycles -system.cpu0.Branches 98397494 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 358993131 69.29% 69.29% # Class of executed instruction -system.cpu0.op_class::IntMult 1071583 0.21% 69.50% # Class of executed instruction -system.cpu0.op_class::IntDiv 48336 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 58966 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 82612008 15.95% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 75288824 14.53% 100.00% # Class of executed instruction +system.cpu0.committedInsts 413973920 # Number of instructions committed +system.cpu0.committedOps 486522682 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 447282441 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 436837 # Number of float alu accesses +system.cpu0.num_func_calls 24924968 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 62713258 # number of instructions that are conditional controls +system.cpu0.num_int_insts 447282441 # number of integer instructions +system.cpu0.num_fp_insts 436837 # number of float instructions +system.cpu0.num_int_register_reads 647714944 # number of times the integer registers were read +system.cpu0.num_int_register_writes 354553253 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 705988 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 367364 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 107220558 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 106909360 # number of times the CC registers were written +system.cpu0.num_mem_refs 148497129 # number of memory refs +system.cpu0.num_load_insts 77758052 # Number of load instructions +system.cpu0.num_store_insts 70739077 # Number of store instructions +system.cpu0.num_idle_cycles 50264604442.745827 # Number of idle cycles +system.cpu0.num_busy_cycles 1547800282.254174 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029873 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970127 # Percentage of idle cycles +system.cpu0.Branches 92346942 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 337152189 69.26% 69.26% # Class of executed instruction +system.cpu0.op_class::IntMult 1046864 0.22% 69.47% # Class of executed instruction +system.cpu0.op_class::IntDiv 47543 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53325 0.01% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::MemRead 77758052 15.97% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 70739077 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 518072849 # Class of executed instruction +system.cpu0.op_class::total 486797091 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 19145 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10037940 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305864730 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10038452 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.469312 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 221.416582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 290.549452 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.432454 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.567479 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 18838 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9220536 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 287472122 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9221048 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.175645 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 266.571154 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 245.371643 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.520647 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.479241 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999888 # 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number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150295 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 302068 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1196444585 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1196444585 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 72800073 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 72976033 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 145776106 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67163987 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 66958173 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134122160 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185807 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 184713 # 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number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 611544 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 610003 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1221547 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 143187 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139519 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 282706 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3670218 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3734625 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7404843 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4304165 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18843.090799 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18814.888974 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18829.127811 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,220 +766,216 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7725236 # number of writebacks -system.cpu0.dcache.writebacks::total 7725236 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058974 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3378673 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3344884 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 6723557 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 3948797 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 3876696 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 7825493 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33701 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16927 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 16781 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33504 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67409 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38337908500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37823855000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76161763500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31904413500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31123658000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 63028071500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10925929500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9736959500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20662889000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 35611655500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 36315467000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71927122500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1499957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1452847000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2952804000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 70242322000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 68947513000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 139189835000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81168251500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 78684472500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 159852724000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2837606500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2994256500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5831863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2838720500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2985129500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5823850000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5676327000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5979386000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11655713000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031802 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031771 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031787 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013987 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014234 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753260 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741379 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747479 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789636 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.785046 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787337 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061369 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059813 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060593 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023954 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024311 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024133 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027958 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028288 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028124 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14809.576358 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14678.665982 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14743.387000 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28191.365173 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27859.019656 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28024.876090 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15890.760284 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16368.223103 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16128.997682 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 40139.290079 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40762.418728 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 40451.654604 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13437.966462 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13246.065278 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13342.463552 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 56500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18739.896929 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18499.092011 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18618.471143 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18318.618934 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18189.651249 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18253.686890 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172235.277103 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173828.755025 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.497152 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178548.172137 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160224.592114 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168952.876087 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175275.380140 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166780.305254 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170982.036106 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023567 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023454 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027399 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026919 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027159 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16029.617735 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15793.441421 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15911.450213 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32325.256008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32762.607437 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32539.753872 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19164.128330 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18309.025558 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18751.442008 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58232.368399 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59533.259672 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58881.993489 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13700.364440 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13691.766169 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13696.132545 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20789.914265 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20612.826334 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20701.815274 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20555.184655 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20296.786877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20427.176154 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171177.324003 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174857.305536 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.179609 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167703.698234 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177887.462011 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.525573 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169422.367479 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176357.056481 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172910.338382 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13866895 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.854828 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 868036851 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13867407 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.595469 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 43293883500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 253.434107 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 258.420721 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.494988 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.504728 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13375087 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.782407 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 813613327 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13375599 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 60.828179 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 61699422500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 237.356539 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 274.425868 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.463587 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.535988 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 895771675 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 895771675 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 433832015 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 434204836 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 868036851 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 433832015 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 434204836 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 868036851 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 433832015 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 434204836 # number of overall hits -system.cpu0.icache.overall_hits::total 868036851 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6930034 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6937378 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13867412 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6930034 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6937378 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13867412 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6930034 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6937378 # number of overall misses -system.cpu0.icache.overall_misses::total 13867412 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93266994500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 92872882000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 186139876500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93266994500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 92872882000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 186139876500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93266994500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 92872882000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 186139876500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 440762049 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 441142214 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 881904263 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 440762049 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 441142214 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 881904263 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 440762049 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 441142214 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 881904263 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015723 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015726 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015724 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015723 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015726 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015724 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015723 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015726 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015724 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12422.827309 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74878.214493 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74878.214493 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84943244500 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12652.707085 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126064.289855 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126064.289855 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1071,76 +1068,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 127806 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 127806 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20371 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91874 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 127789 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.297365 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 80.104866 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 127787 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 127789 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 112262 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24820.406727 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21828.616459 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13574.434559 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 72880 64.92% 64.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 38528 34.32% 99.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 428 0.38% 99.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 314 0.28% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.00% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 36 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 8 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 22 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 112262 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 8237382924 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.971809 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.165518 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 232218204 2.82% 2.82% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 8005164720 97.18% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 8237382924 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91874 81.85% 81.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 20371 18.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 112245 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127806 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 117457 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 117457 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17877 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85465 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 117442 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.102178 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 35.016241 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 117441 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 117442 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 103357 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25041.496947 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21746.242782 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15395.142756 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 102794 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 506 0.49% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 24 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 103357 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 3996353148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.606452 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.488536 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1572755204 39.35% 39.35% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 2423597944 60.65% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 3996353148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85465 82.70% 82.70% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17877 17.30% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 103342 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117457 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127806 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112245 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117457 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103342 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112245 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 240051 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103342 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 220799 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82941587 # DTB read hits -system.cpu1.dtb.read_misses 97218 # DTB read misses -system.cpu1.dtb.write_hits 75253518 # DTB write hits -system.cpu1.dtb.write_misses 30588 # DTB write misses -system.cpu1.dtb.flush_tlb 51836 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 77889145 # DTB read hits +system.cpu1.dtb.read_misses 90593 # DTB read misses +system.cpu1.dtb.write_hits 70493756 # DTB write hits +system.cpu1.dtb.write_misses 26864 # DTB write misses +system.cpu1.dtb.flush_tlb 51813 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 71746 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 67533 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4678 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3800 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9800 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83038805 # DTB read accesses -system.cpu1.dtb.write_accesses 75284106 # DTB write accesses +system.cpu1.dtb.perms_faults 9179 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 77979738 # DTB read accesses +system.cpu1.dtb.write_accesses 70520620 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 158195105 # DTB hits -system.cpu1.dtb.misses 127806 # DTB misses -system.cpu1.dtb.accesses 158322911 # DTB accesses +system.cpu1.dtb.hits 148382901 # DTB hits +system.cpu1.dtb.misses 117457 # DTB misses +system.cpu1.dtb.accesses 148500358 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1170,131 +1159,126 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 77092 # Table walker walks requested -system.cpu1.itb.walker.walksLong 77092 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4382 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67241 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 77092 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 77092 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 77092 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71623 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28009.703587 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25156.150396 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15232.175605 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 36121 50.43% 50.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 34500 48.17% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 359 0.50% 99.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 519 0.72% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 46 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71623 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -887431296 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -887431296 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -887431296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 67241 93.88% 93.88% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4382 6.12% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71623 # Table walker page sizes translated +system.cpu1.itb.walker.walks 75165 # Table walker walks requested +system.cpu1.itb.walker.walksLong 75165 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4147 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 65764 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 75165 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 75165 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75165 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 69911 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28585.308464 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25361.717379 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18567.806598 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69206 98.99% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 615 0.88% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 69911 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1449365704 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1449365704 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1449365704 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 65764 94.07% 94.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4147 5.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 69911 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77092 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77092 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75165 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71623 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71623 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148715 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 441142214 # ITB inst hits -system.cpu1.itb.inst_misses 77092 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 145076 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 412762665 # ITB inst hits +system.cpu1.itb.inst_misses 75165 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51836 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51813 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 52225 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 50171 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 441219306 # ITB inst accesses -system.cpu1.itb.hits 441142214 # DTB hits -system.cpu1.itb.misses 77092 # DTB misses -system.cpu1.itb.accesses 441219306 # DTB accesses -system.cpu1.numCycles 51832427631 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 412837830 # ITB inst accesses +system.cpu1.itb.hits 412762665 # DTB hits +system.cpu1.itb.misses 75165 # DTB misses +system.cpu1.itb.accesses 412837830 # DTB accesses +system.cpu1.numCycles 51810567966 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 440867885 # Number of instructions committed -system.cpu1.committedOps 517886143 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 475513559 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 454227 # Number of float alu accesses -system.cpu1.num_func_calls 26111235 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67284853 # number of instructions that are conditional controls -system.cpu1.num_int_insts 475513559 # number of integer instructions -system.cpu1.num_fp_insts 454227 # number of float instructions -system.cpu1.num_int_register_reads 692532840 # number of times the integer registers were read -system.cpu1.num_int_register_writes 377153809 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 737892 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 372156 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 115804323 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 115491463 # number of times the CC registers were written -system.cpu1.num_mem_refs 158189082 # number of memory refs -system.cpu1.num_load_insts 82939410 # Number of load instructions -system.cpu1.num_store_insts 75249672 # Number of store instructions -system.cpu1.num_idle_cycles 50245805753.829796 # Number of idle cycles -system.cpu1.num_busy_cycles 1586621877.170202 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030611 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969389 # Percentage of idle cycles -system.cpu1.Branches 98435537 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 358757749 69.23% 69.23% # Class of executed instruction -system.cpu1.op_class::IntMult 1128666 0.22% 69.45% # Class of executed instruction -system.cpu1.op_class::IntDiv 49961 0.01% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 51912 0.01% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::MemRead 82939410 16.01% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 75249672 14.52% 100.00% # Class of executed instruction +system.cpu1.committedInsts 412504604 # Number of instructions committed +system.cpu1.committedOps 484735262 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 445679810 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 461935 # Number of float alu accesses +system.cpu1.num_func_calls 24743870 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 62553122 # number of instructions that are conditional controls +system.cpu1.num_int_insts 445679810 # number of integer instructions +system.cpu1.num_fp_insts 461935 # number of float instructions +system.cpu1.num_int_register_reads 643867148 # number of times the integer registers were read +system.cpu1.num_int_register_writes 353090786 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 745900 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 389388 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 106633710 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 106335348 # number of times the CC registers were written +system.cpu1.num_mem_refs 148371142 # number of memory refs +system.cpu1.num_load_insts 77883866 # Number of load instructions +system.cpu1.num_store_insts 70487276 # Number of store instructions +system.cpu1.num_idle_cycles 50277800640.138901 # Number of idle cycles +system.cpu1.num_busy_cycles 1532767325.861101 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029584 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970416 # Percentage of idle cycles +system.cpu1.Branches 92048959 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 335465896 69.17% 69.17% # Class of executed instruction +system.cpu1.op_class::IntMult 1068730 0.22% 69.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 49540 0.01% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 59074 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::MemRead 77883866 16.06% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 70487276 14.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 518177412 # Class of executed instruction +system.cpu1.op_class::total 485014384 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40326 # Transaction distribution -system.iobus.trans_dist::ReadResp 40326 # Transaction distribution +system.iobus.trans_dist::ReadReq 40322 # Transaction distribution +system.iobus.trans_dist::ReadResp 40322 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1313,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353794 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1334,11 +1318,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1367,71 +1351,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568807378 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565848755 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147770000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115487 # number of replacements -system.iocache.tags.tagsinuse 10.455201 # Cycle average of tags in use +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.447157 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115503 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13165365743000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510018 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945183 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653450 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183753622000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511463 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935694 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039902 # Number of tag accesses -system.iocache.tags.data_accesses 1039902 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8841 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8878 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8841 # number of demand (read+write) misses -system.iocache.demand_misses::total 8881 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8841 # number of overall misses -system.iocache.overall_misses::total 8881 # number of overall misses +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1579254237 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1584323237 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1638182519 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1643251519 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12612931141 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12612931141 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13826239236 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13826239236 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1579254237 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1584674237 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1638182519 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1643602519 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1579254237 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1584674237 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1638182519 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1643602519 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8841 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8878 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8841 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8881 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8841 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8881 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1446,54 +1430,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 178628.462504 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 178454.971503 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185377.675569 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185175.965630 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118249.185677 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118249.185677 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129624.233443 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129624.233443 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 178434.212026 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185152.925425 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 178434.212026 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 30353 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185152.925425 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32900 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3277 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3381 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.155316 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.064160 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.124366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995480 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 303 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61951 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2426 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5561 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53526 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004623 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.945297 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 371969368 # Number of tag accesses +system.l2c.tags.data_accesses 371969368 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 206753 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 156932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 209510 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 158543 # number of ReadReq hits +system.l2c.ReadReq_hits::total 731738 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7220092 # number of Writeback hits +system.l2c.Writeback_hits::total 7220092 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 4469 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4434 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 8903 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 808716 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 774561 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1583277 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6676988 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6627078 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13304066 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 2957591 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 2929428 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 5887019 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 375245 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 367579 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70537.296580 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70520.567486 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70529.000862 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71471.937718 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 73037.508636 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73047.399754 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73042.475457 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69043.995246 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69120.579339 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69082.783581 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159735.277103 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161328.755025 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105428.158638 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167048.172137 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148724.592114 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157452.876087 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163256.950484 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154798.415028 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 121293.301851 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.162935 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.166467 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.164666 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005348 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.037023 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034095 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.035568 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.386397 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.397414 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.391899 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005048 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.067153 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.065141 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.027357 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005048 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.067153 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.065141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.027357 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 126613.795603 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70658.373527 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70659.720091 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70659.044995 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120635.414218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120617.257853 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120626.415385 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121926.451676 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122801.012242 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122530.554911 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122672.201444 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120149.774227 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120106.268356 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120127.742975 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158677.324003 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162357.305536 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 134174.114232 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156203.698234 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166387.462011 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161273.525573 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157427.590735 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164351.998230 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 142438.240722 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76829 # Transaction distribution -system.membus.trans_dist::ReadResp 448840 # Transaction distribution -system.membus.trans_dist::WriteReq 33709 # Transaction distribution -system.membus.trans_dist::WriteResp 33709 # Transaction distribution -system.membus.trans_dist::Writeback 1181427 # Transaction distribution -system.membus.trans_dist::CleanEvict 191531 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35493 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35495 # Transaction distribution -system.membus.trans_dist::ReadExReq 990576 # Transaction distribution -system.membus.trans_dist::ReadExResp 990576 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 372011 # Transaction distribution +system.membus.trans_dist::ReadReq 76826 # Transaction distribution +system.membus.trans_dist::ReadResp 378489 # Transaction distribution +system.membus.trans_dist::WriteReq 33708 # Transaction distribution +system.membus.trans_dist::WriteResp 33708 # Transaction distribution +system.membus.trans_dist::Writeback 946688 # Transaction distribution +system.membus.trans_dist::CleanEvict 157044 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33236 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33237 # Transaction distribution +system.membus.trans_dist::ReadExReq 790266 # Transaction distribution +system.membus.trans_dist::ReadExResp 790266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 301663 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4129743 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4259441 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4599906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3314453 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3444143 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340891 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340891 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3785034 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 155575648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 155745486 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7203136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7203136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 162948622 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3620 # Total snoops (count) -system.membus.snoop_fanout::samples 2991422 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123230496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 123400318 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7215296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7215296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 130615614 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3426 # Total snoops (count) +system.membus.snoop_fanout::samples 2449027 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2991422 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2449027 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2991422 # Request fanout histogram -system.membus.reqLayer0.occupancy 107341500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2449027 # Request fanout histogram +system.membus.reqLayer0.occupancy 107350000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5250000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5290500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7710006309 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6222696821 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7440287022 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6001448560 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228944719 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228378003 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2129,54 +2104,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 1264904 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21840032 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8906693 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 16372534 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44670 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2102857 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2102857 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13867412 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6715681 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1335478 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1228814 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41686402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30339787 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 785213 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1207911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 74019313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 887686868 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1058482234 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2638496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3801896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 1952609494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1875627 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 50645688 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.052912 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.223858 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 45764335 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 23167677 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2649 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 1182601 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 20663192 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8166804 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 15533735 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 41576 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 41577 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1895383 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1895383 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13375604 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6113005 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1328211 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1221547 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40210956 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27881321 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 758327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1083325 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 69933929 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 856211156 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 974300010 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2541024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3345992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 1836398182 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1592965 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 47672379 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011257 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105498 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 47965928 94.71% 94.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 2679760 5.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 47135748 98.87% 98.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 536631 1.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 50645688 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 32319092000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 47672379 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 30462031500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1371000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1592884 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20844243000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20106531000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 13901838902 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12681402468 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 455401000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 440699000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 732674000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 665076000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 264f4c629..d26a43093 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.126140 # Number of seconds simulated -sim_ticks 5126139641000 # Number of ticks simulated -final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144266 # Number of seconds simulated +sim_ticks 5144265998000 # Number of ticks simulated +final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128755 # Simulator instruction rate (inst/s) -host_op_rate 254500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618610313 # Simulator tick rate (ticks/s) -host_mem_usage 809248 # Number of bytes of host memory used -host_seconds 3167.00 # Real time elapsed on the host -sim_insts 407767906 # Number of instructions simulated -sim_ops 806002026 # Number of ops (including micro ops) simulated +host_inst_rate 171354 # Simulator instruction rate (inst/s) +host_op_rate 338701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2161855241 # Simulator tick rate (ticks/s) +host_mem_usage 817304 # Number of bytes of host memory used +host_seconds 2379.56 # Real time elapsed on the host +sim_insts 407746267 # Number of instructions simulated +sim_ops 805959101 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory -system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory +system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184963 # Number of read requests accepted -system.physmem.writeReqs 149464 # Number of write requests accepted -system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue -system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184401 # Number of read requests accepted +system.physmem.writeReqs 148992 # Number of write requests accepted +system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue +system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12059 # Per bank write bursts -system.physmem.perBankRdBursts::1 11374 # Per bank write bursts -system.physmem.perBankRdBursts::2 11651 # Per bank write bursts -system.physmem.perBankRdBursts::3 11200 # Per bank write bursts -system.physmem.perBankRdBursts::4 11713 # Per bank write bursts -system.physmem.perBankRdBursts::5 11071 # Per bank write bursts -system.physmem.perBankRdBursts::6 11625 # Per bank write bursts -system.physmem.perBankRdBursts::7 11816 # Per bank write bursts -system.physmem.perBankRdBursts::8 11540 # Per bank write bursts -system.physmem.perBankRdBursts::9 11598 # Per bank write bursts -system.physmem.perBankRdBursts::10 11427 # Per bank write bursts -system.physmem.perBankRdBursts::11 11449 # Per bank write bursts -system.physmem.perBankRdBursts::12 11382 # Per bank write bursts -system.physmem.perBankRdBursts::13 12463 # Per bank write bursts -system.physmem.perBankRdBursts::14 11321 # Per bank write bursts -system.physmem.perBankRdBursts::15 11093 # Per bank write bursts -system.physmem.perBankWrBursts::0 10213 # Per bank write bursts -system.physmem.perBankWrBursts::1 9339 # Per bank write bursts -system.physmem.perBankWrBursts::2 9470 # Per bank write bursts -system.physmem.perBankWrBursts::3 9072 # Per bank write bursts -system.physmem.perBankWrBursts::4 9457 # Per bank write bursts -system.physmem.perBankWrBursts::5 9178 # Per bank write bursts -system.physmem.perBankWrBursts::6 9173 # Per bank write bursts -system.physmem.perBankWrBursts::7 8997 # Per bank write bursts -system.physmem.perBankWrBursts::8 8928 # Per bank write bursts -system.physmem.perBankWrBursts::9 9204 # Per bank write bursts -system.physmem.perBankWrBursts::10 9473 # Per bank write bursts -system.physmem.perBankWrBursts::11 8827 # Per bank write bursts -system.physmem.perBankWrBursts::12 9527 # Per bank write bursts -system.physmem.perBankWrBursts::13 9857 # Per bank write bursts -system.physmem.perBankWrBursts::14 9294 # Per bank write bursts -system.physmem.perBankWrBursts::15 9439 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11512 # Per bank write bursts +system.physmem.perBankRdBursts::1 10865 # Per bank write bursts +system.physmem.perBankRdBursts::2 12624 # Per bank write bursts +system.physmem.perBankRdBursts::3 11646 # Per bank write bursts +system.physmem.perBankRdBursts::4 11360 # Per bank write bursts +system.physmem.perBankRdBursts::5 11063 # Per bank write bursts +system.physmem.perBankRdBursts::6 11424 # Per bank write bursts +system.physmem.perBankRdBursts::7 11380 # Per bank write bursts +system.physmem.perBankRdBursts::8 11354 # Per bank write bursts +system.physmem.perBankRdBursts::9 10854 # Per bank write bursts +system.physmem.perBankRdBursts::10 10623 # Per bank write bursts +system.physmem.perBankRdBursts::11 11335 # Per bank write bursts +system.physmem.perBankRdBursts::12 12163 # Per bank write bursts +system.physmem.perBankRdBursts::13 12460 # Per bank write bursts +system.physmem.perBankRdBursts::14 11874 # Per bank write bursts +system.physmem.perBankRdBursts::15 11688 # Per bank write bursts +system.physmem.perBankWrBursts::0 9762 # Per bank write bursts +system.physmem.perBankWrBursts::1 9087 # Per bank write bursts +system.physmem.perBankWrBursts::2 9770 # Per bank write bursts +system.physmem.perBankWrBursts::3 9357 # Per bank write bursts +system.physmem.perBankWrBursts::4 9485 # Per bank write bursts +system.physmem.perBankWrBursts::5 8994 # Per bank write bursts +system.physmem.perBankWrBursts::6 9154 # Per bank write bursts +system.physmem.perBankWrBursts::7 8718 # Per bank write bursts +system.physmem.perBankWrBursts::8 8812 # Per bank write bursts +system.physmem.perBankWrBursts::9 9056 # Per bank write bursts +system.physmem.perBankWrBursts::10 8954 # Per bank write bursts +system.physmem.perBankWrBursts::11 9300 # Per bank write bursts +system.physmem.perBankWrBursts::12 9801 # Per bank write bursts +system.physmem.perBankWrBursts::13 9709 # Per bank write bursts +system.physmem.perBankWrBursts::14 9528 # Per bank write bursts +system.physmem.perBankWrBursts::15 9485 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 5126139591500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5144265948500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184963 # Read request sizes (log2) +system.physmem.readPktSize::6 184401 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149464 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148992 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see @@ -156,303 +156,298 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads -system.physmem.totQLat 1972823732 # Total ticks spent queuing -system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads +system.physmem.totQLat 2113024695 # Total ticks spent queuing +system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing -system.physmem.readRowHits 152120 # Number of row buffer hits during reads -system.physmem.writeRowHits 110229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes -system.physmem.avgGap 15328127.19 # Average gap between requests -system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.732438 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states -system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing +system.physmem.readRowHits 150283 # Number of row buffer hits during reads +system.physmem.writeRowHits 109804 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes +system.physmem.avgGap 15430035.87 # Average gap between requests +system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.806670 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states +system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.730496 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states -system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states +system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states +system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86515320 # Number of BP lookups -system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits +system.cpu.branchPred.lookups 86512376 # Number of BP lookups +system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 448780162 # number of cpu cycles simulated +system.cpu.numCycles 465431904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued @@ -476,98 +471,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued -system.cpu.iq.rate 1.832808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued +system.cpu.iq.rate 1.767144 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed -system.cpu.iew.exec_branches 83150160 # Number of branches executed -system.cpu.iew.exec_stores 9059996 # Number of stores executed -system.cpu.iew.exec_rate 1.829430 # Inst execution rate -system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639922411 # num instructions producing a value -system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value +system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed +system.cpu.iew.exec_branches 83147027 # Number of branches executed +system.cpu.iew.exec_stores 9067588 # Number of stores executed +system.cpu.iew.exec_rate 1.763892 # Inst execution rate +system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639862073 # num instructions producing a value +system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back +system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407767906 # Number of instructions committed -system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407746267 # Number of instructions committed +system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22406164 # Number of memory references committed -system.cpu.commit.loads 13986712 # Number of loads committed -system.cpu.commit.membars 468149 # Number of memory barriers committed -system.cpu.commit.branches 82157432 # Number of branches committed +system.cpu.commit.refs 22407791 # Number of memory references committed +system.cpu.commit.loads 13985627 # Number of loads committed +system.cpu.commit.membars 468163 # Number of memory barriers committed +system.cpu.commit.branches 82155343 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734850257 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155439 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734813827 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155420 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -594,231 +589,230 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction -system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1265696040 # The number of ROB reads -system.cpu.rob.rob_writes 1660107630 # The number of ROB writes -system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407767906 # Number of Instructions Simulated -system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads -system.cpu.int_regfile_writes 654841654 # number of integer regfile writes -system.cpu.fp_regfile_reads 165 # number of floating regfile reads -system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads -system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes -system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads -system.cpu.misc_regfile_writes 399890 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1655948 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction +system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1281402583 # The number of ROB reads +system.cpu.rob.rob_writes 1659991505 # The number of ROB writes +system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407746267 # Number of Instructions Simulated +system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.141474 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # 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number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334795 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334795 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406500 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406500 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2136235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2136235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2542735 # number of overall misses -system.cpu.dcache.overall_misses::total 2542735 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26875877500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26875877500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13801276738 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13801276738 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40677154238 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40677154238 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40677154238 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40677154238 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 469636 # 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number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63083 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18897271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18897271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18960354 # number of overall hits +system.cpu.dcache.overall_hits::total 18960354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses +system.cpu.dcache.overall_misses::total 2542424 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29915350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21131383234 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21131383234 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51046733734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51046733734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51046733734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51046733734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12620561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12620561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412515 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412515 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469702 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469702 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21033076 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21033076 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21502778 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21502778 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142673 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142673 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865696 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865696 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101545 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101545 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118237 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118237 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23900.465508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20077.978234 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 549742 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52309 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.509511 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403128 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1256572 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1256572 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659700 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659700 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275238000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275238000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179377736 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179377736 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6821935500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6821935500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33454615736 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33454615736 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40276551236 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40276551236 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2616393000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2616393000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858263 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858263 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395667 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,180 +821,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 72087 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 816618500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 816618500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 816618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 816618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 816618500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 816618500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395667 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395667 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395667 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 972475 # number of replacements -system.cpu.icache.tags.tagsinuse 509.589862 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7892622 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 972987 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.111745 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147937650500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.589862 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995293 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995293 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 979952 # number of replacements +system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9905522 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9905522 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7892622 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7892622 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7892622 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7892622 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7892622 # number of overall hits -system.cpu.icache.overall_hits::total 7892622 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1039533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1039533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1039533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1039533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1039533 # number of overall misses -system.cpu.icache.overall_misses::total 1039533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14506630997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14506630997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14506630997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14506630997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14506630997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116381 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116381 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116381 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13954.949960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13954.949960 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6454 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.554140 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 9920034 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9920034 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7892668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7892668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7892668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7892668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7892668 # number of overall hits +system.cpu.icache.overall_hits::total 7892668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1046827 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046827 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1046827 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1046827 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses +system.cpu.icache.overall_misses::total 1046827 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66166 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973367 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 973367 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 973367 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 973367 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 973367 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973367 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12880264497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12880264497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12880264497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108973 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108973 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980539 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980539 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13806283989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13806283989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13806283989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13806283989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13806283989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13806283989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13962 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.017494 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 24005 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 95741 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 95741 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 17618 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 17618 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24016 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 24016 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24016 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 24016 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14841 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14841 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14841 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14841 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14841 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14841 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 17620 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 17620 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 17620 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 20167 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 20167 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 20167 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 20167 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 20167 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 20167 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 233184000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 233184000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 233184000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 233184000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 233184000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 233184000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37785 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37785 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38857 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38857 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38857 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38857 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381959 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381959 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381939 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.381939 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381939 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.381939 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.533702 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.533702 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.533702 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1009,183 +1003,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14841 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14841 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155259000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155259000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155259000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155259000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155259000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155259000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381959 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 20167 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 20167 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 20167 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 20167 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 20167 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112328 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64826.279220 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4884469 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176125 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.732968 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111670 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.632944 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.306836 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63797 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 708 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5556 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54082 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.973465 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43431157 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43431157 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1578009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1578009 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154224 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154224 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 956701 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 956701 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 65553 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12091 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332425 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1410069 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 65553 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12091 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 956701 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1486649 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2520994 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 65553 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12091 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 956701 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1486649 # number of overall hits -system.cpu.l2cache.overall_hits::total 2520994 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1786 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1786 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133488 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133488 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16231 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16231 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 61 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 6 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35709 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 35776 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16231 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185495 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16231 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169197 # number of overall misses -system.cpu.l2cache.overall_misses::total 185495 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23220500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23220500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10274230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10274230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1348223000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1348223000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 5829000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 513000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3059963500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3066305500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5829000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 513000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22154566500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257667000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257667000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2456737500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2456737500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92714404500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92714404500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # 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mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 220316 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 226924 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222102 # Transaction distribution -system.iobus.trans_dist::ReadResp 222102 # Transaction distribution -system.iobus.trans_dist::WriteReq 57708 # Transaction distribution -system.iobus.trans_dist::WriteResp 57708 # Transaction distribution -system.iobus.trans_dist::MessageReq 1641 # Transaction distribution -system.iobus.trans_dist::MessageResp 1641 # Transaction distribution +system.iobus.trans_dist::ReadReq 222097 # Transaction distribution +system.iobus.trans_dist::ReadResp 222097 # Transaction distribution +system.iobus.trans_dist::WriteReq 57711 # Transaction distribution +system.iobus.trans_dist::WriteResp 57711 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) @@ -1384,18 +1384,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) @@ -1408,13 +1408,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1426,7 +1426,7 @@ system.iobus.reqLayer4.occupancy 122000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1450,54 +1450,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47580 # number of replacements -system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428715 # Number of tag accesses -system.iocache.tags.data_accesses 428715 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 915 # number of ReadReq misses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 915 # number of demand (read+write) misses -system.iocache.demand_misses::total 915 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses -system.iocache.overall_misses::total 915 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles -system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 915 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 915 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1506,40 +1506,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1548,77 +1548,77 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602896 # Transaction distribution -system.membus.trans_dist::ReadResp 655806 # Transaction distribution -system.membus.trans_dist::WriteReq 13873 # Transaction distribution -system.membus.trans_dist::WriteResp 13873 # Transaction distribution -system.membus.trans_dist::Writeback 149464 # Transaction distribution -system.membus.trans_dist::CleanEvict 9883 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution -system.membus.trans_dist::ReadExReq 133195 # Transaction distribution -system.membus.trans_dist::ReadExResp 133194 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution -system.membus.trans_dist::MessageReq 1641 # Transaction distribution -system.membus.trans_dist::MessageResp 1641 # Transaction distribution +system.membus.trans_dist::ReadReq 602897 # Transaction distribution +system.membus.trans_dist::ReadResp 655826 # Transaction distribution +system.membus.trans_dist::WriteReq 13882 # Transaction distribution +system.membus.trans_dist::WriteResp 13882 # Transaction distribution +system.membus.trans_dist::Writeback 148992 # Transaction distribution +system.membus.trans_dist::CleanEvict 9700 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution +system.membus.trans_dist::ReadExReq 132608 # Transaction distribution +system.membus.trans_dist::ReadExResp 132605 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution system.membus.trans_dist::BadAddressError 8 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1616 # Total snoops (count) -system.membus.snoop_fanout::samples 1013692 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram +system.membus.snoop_fanout::samples 1012128 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1013692 # Request fanout histogram -system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1012128 # Request fanout histogram +system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 494bbffd2..4fb206696 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137726 # Number of seconds simulated -sim_ticks 5137726358500 # Number of ticks simulated -final_tick 5137726358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.141985 # Number of seconds simulated +sim_ticks 5141984685500 # Number of ticks simulated +final_tick 5141984685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193743 # Simulator instruction rate (inst/s) -host_op_rate 385165 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4079424438 # Simulator tick rate (ticks/s) -host_mem_usage 1056160 # Number of bytes of host memory used -host_seconds 1259.42 # Real time elapsed on the host -sim_insts 244004222 # Number of instructions simulated -sim_ops 485086710 # Number of ops (including micro ops) simulated +host_inst_rate 264541 # Simulator instruction rate (inst/s) +host_op_rate 525842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5597553756 # Simulator tick rate (ticks/s) +host_mem_usage 1010248 # Number of bytes of host memory used +host_seconds 918.61 # Real time elapsed on the host +sim_insts 243010444 # Number of instructions simulated +sim_ops 483045307 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 380096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4972288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 215232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2058496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 369024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3382272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 439936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4996672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 212288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2043456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 288960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3313664 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11408192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 380096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 369024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9193728 # Number of bytes written to this memory -system.physmem.bytes_written::total 9193728 # Number of bytes written to this memory +system.physmem.bytes_read::total 11325056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 439936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 212288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 288960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9131200 # Number of bytes written to this memory +system.physmem.bytes_written::total 9131200 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 32164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5766 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 52848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6874 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 31929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 51776 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178253 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143652 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143652 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176954 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142675 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142675 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 73981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 967799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 400663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 658321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2220475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 73981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1789455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1789455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1789455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 85558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 971740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 397406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 56196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 644433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2202468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 85558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 56196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1775812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775812 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 73981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 967799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 400663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 658321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4009929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 94617 # Number of read requests accepted -system.physmem.writeReqs 88760 # Number of write requests accepted -system.physmem.readBursts 94617 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 88760 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6047936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 5680640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6055488 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5680640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 85558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 971740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 397406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 56196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 644433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3978280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 91559 # Number of read requests accepted +system.physmem.writeReqs 81706 # Number of write requests accepted +system.physmem.readBursts 91559 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 81706 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5853184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 5229184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5859776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5229184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 28899 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6147 # Per bank write bursts -system.physmem.perBankRdBursts::1 5269 # Per bank write bursts -system.physmem.perBankRdBursts::2 5685 # Per bank write bursts -system.physmem.perBankRdBursts::3 5978 # Per bank write bursts -system.physmem.perBankRdBursts::4 5788 # Per bank write bursts -system.physmem.perBankRdBursts::5 5231 # Per bank write bursts -system.physmem.perBankRdBursts::6 5218 # Per bank write bursts -system.physmem.perBankRdBursts::7 5097 # Per bank write bursts -system.physmem.perBankRdBursts::8 6282 # Per bank write bursts -system.physmem.perBankRdBursts::9 6366 # Per bank write bursts -system.physmem.perBankRdBursts::10 6408 # Per bank write bursts -system.physmem.perBankRdBursts::11 6175 # Per bank write bursts -system.physmem.perBankRdBursts::12 5716 # Per bank write bursts -system.physmem.perBankRdBursts::13 6642 # Per bank write bursts -system.physmem.perBankRdBursts::14 6153 # Per bank write bursts -system.physmem.perBankRdBursts::15 6344 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 5213 # Per bank write bursts -system.physmem.perBankWrBursts::2 6082 # Per bank write bursts -system.physmem.perBankWrBursts::3 5966 # Per bank write bursts -system.physmem.perBankWrBursts::4 5232 # Per bank write bursts -system.physmem.perBankWrBursts::5 5147 # Per bank write bursts -system.physmem.perBankWrBursts::6 4857 # Per bank write bursts -system.physmem.perBankWrBursts::7 4466 # Per bank write bursts -system.physmem.perBankWrBursts::8 5491 # Per bank write bursts -system.physmem.perBankWrBursts::9 5559 # Per bank write bursts -system.physmem.perBankWrBursts::10 5838 # Per bank write bursts -system.physmem.perBankWrBursts::11 5586 # Per bank write bursts -system.physmem.perBankWrBursts::12 5717 # Per bank write bursts -system.physmem.perBankWrBursts::13 5929 # Per bank write bursts -system.physmem.perBankWrBursts::14 5787 # Per bank write bursts -system.physmem.perBankWrBursts::15 5699 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 24142 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5703 # Per bank write bursts +system.physmem.perBankRdBursts::1 4852 # Per bank write bursts +system.physmem.perBankRdBursts::2 5373 # Per bank write bursts +system.physmem.perBankRdBursts::3 5511 # Per bank write bursts +system.physmem.perBankRdBursts::4 5930 # Per bank write bursts +system.physmem.perBankRdBursts::5 4999 # Per bank write bursts +system.physmem.perBankRdBursts::6 5647 # Per bank write bursts +system.physmem.perBankRdBursts::7 5865 # Per bank write bursts +system.physmem.perBankRdBursts::8 5509 # Per bank write bursts +system.physmem.perBankRdBursts::9 5229 # Per bank write bursts +system.physmem.perBankRdBursts::10 5185 # Per bank write bursts +system.physmem.perBankRdBursts::11 5201 # Per bank write bursts +system.physmem.perBankRdBursts::12 6216 # Per bank write bursts +system.physmem.perBankRdBursts::13 6911 # Per bank write bursts +system.physmem.perBankRdBursts::14 6949 # Per bank write bursts +system.physmem.perBankRdBursts::15 6376 # Per bank write bursts +system.physmem.perBankWrBursts::0 5797 # Per bank write bursts +system.physmem.perBankWrBursts::1 4843 # Per bank write bursts +system.physmem.perBankWrBursts::2 5036 # Per bank write bursts +system.physmem.perBankWrBursts::3 5163 # Per bank write bursts +system.physmem.perBankWrBursts::4 5363 # Per bank write bursts +system.physmem.perBankWrBursts::5 4815 # Per bank write bursts +system.physmem.perBankWrBursts::6 4988 # Per bank write bursts +system.physmem.perBankWrBursts::7 5321 # Per bank write bursts +system.physmem.perBankWrBursts::8 4852 # Per bank write bursts +system.physmem.perBankWrBursts::9 4657 # Per bank write bursts +system.physmem.perBankWrBursts::10 4410 # Per bank write bursts +system.physmem.perBankWrBursts::11 4367 # Per bank write bursts +system.physmem.perBankWrBursts::12 5498 # Per bank write bursts +system.physmem.perBankWrBursts::13 5314 # Per bank write bursts +system.physmem.perBankWrBursts::14 5778 # Per bank write bursts +system.physmem.perBankWrBursts::15 5504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5136593386000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5140984417000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 94617 # Read request sizes (log2) +system.physmem.readPktSize::6 91559 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 88760 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 81706 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 86389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1117 +161,1114 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 89 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.270307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.374177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.197981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16587 39.78% 39.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10275 24.64% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4266 10.23% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2445 5.86% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1622 3.89% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1132 2.71% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 786 1.89% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 680 1.63% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3904 9.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41697 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4370 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.624485 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 178.940609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4367 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4370 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4370 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.311213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.106663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.785732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 51 1.17% 1.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 5 0.11% 1.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 8 0.18% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3654 83.62% 85.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 60 1.37% 86.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 119 2.72% 89.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 59 1.35% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 85 1.95% 92.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 116 2.65% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.30% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.11% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.21% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.07% 95.84% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 276.476998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.125046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 300.303961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15966 39.83% 39.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9813 24.48% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4306 10.74% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2350 5.86% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1723 4.30% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1131 2.82% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 740 1.85% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 595 1.48% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3460 8.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40084 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.316984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.117398 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4096 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.938019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.673577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.950142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.10% 1.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.07% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3475 84.80% 86.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 74 1.81% 88.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.68% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 103 2.51% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 14 0.34% 92.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 88 2.15% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 1.10% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.12% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.20% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.20% 95.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.09% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 133 3.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.14% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.23% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4370 # Writes before turning the bus around for reads -system.physmem.totQLat 1101479246 # Total ticks spent queuing -system.physmem.totMemAccLat 2873335496 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 472495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11655.99 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 126 3.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 13 0.32% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.05% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.37% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4098 # Writes before turning the bus around for reads +system.physmem.totQLat 1118460500 # Total ticks spent queuing +system.physmem.totMemAccLat 2833260500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 457280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12229.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30405.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30979.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.15 # Average write queue length when enqueuing -system.physmem.readRowHits 75876 # Number of row buffer hits during reads -system.physmem.writeRowHits 65681 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 28011110.37 # Average gap between requests -system.physmem.pageHitRate 77.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153536040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83535375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 346421400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279618480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94990329855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2239672524000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2585764947390 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.869445 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3685813216724 # Time in different power states -system.physmem_0.memoryStateTime::REF 127934040000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.88 # Average write queue length when enqueuing +system.physmem.readRowHits 73104 # Number of row buffer hits during reads +system.physmem.writeRowHits 59973 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.40 # Row buffer hit rate for writes +system.physmem.avgGap 29671222.79 # Average gap between requests +system.physmem.pageHitRate 76.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 146323800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79666125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 342256200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 267792480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96409908585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240143266750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587784324100 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.897651 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686083069500 # Time in different power states +system.physmem_0.memoryStateTime::REF 128013860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17956780776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19995411750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 161655480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87978000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 390663000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 295410240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95244065640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2234394426750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580813181350 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.044329 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685435461238 # Time in different power states -system.physmem_1.memoryStateTime::REF 127934040000 # Time in different power states +system.physmem_1.actEnergy 156711240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 371092800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 261662400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96741256995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2232099467250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580110601720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.145421 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685614437250 # Time in different power states +system.physmem_1.memoryStateTime::REF 128013860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18309070012 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20427995000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 810473886 # number of cpu cycles simulated +system.cpu0.numCycles 1069587616 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70312072 # Number of instructions committed -system.cpu0.committedOps 143658243 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 131612768 # Number of integer alu accesses +system.cpu0.committedInsts 72296493 # Number of instructions committed +system.cpu0.committedOps 147472982 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 135372886 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 897074 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13988759 # number of instructions that are conditional controls -system.cpu0.num_int_insts 131612768 # number of integer instructions +system.cpu0.num_func_calls 990052 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14329607 # number of instructions that are conditional controls +system.cpu0.num_int_insts 135372886 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 240911367 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113282572 # number of times the integer registers were written +system.cpu0.num_int_register_reads 248231827 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116398223 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82064957 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 54880945 # number of times the CC registers were written -system.cpu0.num_mem_refs 13139441 # number of memory refs -system.cpu0.num_load_insts 9809284 # Number of load instructions -system.cpu0.num_store_insts 3330157 # Number of store instructions -system.cpu0.num_idle_cycles 769348747.137634 # Number of idle cycles -system.cpu0.num_busy_cycles 41125138.862366 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050742 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949258 # Percentage of idle cycles -system.cpu0.Branches 15218344 # Number of branches fetched -system.cpu0.op_class::No_OpClass 83498 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 130336285 90.73% 90.78% # Class of executed instruction -system.cpu0.op_class::IntMult 55624 0.04% 90.82% # Class of executed instruction -system.cpu0.op_class::IntDiv 45353 0.03% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::MemRead 9807642 6.83% 97.68% # Class of executed instruction -system.cpu0.op_class::MemWrite 3330157 2.32% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 84256506 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56232303 # number of times the CC registers were written +system.cpu0.num_mem_refs 13832544 # number of memory refs +system.cpu0.num_load_insts 10299641 # Number of load instructions +system.cpu0.num_store_insts 3532903 # Number of store instructions +system.cpu0.num_idle_cycles 1014098909.517961 # Number of idle cycles +system.cpu0.num_busy_cycles 55488706.482039 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051879 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948121 # Percentage of idle cycles +system.cpu0.Branches 15685270 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94460 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 133436032 90.48% 90.55% # Class of executed instruction +system.cpu0.op_class::IntMult 61341 0.04% 90.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 50787 0.03% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::MemRead 10297804 6.98% 97.60% # Class of executed instruction +system.cpu0.op_class::MemWrite 3532903 2.40% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143658559 # Class of executed instruction +system.cpu0.op_class::total 147473327 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1637472 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999430 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19610556 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1637984 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.972373 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1636478 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19597198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1636990 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.971483 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 233.382237 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 253.425972 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.191221 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.455825 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.494973 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.049202 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.606115 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.665668 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 114.727666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360559 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415363 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.224077 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88313667 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88313667 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4629522 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2541915 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4295165 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11466602 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3206369 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1799760 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3076031 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8082160 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19345 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9882 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30831 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60058 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7835891 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4341675 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7371196 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19548762 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7855236 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4351557 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7402027 # number of overall hits -system.cpu0.dcache.overall_hits::total 19608820 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 342984 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 163194 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 822092 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1328270 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 120211 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 69264 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 136170 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325645 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 144505 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 65147 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196531 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406183 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 463195 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 232458 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 958262 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1653915 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 607700 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 297605 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1154793 # number of overall misses -system.cpu0.dcache.overall_misses::total 2060098 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262546000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12291465500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14554011500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2775957490 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4654158371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7430115861 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5038503490 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16945623871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21984127361 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5038503490 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16945623871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21984127361 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4972506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2705109 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5117257 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12794872 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3326580 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1869024 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3212201 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8407805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 163850 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 75029 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 227362 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466241 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8299086 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4574133 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8329458 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21202677 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8462936 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4649162 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8556820 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21668918 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.068976 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060328 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.160651 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.103813 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036137 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042391 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038731 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.881935 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.868291 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.864397 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871187 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055813 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050820 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115045 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.078005 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071807 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064013 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134956 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.095072 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13864.149417 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14951.447648 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10957.118282 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40077.926340 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34179.028942 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 22816.612756 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21674.898218 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17683.706409 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13292.174846 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16930.170830 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14674.165734 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10671.398817 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 195153 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88196545 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88196545 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5063587 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2515932 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3866751 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11446270 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3403152 # 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average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 29337.824286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21127.127154 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15849.156166 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22927.128122 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17497.706055 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12698.419087 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 213021 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22760 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22215 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.574385 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.589061 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547245 # number of writebacks -system.cpu0.dcache.writebacks::total 1547245 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 383157 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 383206 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1554 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32300 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31317555500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33896049500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65213605000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060310 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085775 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.047056 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036227 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032336 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020407 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.868291 # 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average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1547054 # number of writebacks +system.cpu0.dcache.writebacks::total 1547054 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 65 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 367229 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 367294 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1711 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33525 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35236 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1776 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 400754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 402530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1776 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 400754 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 402530 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 158637 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 415762 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 574399 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60622 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 105442 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166064 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 61803 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 187828 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 249631 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 219259 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 521204 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 740463 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 281062 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 709032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 990094 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 185046 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 202918 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 387964 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3480 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2043 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 5523 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 188526 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 204961 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 393487 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2187272000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5900092500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8087364500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3897729991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 6072748397 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9970478388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1081694500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2966872000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 4048566500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6085001991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11972840897 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18057842888 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7166696491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14939712897 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 22106409388 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30549904500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32777781000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63327685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 637496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 432772500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1070269000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31187401000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33210553500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64397954500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089416 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045021 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033523 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.034243 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019733 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860275 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.857294 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.535678 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048909 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067435 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034971 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061706 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089208 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045753 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13787.905722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14191.033572 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14079.698084 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64295.635099 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57593.258825 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 60039.974877 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17502.297623 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15795.685414 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16218.204069 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27752.575680 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22971.506161 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24387.231891 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25498.631942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21070.576359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22327.586459 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165093.568626 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161532.150918 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163230.829407 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183188.649425 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211831.864905 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 193783.994206 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165427.585585 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162033.525890 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163659.674907 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 865313 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.808042 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 127930489 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 865825 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 147.755596 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149027837500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 256.241174 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 140.482462 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 114.084406 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.500471 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.274380 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.222821 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997672 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 856629 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.743625 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130224655 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 857141 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 151.929093 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149031497500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 143.311880 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 129.505351 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.926394 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.279906 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.252940 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.464700 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997546 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 129687214 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 129687214 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 85494784 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39252405 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3183300 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 127930489 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85494784 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39252405 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3183300 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 127930489 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85494784 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39252405 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3183300 # number of overall hits -system.cpu0.icache.overall_hits::total 127930489 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 295547 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 174112 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 421231 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 890890 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 295547 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 174112 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 421231 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 890890 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 295547 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 174112 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 421231 # number of overall misses -system.cpu0.icache.overall_misses::total 890890 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2498575500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5836919481 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8335494981 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2498575500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5836919481 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8335494981 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2498575500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5836919481 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8335494981 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 85790331 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39426517 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3604531 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 128821379 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 85790331 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39426517 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3604531 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 128821379 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 85790331 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39426517 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3604531 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 128821379 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003445 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004416 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116862 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006916 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003445 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004416 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116862 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006916 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003445 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004416 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116862 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006916 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14350.392276 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13856.813675 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9356.368329 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14350.392276 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13856.813675 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9356.368329 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14350.392276 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13856.813675 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9356.368329 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4826 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 131961129 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131961129 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 88027171 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39361631 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2835853 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 130224655 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 88027171 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39361631 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2835853 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 130224655 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 88027171 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39361631 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2835853 # number of overall hits +system.cpu0.icache.overall_hits::total 130224655 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 330869 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 176943 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 371512 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 879324 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 330869 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 176943 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 371512 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 879324 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 330869 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 176943 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 88358040 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39538574 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3207365 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 131103979 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 88358040 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39538574 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3207365 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 131103979 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 88358040 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39538574 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3207365 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 131103979 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003745 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004475 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115831 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006707 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003745 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004475 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115831 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006707 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003745 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004475 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115831 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006707 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15272.771457 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14459.819529 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9182.515743 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15272.771457 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14459.819529 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9182.515743 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15272.771457 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14459.819529 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9182.515743 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11595 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 303 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 455 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.927393 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.483516 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25055 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 25055 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 25055 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 25055 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 25055 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 25055 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 174112 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 396176 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 570288 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 174112 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 396176 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 570288 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 174112 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 396176 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 570288 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2324463500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5197379983 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7521843483 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2324463500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5197379983 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7521843483 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2324463500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5197379983 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7521843483 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004427 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004427 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004427 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13189.552442 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22174 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22174 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22174 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22174 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22174 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22174 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 176943 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 349338 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 526281 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 176943 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 349338 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 526281 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 176943 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 349338 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 526281 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2525467000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4769426473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7294893473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2525467000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4769426473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7294893473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2525467000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4769426473 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7294893473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004014 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004014 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004014 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13861.213825 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606018119 # number of cpu cycles simulated +system.cpu1.numCycles 2608369012 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35722790 # Number of instructions committed -system.cpu1.committedOps 69377917 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64437935 # Number of integer alu accesses +system.cpu1.committedInsts 35935781 # Number of instructions committed +system.cpu1.committedOps 69853480 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64823976 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 498036 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6548156 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64437935 # number of integer instructions +system.cpu1.num_func_calls 488968 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6599189 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64823976 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119381439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55453390 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120030856 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55861909 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36402445 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27104510 # number of times the CC registers were written -system.cpu1.num_mem_refs 4834095 # number of memory refs -system.cpu1.num_load_insts 2964009 # Number of load instructions -system.cpu1.num_store_insts 1870086 # Number of store instructions -system.cpu1.num_idle_cycles 2478102522.985643 # Number of idle cycles -system.cpu1.num_busy_cycles 127915596.014357 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049085 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950915 # Percentage of idle cycles -system.cpu1.Branches 7225753 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35671 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64456455 92.91% 92.96% # Class of executed instruction -system.cpu1.op_class::IntMult 31131 0.04% 93.00% # Class of executed instruction -system.cpu1.op_class::IntDiv 22623 0.03% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::MemRead 2962280 4.27% 97.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 1870086 2.70% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36569866 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27235503 # number of times the CC registers were written +system.cpu1.num_mem_refs 4739526 # number of memory refs +system.cpu1.num_load_insts 2929606 # Number of load instructions +system.cpu1.num_store_insts 1809920 # Number of store instructions +system.cpu1.num_idle_cycles 2476291441.144386 # Number of idle cycles +system.cpu1.num_busy_cycles 132077570.855614 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050636 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949364 # Percentage of idle cycles +system.cpu1.Branches 7267259 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35769 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 65023245 93.08% 93.14% # Class of executed instruction +system.cpu1.op_class::IntMult 31643 0.05% 93.18% # Class of executed instruction +system.cpu1.op_class::IntDiv 24977 0.04% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::MemRead 2928241 4.19% 97.41% # Class of executed instruction +system.cpu1.op_class::MemWrite 1809920 2.59% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69378246 # Class of executed instruction +system.cpu1.op_class::total 69853795 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29560975 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29560975 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 321330 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26625449 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26036610 # Number of BTB hits +system.cpu2.branchPred.lookups 28595724 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28595724 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 274281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 25954960 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25419524 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.788435 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 603794 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 66654 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155113045 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.937057 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 541766 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 58217 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155590039 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11047280 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145686023 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29560975 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26640404 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142542790 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 677515 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 104928 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8867 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 68985 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3604542 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 166149 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3283 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154116964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.860489 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.036370 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9827756 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141445049 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28595724 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 25961290 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144324316 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 577708 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 89529 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9926 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 52140 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1381 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3207378 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 141789 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2491 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154597903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.800587 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.004500 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98277439 63.77% 63.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 921613 0.60% 64.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23771065 15.42% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 603849 0.39% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 843324 0.55% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 864608 0.56% 81.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 573617 0.37% 81.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 772001 0.50% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27489448 17.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100285595 64.87% 64.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 850088 0.55% 65.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23359910 15.11% 80.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 558025 0.36% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 768716 0.50% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 809103 0.52% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 512827 0.33% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 703407 0.45% 82.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26750232 17.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154116964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.190577 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.939225 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10113688 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93745988 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23732554 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5061206 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 339409 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283817902 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 339409 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12262766 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76655623 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4610961 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26368994 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12755160 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282570010 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 203292 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5910187 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 59652 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4622392 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337562699 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 617313701 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378956511 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 176 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325317107 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12245592 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 169706 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 171154 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24674635 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6903065 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3842483 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 404867 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 342392 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280633357 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 431682 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278499537 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103065 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9014489 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13791367 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 66778 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154116964 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.807066 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400549 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154597903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.183789 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909088 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8590820 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95748375 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 20322096 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4023271 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 289506 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 275783905 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 289506 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10203934 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77122652 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4692669 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 22463307 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14202064 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 274713209 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 193941 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5398657 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70031 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 7189088 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 328421156 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 598952608 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 367856783 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 202 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 317944423 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10476733 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 154897 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 156262 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19984245 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6287198 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3639298 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 400920 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 367403 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 273029174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 403661 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 271361789 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 92310 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7713990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11716947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 58327 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154597903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755275 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385225 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90926640 59.00% 59.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5330208 3.46% 62.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3853102 2.50% 64.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3864237 2.51% 67.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22585971 14.66% 82.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2780196 1.80% 83.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24046184 15.60% 99.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 494962 0.32% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 235464 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93164208 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5135729 3.32% 63.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3649233 2.36% 65.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3187928 2.06% 68.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23055647 14.91% 82.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2154571 1.39% 84.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23598215 15.26% 99.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 439899 0.28% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 212473 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154116964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154597903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1774419 86.10% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 221659 10.76% 96.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 64684 3.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1212353 81.77% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 211907 14.29% 96.06% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 58391 3.94% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 87958 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267524922 96.06% 96.09% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 58980 0.02% 96.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 56493 0.02% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 63 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7208859 2.59% 98.72% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3562262 1.28% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 71762 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 261142020 96.23% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 52428 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48121 0.02% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 75 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6661415 2.45% 98.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3385968 1.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278499537 # Type of FU issued -system.cpu2.iq.rate 1.795462 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2060762 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007400 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713279610 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 290083917 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276907807 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280472218 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 745560 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 271361789 # Type of FU issued +system.cpu2.iq.rate 1.744082 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1482651 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005464 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 698896144 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 281150786 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 269884047 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 272772537 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 697485 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1225052 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5188 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 625672 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1044107 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5365 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4726 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 557112 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750058 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26954 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 749552 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 25864 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 339409 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70544458 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3078967 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281065039 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 38553 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6903084 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3842483 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 256263 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 170697 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2578390 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5188 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 180466 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 193564 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374030 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277914745 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7063605 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530025 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 289506 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69224885 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4893125 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 273432835 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 29776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6287198 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3639298 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 235948 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 164149 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4411192 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4726 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 153905 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164065 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 317970 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 270855594 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6536848 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 455372 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10537501 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28240197 # Number of branches executed -system.cpu2.iew.exec_stores 3473896 # Number of stores executed -system.cpu2.iew.exec_rate 1.791692 # Inst execution rate -system.cpu2.iew.wb_sent 277728046 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276907908 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215869899 # num instructions producing a value -system.cpu2.iew.wb_consumers 354183211 # num instructions consuming a value +system.cpu2.iew.exec_refs 9843230 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27477788 # Number of branches executed +system.cpu2.iew.exec_stores 3306382 # Number of stores executed +system.cpu2.iew.exec_rate 1.740829 # Inst execution rate +system.cpu2.iew.wb_sent 270693369 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 269884157 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 210625616 # num instructions producing a value +system.cpu2.iew.wb_consumers 345602988 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.785201 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609487 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.734585 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609444 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9010167 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325088 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152771285 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.780770 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.657176 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7711989 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 345334 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 277097 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153447715 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731657 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.637088 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94646882 61.95% 61.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4418156 2.89% 64.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1318603 0.86% 65.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24750822 16.20% 81.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 992364 0.65% 82.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 731797 0.48% 83.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 443039 0.29% 83.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23300929 15.25% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2168693 1.42% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 96780970 63.07% 63.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4222028 2.75% 65.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1231000 0.80% 66.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24221852 15.79% 82.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 924771 0.60% 83.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 693299 0.45% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 425605 0.28% 83.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 22935468 14.95% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2012722 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152771285 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137969360 # Number of instructions committed -system.cpu2.commit.committedOps 272050550 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153447715 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 134778170 # Number of instructions committed +system.cpu2.commit.committedOps 265718845 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8894843 # Number of memory references committed -system.cpu2.commit.loads 5678032 # Number of loads committed -system.cpu2.commit.membars 160530 # Number of memory barriers committed -system.cpu2.commit.branches 27847068 # Number of branches committed +system.cpu2.commit.refs 8325277 # Number of memory references committed +system.cpu2.commit.loads 5243091 # Number of loads committed +system.cpu2.commit.membars 153740 # Number of memory barriers committed +system.cpu2.commit.branches 27132938 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248702825 # Number of committed integer instructions. -system.cpu2.commit.function_calls 458806 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 52824 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 262991815 96.67% 96.69% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 56918 0.02% 96.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 54179 0.02% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5677987 2.09% 98.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3216811 1.18% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 242753564 # Number of committed integer instructions. +system.cpu2.commit.function_calls 416792 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 41984 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 257254606 96.81% 96.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 50787 0.02% 96.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 46205 0.02% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5243061 1.97% 98.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3082186 1.16% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272050550 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2168693 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 431630642 # The number of ROB reads -system.cpu2.rob.rob_writes 563473683 # The number of ROB writes -system.cpu2.timesIdled 116646 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 996081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908046353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137969360 # Number of Instructions Simulated -system.cpu2.committedOps 272050550 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.124257 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.124257 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.889476 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.889476 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370420908 # number of integer regfile reads -system.cpu2.int_regfile_writes 221942656 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73069 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141352578 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108476747 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90603281 # number of misc regfile reads -system.cpu2.misc_regfile_writes 149391 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552124 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552124 # Transaction distribution -system.iobus.trans_dist::WriteReq 57703 # Transaction distribution -system.iobus.trans_dist::WriteResp 57703 # Transaction distribution -system.iobus.trans_dist::MessageReq 1656 # Transaction distribution -system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.cpu2.commit.op_class_0::total 265718845 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2012722 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 424836983 # The number of ROB reads +system.cpu2.rob.rob_writes 548017282 # The number of ROB writes +system.cpu2.timesIdled 100227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 992136 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909996040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 134778170 # Number of Instructions Simulated +system.cpu2.committedOps 265718845 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.154416 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.154416 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.866239 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.866239 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 360832495 # number of integer regfile reads +system.cpu2.int_regfile_writes 216221900 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73134 # number of floating regfile reads +system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes +system.cpu2.cc_regfile_reads 137826475 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106107258 # number of cc regfile writes +system.cpu2.misc_regfile_reads 87959882 # number of misc regfile reads +system.cpu2.misc_regfile_writes 137617 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552161 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552161 # Transaction distribution +system.iobus.trans_dist::WriteReq 57740 # Transaction distribution +system.iobus.trans_dist::WriteResp 57740 # Transaction distribution +system.iobus.trans_dist::MessageReq 1667 # Transaction distribution +system.iobus.trans_dist::MessageResp 1667 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27868 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95250 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95250 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7222966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124546 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7223136 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540108 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540117 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13927 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13934 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602845 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2765072 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568475 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602951 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2194728 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5295000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3095000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 748000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 140118000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 421000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11369000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8907000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 144756051 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 119418499 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 299839000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 295238000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30990000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 23500000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1161000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 920000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47570 # number of replacements -system.iocache.tags.tagsinuse 0.092294 # Cycle average of tags in use +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.105025 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000591335509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005768 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005768 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000694858009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.105025 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006564 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006564 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428625 # Number of tag accesses -system.iocache.tags.data_accesses 428625 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 905 # number of demand (read+write) misses -system.iocache.demand_misses::total 905 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 905 # number of overall misses -system.iocache.overall_misses::total 905 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128938756 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128938756 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3283387295 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3283387295 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 128938756 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 128938756 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 128938756 # number of overall miss cycles -system.iocache.overall_miss_latency::total 128938756 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17834920 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17834920 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3008484579 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3008484579 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 17834920 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 17834920 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 17834920 # number of overall miss cycles +system.iocache.overall_miss_latency::total 17834920 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 905 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 905 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 905 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 905 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1280,323 +1277,323 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142473.763536 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 142473.763536 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 142473.763536 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 19641.982379 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 19641.982379 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 19641.982379 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 771 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27816 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 27816 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 771 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 771 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 771 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 771 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90388756 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1892587295 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1892587295 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 90388756 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 90388756 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.851934 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.595377 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.595377 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.851934 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.851934 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 150 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 23200 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 23200 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 150 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 150 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 150 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 150 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10334920 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1848484579 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1848484579 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10334920 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10334920 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.165198 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.496575 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.496575 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.165198 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.165198 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105297 # number of replacements -system.l2c.tags.tagsinuse 64829.932138 # Cycle average of tags in use -system.l2c.tags.total_refs 4653506 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169379 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.473925 # Average number of references to valid blocks. +system.l2c.tags.replacements 104099 # number of replacements +system.l2c.tags.tagsinuse 64798.751400 # Cycle average of tags in use +system.l2c.tags.total_refs 4622477 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168145 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.491017 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51173.407982 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1534.003878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4961.516829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 244.491161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1538.007484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.330522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1242.728330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4127.311591 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.780844 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50975.916354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1575.171206 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4997.364493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 516.989893 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1851.248692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 5.076348 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 959.125226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3917.724589 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777831 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.023407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000127 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.062978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989226 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64082 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3909 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52613 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977814 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41530530 # Number of tag accesses -system.l2c.tags.data_accesses 41530530 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 18603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 13451 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 62068 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 124940 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024035 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000077 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.014635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.059780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988750 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64046 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3569 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52933 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977264 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41263442 # Number of tag accesses +system.l2c.tags.data_accesses 41263442 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10440 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6238 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 52514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.114641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035277 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 142977.272727 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70583.025830 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70739.830508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70690.476190 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117000.591541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 120028.135432 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118803.919810 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124134.448417 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121974.191663 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 128086.764828 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126257.446809 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117794.030825 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117794.030825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152593.568626 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149032.145990 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150730.826829 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171688.649425 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200329.907000 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 182283.269962 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152946.044577 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 149543.469245 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151173.698242 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5066901 # Transaction distribution -system.membus.trans_dist::ReadResp 5115808 # Transaction distribution -system.membus.trans_dist::WriteReq 13888 # Transaction distribution -system.membus.trans_dist::WriteResp 13888 # Transaction distribution -system.membus.trans_dist::Writeback 143652 # Transaction distribution -system.membus.trans_dist::CleanEvict 8856 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1645 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1645 # Transaction distribution -system.membus.trans_dist::ReadExReq 130459 # Transaction distribution -system.membus.trans_dist::ReadExResp 130459 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48907 # Transaction distribution -system.membus.trans_dist::MessageReq 1656 # Transaction distribution -system.membus.trans_dist::MessageResp 1656 # Transaction distribution +system.membus.trans_dist::ReadReq 5081876 # Transaction distribution +system.membus.trans_dist::ReadResp 5130307 # Transaction distribution +system.membus.trans_dist::WriteReq 13937 # Transaction distribution +system.membus.trans_dist::WriteResp 13937 # Transaction distribution +system.membus.trans_dist::Writeback 142675 # Transaction distribution +system.membus.trans_dist::CleanEvict 8457 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1667 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1667 # Transaction distribution +system.membus.trans_dist::ReadExReq 129637 # Transaction distribution +system.membus.trans_dist::ReadExResp 129637 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48432 # Transaction distribution +system.membus.trans_dist::MessageReq 1667 # Transaction distribution +system.membus.trans_dist::MessageResp 1667 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10626768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10772166 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074345 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17606208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27248990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3023616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3023616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30279230 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 694 # Total snoops (count) -system.membus.snoop_fanout::samples 5463095 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017408 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3067080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10653122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10798595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568475 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6134157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17466624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27169256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3035200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3035200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30211124 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 409 # Total snoops (count) +system.membus.snoop_fanout::samples 5475610 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017446 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5461439 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1656 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5473943 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5463095 # Request fanout histogram -system.membus.reqLayer0.occupancy 232635000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5475610 # Request fanout histogram +system.membus.reqLayer0.occupancy 227177500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304127000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 301308000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2322000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1840000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 583726731 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 538434425 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1161000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 920000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1349926167 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1326481306 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 52433855 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 41176558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1814,53 +1815,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 5228525 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7442369 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1636010 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 961008 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1644 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290225 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290225 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 865835 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1348541 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1161 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 27816 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2596558 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15078411 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72306 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 219403 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17966678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55412672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213513438 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 261576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 779088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269966774 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176011 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10394757 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029410 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.168953 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 5040257 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546109 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 319 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1148 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 5235870 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7440960 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13939 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13939 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1628762 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 950991 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1645 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1645 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289206 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289206 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 857150 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1347950 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 920 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 23200 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2570707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15105454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 66396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204903 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17947460 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54857344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213491432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 241048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 697376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269287200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 238040 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10439686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005090 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.071166 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10089048 97.06% 97.06% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 305709 2.94% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 10386543 99.49% 99.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 53143 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10394757 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2840392499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 10439686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2709674498 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 358500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 251420 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 856033294 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 789952436 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1941516813 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1874874404 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27469982 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23291487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100352159 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 94859175 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 8f24165d3..2f7887688 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.061241 # Number of seconds simulated -sim_ticks 61240850500 # Number of ticks simulated -final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61241011500 # Number of ticks simulated +final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182783 # Simulator instruction rate (inst/s) -host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123547949 # Simulator tick rate (ticks/s) -host_mem_usage 442472 # Number of bytes of host memory used -host_seconds 495.69 # Real time elapsed on the host +host_inst_rate 252391 # Simulator instruction rate (inst/s) +host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170598134 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 358.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61240757000 # Total gap between requests +system.physmem.totGap 61240917000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.totQLat 73458500 # Total ticks spent queuing -system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation +system.physmem.totQLat 73241750 # Total ticks spent queuing +system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 14026 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3932243.29 # Average gap between requests +system.physmem.avgGap 3932253.56 # Average gap between requests system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.518851 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states +system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511702 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.514525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states +system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513254 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -377,29 +377,29 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122481701 # number of cpu cycles simulated +system.cpu.numCycles 122482023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351853 # CPI: cycles per instruction -system.cpu.ipc 0.739726 # IPC: instructions per cycle -system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.351856 # CPI: cycles per instruction +system.cpu.ipc 0.739724 # IPC: instructions per cycle +system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits -system.cpu.icache.overall_hits::total 27770466 # number of overall hits +system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits +system.cpu.icache.overall_hits::total 27770468 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -660,18 +660,18 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) @@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +740,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,19 +764,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution @@ -792,14 +798,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) @@ -827,9 +833,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6f66b7dfa..6db072c1c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058182 # Number of seconds simulated -sim_ticks 58182114500 # Number of ticks simulated -final_tick 58182114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058181 # Number of seconds simulated +sim_ticks 58181475500 # Number of ticks simulated +final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128679 # Simulator instruction rate (inst/s) -host_op_rate 129320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82645168 # Simulator tick rate (ticks/s) -host_mem_usage 446228 # Number of bytes of host memory used -host_seconds 704.00 # Real time elapsed on the host +host_inst_rate 122946 # Simulator instruction rate (inst/s) +host_op_rate 123559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78962453 # Simulator tick rate (ticks/s) +host_mem_usage 448784 # Number of bytes of host memory used +host_seconds 736.82 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 933184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1028928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 27456 # Number of bytes written to this memory -system.physmem.bytes_written::total 27456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 429 # Number of write requests responded to by this memory -system.physmem.num_writes::total 429 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 761196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 884395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16039018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17684610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 471898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 884395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16039018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18156508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16077 # Number of read requests accepted -system.physmem.writeReqs 429 # Number of write requests accepted -system.physmem.readBursts 16077 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1014080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14848 # Total number of bytes read from write queue -system.physmem.bytesWritten 26048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1028928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 27456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 232 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory +system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory +system.physmem.bytes_written::total 28672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16061 # Number of read requests accepted +system.physmem.writeReqs 448 # Number of write requests accepted +system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue +system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1011 # Per bank write bursts +system.physmem.perBankRdBursts::0 1015 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 957 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1060 # Per bank write bursts -system.physmem.perBankRdBursts::5 1137 # Per bank write bursts -system.physmem.perBankRdBursts::6 1146 # Per bank write bursts -system.physmem.perBankRdBursts::7 1099 # Per bank write bursts -system.physmem.perBankRdBursts::8 1049 # Per bank write bursts +system.physmem.perBankRdBursts::2 960 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1138 # Per bank write bursts +system.physmem.perBankRdBursts::6 1126 # Per bank write bursts +system.physmem.perBankRdBursts::7 1116 # Per bank write bursts +system.physmem.perBankRdBursts::8 1048 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 940 # Per bank write bursts -system.physmem.perBankRdBursts::11 901 # Per bank write bursts -system.physmem.perBankRdBursts::12 907 # Per bank write bursts -system.physmem.perBankRdBursts::13 888 # Per bank write bursts -system.physmem.perBankRdBursts::14 960 # Per bank write bursts -system.physmem.perBankRdBursts::15 923 # Per bank write bursts -system.physmem.perBankWrBursts::0 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 947 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 891 # Per bank write bursts +system.physmem.perBankRdBursts::14 939 # Per bank write bursts +system.physmem.perBankRdBursts::15 932 # Per bank write bursts +system.physmem.perBankWrBursts::0 39 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 7 # Per bank write bursts -system.physmem.perBankWrBursts::4 4 # Per bank write bursts -system.physmem.perBankWrBursts::5 30 # Per bank write bursts -system.physmem.perBankWrBursts::6 102 # Per bank write bursts -system.physmem.perBankWrBursts::7 27 # Per bank write bursts -system.physmem.perBankWrBursts::8 34 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts +system.physmem.perBankWrBursts::5 33 # Per bank write bursts +system.physmem.perBankWrBursts::6 78 # Per bank write bursts +system.physmem.perBankWrBursts::7 51 # Per bank write bursts +system.physmem.perBankWrBursts::8 44 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 11 # Per bank write bursts -system.physmem.perBankWrBursts::11 5 # Per bank write bursts -system.physmem.perBankWrBursts::12 6 # Per bank write bursts -system.physmem.perBankWrBursts::13 38 # Per bank write bursts -system.physmem.perBankWrBursts::14 82 # Per bank write bursts -system.physmem.perBankWrBursts::15 24 # Per bank write bursts +system.physmem.perBankWrBursts::10 13 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 8 # Per bank write bursts +system.physmem.perBankWrBursts::13 25 # Per bank write bursts +system.physmem.perBankWrBursts::14 64 # Per bank write bursts +system.physmem.perBankWrBursts::15 39 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58181957500 # Total gap between requests +system.physmem.totGap 58181318500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16077 # Read request sizes (log2) +system.physmem.readPktSize::6 16061 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 429 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10965 # What read queue length does an incoming req see +system.physmem.writePktSize::6 448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see @@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -197,93 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 535.822406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.454496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 434.844935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 623 32.16% 32.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 199 10.27% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 5.11% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 70 3.61% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 2.53% 53.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 2.63% 56.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 2.63% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 2.43% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 38.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 687.695652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.373989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3139.186163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.695652 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676543 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.822125 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4 17.39% 17.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18 78.26% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 4.35% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.physmem.totQLat 162696744 # Total ticks spent queuing -system.physmem.totMemAccLat 459790494 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.02 # Average queueing delay per DRAM burst +system.physmem.totQLat 162337192 # Total ticks spent queuing +system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing -system.physmem.avgWrQLen 18.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14165 # Number of row buffer hits during reads -system.physmem.writeRowHits 138 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing +system.physmem.readRowHits 14167 # Number of row buffer hits during reads +system.physmem.writeRowHits 131 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.47 # Row buffer hit rate for writes -system.physmem.avgGap 3524897.46 # Average gap between requests -system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7749000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4228125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64591800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1302480 # Energy for write commands per rank (pJ) +system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes +system.physmem.avgGap 3524218.21 # Average gap between requests +system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2489657400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32723562000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39091051125 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.908601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54427806081 # Time in different power states +system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.947294 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1808607669 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6811560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3716625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1211760 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2472306885 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32738773500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39081467850 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.744040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54453180249 # Time in different power states +system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.722887 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1783438751 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257673 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279792 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837861 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842586 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784928 # Number of BTB hits +system.cpu.branchPred.lookups 28257355 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513130 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75759 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116364230 # number of cpu cycles simulated +system.cpu.numCycles 116362952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748840 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134987137 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257673 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860687 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114722877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301983 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116313064 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58742008 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13941997 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9231022 7.94% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398037 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116313064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64052748 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33035096 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558012 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101304 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430189 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996961 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15280915 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49896712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425336 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14773354 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898724 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415582 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131047 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144428 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527040 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487812 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483272365 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119474128 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21506605 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812984 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349507 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517744 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254125 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109690412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387626 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074735 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18657629 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41690294 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116313064 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989298 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54672209 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31362113 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008866 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072036 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197527 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,9 +487,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116313064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9793385 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available @@ -512,19 +512,19 @@ system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # at system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 14 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9616432 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703828 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984128 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +546,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343025 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049584 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387626 # Type of FU issued -system.cpu.iq.rate 0.871295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20113709 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198384 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340276307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128356979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625202 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501099 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued +system.cpu.iq.rate 0.871306 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4337073 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1343 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604663 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130598 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8118752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684481 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109711326 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812984 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349507 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 179113 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1343 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436660 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126680 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806374 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260946 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28724279 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624229 # Number of branches executed -system.cpu.iew.exec_stores 4917905 # Number of stores executed -system.cpu.iew.exec_rate 0.860459 # Inst execution rate -system.cpu.iew.wb_sent 99709898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625314 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703303 # num instructions producing a value -system.cpu.iew.wb_consumers 95544285 # num instructions consuming a value +system.cpu.iew.exec_nop 12668 # number of nop insts executed +system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624234 # Number of branches executed +system.cpu.iew.exec_stores 4917910 # Number of stores executed +system.cpu.iew.exec_rate 0.860470 # Inst execution rate +system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703416 # num instructions producing a value +system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856151 # insts written-back per cycle +system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113620717 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77197638 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18614899 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7150727 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466583 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641577 1.44% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544810 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704355 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179975 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120153 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113620717 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +675,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120153 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217934090 # The number of ROB reads -system.cpu.rob.rob_writes 219571457 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51166 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217931602 # The number of ROB reads +system.cpu.rob.rob_writes 219570402 # The number of ROB writes +system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778502 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111423 # number of integer regfile reads -system.cpu.int_regfile_writes 58700979 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111563 # number of integer regfile reads +system.cpu.int_regfile_writes 58701013 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063033 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693305 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414934 # number of misc regfile reads +system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470204 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787652 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18251843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470716 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336280 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 5470194 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787652 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908596 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908596 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353793 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353793 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243562 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243562 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244084 # number of overall hits -system.cpu.dcache.overall_hits::total 18244084 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585887 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585887 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381188 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381188 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits +system.cpu.dcache.overall_hits::total 18244176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967082 # number of overall misses -system.cpu.dcache.overall_misses::total 9967082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4007000296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4007000296 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses +system.cpu.dcache.overall_misses::total 9967031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92728516796 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92728516796 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475656 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,100 +755,100 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080505 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080505 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353309 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353309 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.431083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.431083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.483399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9303.483399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.476865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9303.476865 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329940 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 111027 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716427 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.648310 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5432438 # number of writebacks -system.cpu.dcache.writebacks::total 5432438 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158703 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158703 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks +system.cpu.dcache.writebacks::total 5433212 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496363 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496363 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470716 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470716 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2284927222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2284927222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193924 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.036329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.036329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.069452 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.069452 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.507566 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300812 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35495.397802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.507566 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id @@ -857,196 +857,196 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 51 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64604850 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64604850 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300812 # number of overall hits -system.cpu.icache.overall_hits::total 32300812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses -system.cpu.icache.overall_misses::total 1158 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61588984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61588984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61588984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61588984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32301970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32301970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32301970 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32301970 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32301970 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32301970 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64604262 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64604262 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32300517 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32300517 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32300517 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32300517 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32300517 # number of overall hits +system.cpu.icache.overall_hits::total 32300517 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses +system.cpu.icache.overall_misses::total 1159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62258984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62258984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62258984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62258984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19024 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53717.846419 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53717.846419 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.551111 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49864488 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49864488 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49864488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49864488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49864488 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49864488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50293988 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50293988 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50293988 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50293988 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50293988 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50293988 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54796.140659 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54796.140659 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4982376 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5297288 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 273784 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4980719 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5295706 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273829 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074296 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 642 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12072.124687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10689018 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 16082 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 664.657257 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 620 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 574.634156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 222.368326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 216.541992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.674962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.013572 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013217 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.736824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15165 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 575.029353 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 219.514162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 213.224612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675258 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.013398 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013014 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.736767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 266 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15174 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 238 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1064 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.925598 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175272448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175272448 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 5432438 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5432438 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226006 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226006 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 217 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 217 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243653 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243653 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469659 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469876 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 217 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469659 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469876 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 504 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 504 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 693 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 693 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 553 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 553 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 693 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1057 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1750 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 693 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1057 # number of overall misses -system.cpu.l2cache.overall_misses::total 1750 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42131500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 42131500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32807500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32807500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47516500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 74939000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 122455500 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.760440 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000273 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.760440 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000147 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004056 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5245116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5432867 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 35515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226510 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697801856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697860096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 23225 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10965506 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045973 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 23240 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10942281 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 23225 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10965506 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10903578500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206077992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15736 # Transaction distribution -system.membus.trans_dist::Writeback 429 # Transaction distribution -system.membus.trans_dist::CleanEvict 169 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15736 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1056384 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15718 # Transaction distribution +system.membus.trans_dist::Writeback 448 # Transaction distribution +system.membus.trans_dist::CleanEvict 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 343 # Transaction distribution +system.membus.trans_dist::ReadExResp 343 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16675 # Request fanout histogram +system.membus.snoop_fanout::samples 16648 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16675 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16675 # Request fanout histogram -system.membus.reqLayer0.occupancy 28309413 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16648 # Request fanout histogram +system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 84107303 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86fbc3533..8cbe9f760 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488535500 # Number of ticks simulated -final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488536500 # Number of ticks simulated +final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1224088 # Simulator instruction rate (inst/s) -host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1814798992 # Simulator tick rate (ticks/s) -host_mem_usage 426288 # Number of bytes of host memory used -host_seconds 199.19 # Real time elapsed on the host +host_inst_rate 1117046 # Simulator instruction rate (inst/s) +host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1656101101 # Simulator tick rate (ticks/s) +host_mem_usage 428664 # Number of bytes of host memory used +host_seconds 218.28 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977071 # number of cpu cycles simulated +system.cpu.numCycles 722977073 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -304,13 +304,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -458,6 +458,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution @@ -473,14 +479,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 40c2eacfb..9774ca6b0 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu sim_ticks 61602395500 # Number of ticks simulated final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83209 # Simulator instruction rate (inst/s) -host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32444685 # Simulator tick rate (ticks/s) -host_mem_usage 451056 # Number of bytes of host memory used -host_seconds 1898.69 # Real time elapsed on the host +host_inst_rate 109389 # Simulator instruction rate (inst/s) +host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42652748 # Simulator tick rate (ticks/s) +host_mem_usage 458300 # Number of bytes of host memory used +host_seconds 1444.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 132992250 # Total ticks spent queuing -system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 132940250 # Total ticks spent queuing +system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s @@ -249,28 +249,28 @@ system.physmem_0.preEnergy 5960625 # En system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.233667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states +system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.233237 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.432156 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states +system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.431985 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 36908902 # Number of BP lookups system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted @@ -325,24 +325,24 @@ system.cpu.decode.SquashCycles 776598 # Nu system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 492 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. @@ -358,13 +358,13 @@ system.cpu.iq.issued_per_cycle::samples 123139971 # Nu system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -401,7 +401,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available @@ -441,15 +441,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued system.cpu.iq.rate 2.484506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested +system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -464,14 +464,14 @@ system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly @@ -485,7 +485,7 @@ system.cpu.iew.exec_refs 131430383 # nu system.cpu.iew.exec_branches 31401847 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed system.cpu.iew.exec_rate 2.476825 # Inst execution rate -system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213925 # num instructions producing a value system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value @@ -500,14 +500,14 @@ system.cpu.commit.committed_per_cycle::samples 117119203 system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -570,7 +570,7 @@ system.cpu.cpi_total 0.779834 # CP system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 491477122 # number of integer regfile reads -system.cpu.int_regfile_writes 239432261 # number of integer regfile writes +system.cpu.int_regfile_writes 239432260 # number of integer regfile writes system.cpu.fp_regfile_reads 110 # number of floating regfile reads system.cpu.fp_regfile_writes 84 # number of floating regfile writes system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads @@ -609,14 +609,14 @@ system.cpu.dcache.demand_misses::cpu.data 2785082 # n system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses system.cpu.dcache.overall_misses::total 2785082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -633,19 +633,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -683,22 +683,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id @@ -721,12 +721,12 @@ system.cpu.icache.demand_misses::cpu.inst 1323 # n system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses @@ -739,12 +739,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,34 +765,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 487 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy @@ -834,18 +834,18 @@ system.cpu.l2cache.demand_misses::total 30422 # nu system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses system.cpu.l2cache.overall_misses::total 30422 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) @@ -874,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,18 +910,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses @@ -936,19 +936,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution @@ -966,15 +972,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 487 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) @@ -1005,7 +1011,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d40f8a71c..d05ee6d96 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365988859500 # Number of ticks simulated final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643347 # Simulator instruction rate (inst/s) -host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490347920 # Simulator tick rate (ticks/s) -host_mem_usage 451472 # Number of bytes of host memory used -host_seconds 245.57 # Real time elapsed on the host +host_inst_rate 563395 # Simulator instruction rate (inst/s) +host_op_rate 992048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1305133674 # Simulator tick rate (ticks/s) +host_mem_usage 455224 # Number of bytes of host memory used +host_seconds 280.42 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 313 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 0819be4e4..91596dbee 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.412080 # Nu sim_ticks 412080064500 # Number of ticks simulated final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229857 # Simulator instruction rate (inst/s) -host_op_rate 229857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154795079 # Simulator tick rate (ticks/s) -host_mem_usage 293864 # Number of bytes of host memory used -host_seconds 2662.10 # Real time elapsed on the host +host_inst_rate 310711 # Simulator instruction rate (inst/s) +host_op_rate 310711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209245414 # Simulator tick rate (ticks/s) +host_mem_usage 301844 # Number of bytes of host memory used +host_seconds 1969.36 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -704,6 +704,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5082760 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538418 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution @@ -719,15 +725,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 346897 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.244556 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.020980 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5082760 93.61% 93.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 346897 6.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5427266 99.96% 99.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2391 0.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 0b95ee278..7a68c081f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363605 # Number of seconds simulated -sim_ticks 363605295500 # Number of ticks simulated -final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363600 # Number of seconds simulated +sim_ticks 363599502500 # Number of ticks simulated +final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163495 # Simulator instruction rate (inst/s) -host_op_rate 177087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117350463 # Simulator tick rate (ticks/s) -host_mem_usage 312624 # Number of bytes of host memory used -host_seconds 3098.46 # Real time elapsed on the host +host_inst_rate 226144 # Simulator instruction rate (inst/s) +host_op_rate 244944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162315109 # Simulator tick rate (ticks/s) +host_mem_usage 321124 # Number of bytes of host memory used +host_seconds 2240.08 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory -system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144121 # Number of read requests accepted -system.physmem.writeReqs 96704 # Number of write requests accepted -system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144124 # Number of read requests accepted +system.physmem.writeReqs 96709 # Number of write requests accepted +system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::0 9331 # Per bank write bursts system.physmem.perBankRdBursts::1 8969 # Per bank write bursts -system.physmem.perBankRdBursts::2 9002 # Per bank write bursts +system.physmem.perBankRdBursts::2 9003 # Per bank write bursts system.physmem.perBankRdBursts::3 8675 # Per bank write bursts -system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::4 9453 # Per bank write bursts system.physmem.perBankRdBursts::5 9352 # Per bank write bursts -system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::6 8945 # Per bank write bursts system.physmem.perBankRdBursts::7 8102 # Per bank write bursts system.physmem.perBankRdBursts::8 8582 # Per bank write bursts -system.physmem.perBankRdBursts::9 8671 # Per bank write bursts +system.physmem.perBankRdBursts::9 8674 # Per bank write bursts system.physmem.perBankRdBursts::10 8765 # Per bank write bursts -system.physmem.perBankRdBursts::11 9475 # Per bank write bursts -system.physmem.perBankRdBursts::12 9349 # Per bank write bursts -system.physmem.perBankRdBursts::13 9515 # Per bank write bursts -system.physmem.perBankRdBursts::14 8723 # Per bank write bursts -system.physmem.perBankRdBursts::15 9120 # Per bank write bursts -system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts +system.physmem.perBankRdBursts::12 9348 # Per bank write bursts +system.physmem.perBankRdBursts::13 9513 # Per bank write bursts +system.physmem.perBankRdBursts::14 8719 # Per bank write bursts +system.physmem.perBankRdBursts::15 9123 # Per bank write bursts +system.physmem.perBankWrBursts::0 6195 # Per bank write bursts system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6010 # Per bank write bursts +system.physmem.perBankWrBursts::2 6011 # Per bank write bursts system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6183 # Per bank write bursts -system.physmem.perBankWrBursts::5 6186 # Per bank write bursts +system.physmem.perBankWrBursts::4 6181 # Per bank write bursts +system.physmem.perBankWrBursts::5 6188 # Per bank write bursts system.physmem.perBankWrBursts::6 6015 # Per bank write bursts -system.physmem.perBankWrBursts::7 5498 # Per bank write bursts -system.physmem.perBankWrBursts::8 5738 # Per bank write bursts -system.physmem.perBankWrBursts::9 5829 # Per bank write bursts +system.physmem.perBankWrBursts::7 5499 # Per bank write bursts +system.physmem.perBankWrBursts::8 5743 # Per bank write bursts +system.physmem.perBankWrBursts::9 5830 # Per bank write bursts system.physmem.perBankWrBursts::10 5965 # Per bank write bursts system.physmem.perBankWrBursts::11 6463 # Per bank write bursts -system.physmem.perBankWrBursts::12 6313 # Per bank write bursts +system.physmem.perBankWrBursts::12 6312 # Per bank write bursts system.physmem.perBankWrBursts::13 6285 # Per bank write bursts -system.physmem.perBankWrBursts::14 6005 # Per bank write bursts -system.physmem.perBankWrBursts::15 6083 # Per bank write bursts +system.physmem.perBankWrBursts::14 6003 # Per bank write bursts +system.physmem.perBankWrBursts::15 6086 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363605269500 # Total gap between requests +system.physmem.totGap 363599476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144121 # Read request sizes (log2) +system.physmem.readPktSize::6 144124 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96704 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96709 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,53 +193,55 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads @@ -249,13 +251,13 @@ system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Wr system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads -system.physmem.totQLat 1541292750 # Total ticks spent queuing -system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads +system.physmem.totQLat 1538433000 # Total ticks spent queuing +system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s @@ -265,50 +267,50 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing -system.physmem.readRowHits 110876 # Number of row buffer hits during reads -system.physmem.writeRowHits 64571 # Number of row buffer hits during writes +system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing +system.physmem.readRowHits 110870 # Number of row buffer hits during reads +system.physmem.writeRowHits 64542 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes -system.physmem.avgGap 1509831.91 # Average gap between requests -system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.768610 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes +system.physmem.avgGap 1509757.70 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.804658 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.641324 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.633389 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131896308 # Number of BP lookups -system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits +system.cpu.branchPred.lookups 131895360 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,98 +429,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727210591 # number of cpu cycles simulated +system.cpu.numCycles 727199005 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435524 # CPI: cycles per instruction -system.cpu.ipc 0.696610 # IPC: instructions per cycle -system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139971 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks. +system.cpu.cpi 1.435501 # CPI: cycles per instruction +system.cpu.ipc 0.696621 # IPC: instructions per cycle +system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139984 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits -system.cpu.dcache.overall_hits::total 168191897 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses -system.cpu.dcache.overall_misses::total 1555488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits +system.cpu.dcache.overall_hits::total 168191562 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses +system.cpu.dcache.overall_misses::total 1555482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -527,111 +529,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks -system.cpu.dcache.writebacks::total 1068574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks +system.cpu.dcache.writebacks::total 1068583 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17719 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17702 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398694449 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398694449 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199317838 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199317838 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199317838 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199317838 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199317838 # number of overall hits -system.cpu.icache.overall_hits::total 199317838 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19591 # number of overall misses -system.cpu.icache.overall_misses::total 19591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 490899000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 490899000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 490899000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 490899000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 490899000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 490899000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199337429 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199337429 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19574 # number of overall misses +system.cpu.icache.overall_misses::total 19574 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 491333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 491333500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 491333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 491333500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 491333500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 491333500 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.175284 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.175284 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050631 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050631 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175284 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122989 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175284 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122989 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123868 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78407.432386 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78407.432386 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79364.471000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79364.471000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82301.792879 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79507.686971 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,8 +772,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96704 # number of writebacks -system.cpu.l2cache.writebacks::total 96704 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96709 # number of writebacks +system.cpu.l2cache.writebacks::total 96709 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits @@ -782,114 +784,120 @@ system.cpu.l2cache.demand_mshr_hits::total 16 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3429 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3429 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3429 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 144124 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6897453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6897453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237701500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237701500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2882229000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2882229000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237701500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9779682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10017383500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237701500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9779682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10017383500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282894 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282894 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.175181 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050613 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050613 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123855 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123855 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111367 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43292 # Transaction distribution -system.membus.trans_dist::Writeback 96704 # Transaction distribution -system.membus.trans_dist::CleanEvict 13244 # Transaction distribution +system.membus.trans_dist::ReadResp 43295 # Transaction distribution +system.membus.trans_dist::Writeback 96709 # Transaction distribution +system.membus.trans_dist::CleanEvict 13242 # Transaction distribution system.membus.trans_dist::ReadExReq 100829 # Transaction distribution system.membus.trans_dist::ReadExResp 100829 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254069 # Request fanout histogram +system.membus.snoop_fanout::samples 254075 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254069 # Request fanout histogram -system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 254075 # Request fanout histogram +system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c93b4b47a..153b00611 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233332 # Number of seconds simulated -sim_ticks 233331881000 # Number of ticks simulated -final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233306 # Number of seconds simulated +sim_ticks 233306027000 # Number of ticks simulated +final_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137799 # Simulator instruction rate (inst/s) -host_op_rate 149285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63638999 # Simulator tick rate (ticks/s) -host_mem_usage 320760 # Number of bytes of host memory used -host_seconds 3666.49 # Real time elapsed on the host +host_inst_rate 128535 # Simulator instruction rate (inst/s) +host_op_rate 139249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59354207 # Simulator tick rate (ticks/s) +host_mem_usage 322028 # Number of bytes of host memory used +host_seconds 3930.74 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory -system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory -system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412225 # Number of read requests accepted -system.physmem.writeReqs 292410 # Number of write requests accepted -system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue -system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26528 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25303 # Per bank write bursts -system.physmem.perBankRdBursts::3 24713 # Per bank write bursts -system.physmem.perBankRdBursts::4 27194 # Per bank write bursts -system.physmem.perBankRdBursts::5 26607 # Per bank write bursts -system.physmem.perBankRdBursts::6 24941 # Per bank write bursts -system.physmem.perBankRdBursts::7 24442 # Per bank write bursts -system.physmem.perBankRdBursts::8 25767 # Per bank write bursts -system.physmem.perBankRdBursts::9 24723 # Per bank write bursts -system.physmem.perBankRdBursts::10 25091 # Per bank write bursts -system.physmem.perBankRdBursts::11 26187 # Per bank write bursts -system.physmem.perBankRdBursts::12 26462 # Per bank write bursts -system.physmem.perBankRdBursts::13 26013 # Per bank write bursts -system.physmem.perBankRdBursts::14 25052 # Per bank write bursts -system.physmem.perBankRdBursts::15 25510 # Per bank write bursts -system.physmem.perBankWrBursts::0 18779 # Per bank write bursts -system.physmem.perBankWrBursts::1 18326 # Per bank write bursts -system.physmem.perBankWrBursts::2 18027 # Per bank write bursts -system.physmem.perBankWrBursts::3 17939 # Per bank write bursts -system.physmem.perBankWrBursts::4 18703 # Per bank write bursts -system.physmem.perBankWrBursts::5 18353 # Per bank write bursts -system.physmem.perBankWrBursts::6 17755 # Per bank write bursts -system.physmem.perBankWrBursts::7 17808 # Per bank write bursts -system.physmem.perBankWrBursts::8 18074 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory +system.physmem.bytes_read::total 26349056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory +system.physmem.bytes_written::total 18702784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411704 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292231 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411704 # Number of read requests accepted +system.physmem.writeReqs 292231 # Number of write requests accepted +system.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue +system.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26604 # Per bank write bursts +system.physmem.perBankRdBursts::1 25479 # Per bank write bursts +system.physmem.perBankRdBursts::2 25122 # Per bank write bursts +system.physmem.perBankRdBursts::3 24753 # Per bank write bursts +system.physmem.perBankRdBursts::4 27168 # Per bank write bursts +system.physmem.perBankRdBursts::5 26312 # Per bank write bursts +system.physmem.perBankRdBursts::6 25243 # Per bank write bursts +system.physmem.perBankRdBursts::7 24096 # Per bank write bursts +system.physmem.perBankRdBursts::8 25848 # Per bank write bursts +system.physmem.perBankRdBursts::9 24676 # Per bank write bursts +system.physmem.perBankRdBursts::10 25150 # Per bank write bursts +system.physmem.perBankRdBursts::11 26103 # Per bank write bursts +system.physmem.perBankRdBursts::12 26513 # Per bank write bursts +system.physmem.perBankRdBursts::13 25940 # Per bank write bursts +system.physmem.perBankRdBursts::14 25062 # Per bank write bursts +system.physmem.perBankRdBursts::15 25488 # Per bank write bursts +system.physmem.perBankWrBursts::0 18828 # Per bank write bursts +system.physmem.perBankWrBursts::1 18294 # Per bank write bursts +system.physmem.perBankWrBursts::2 17806 # Per bank write bursts +system.physmem.perBankWrBursts::3 17978 # Per bank write bursts +system.physmem.perBankWrBursts::4 18719 # Per bank write bursts +system.physmem.perBankWrBursts::5 18281 # Per bank write bursts +system.physmem.perBankWrBursts::6 17995 # Per bank write bursts +system.physmem.perBankWrBursts::7 17635 # Per bank write bursts +system.physmem.perBankWrBursts::8 18144 # Per bank write bursts system.physmem.perBankWrBursts::9 17824 # Per bank write bursts -system.physmem.perBankWrBursts::10 18093 # Per bank write bursts -system.physmem.perBankWrBursts::11 18724 # Per bank write bursts -system.physmem.perBankWrBursts::12 18814 # Per bank write bursts -system.physmem.perBankWrBursts::13 18339 # Per bank write bursts -system.physmem.perBankWrBursts::14 18411 # Per bank write bursts -system.physmem.perBankWrBursts::15 18403 # Per bank write bursts +system.physmem.perBankWrBursts::10 18107 # Per bank write bursts +system.physmem.perBankWrBursts::11 18749 # Per bank write bursts +system.physmem.perBankWrBursts::12 18847 # Per bank write bursts +system.physmem.perBankWrBursts::13 18260 # Per bank write bursts +system.physmem.perBankWrBursts::14 18418 # Per bank write bursts +system.physmem.perBankWrBursts::15 18313 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233331863000 # Total gap between requests +system.physmem.totGap 233306009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412225 # Read request sizes (log2) +system.physmem.readPktSize::6 411704 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292410 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292231 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads -system.physmem.totQLat 9022211140 # Total ticks spent queuing -system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads +system.physmem.totQLat 9105020732 # Total ticks spent queuing +system.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing -system.physmem.readRowHits 299444 # Number of row buffer hits during reads -system.physmem.writeRowHits 95740 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes -system.physmem.avgGap 331138.62 # Average gap between requests -system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.458661 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states -system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing +system.physmem.readRowHits 299267 # Number of row buffer hits during reads +system.physmem.writeRowHits 95628 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 331431.18 # Average gap between requests +system.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.246471 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states +system.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.198461 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states -system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states +system.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ) +system.physmem_1.averagePower 722.989890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states +system.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175090137 # Number of BP lookups -system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits +system.cpu.branchPred.lookups 175092094 # Number of BP lookups +system.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83876326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466663763 # number of cpu cycles simulated +system.cpu.numCycles 466612055 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287098365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276695654 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued -system.cpu.iq.rate 1.307684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610256171 # Type of FU issued +system.cpu.iq.rate 1.307845 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487489 # number of nop insts executed -system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed -system.cpu.iew.exec_branches 131372234 # Number of branches executed -system.cpu.iew.exec_stores 60956689 # Number of stores executed -system.cpu.iew.exec_rate 1.284432 # Inst execution rate -system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349907425 # num instructions producing a value -system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value +system.cpu.iew.exec_nop 1487415 # number of nop insts executed +system.cpu.iew.exec_refs 190539133 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373270 # Number of branches executed +system.cpu.iew.exec_stores 60964533 # Number of stores executed +system.cpu.iew.exec_rate 1.284586 # Inst execution rate +system.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594986597 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349903865 # num instructions producing a value +system.cpu.iew.wb_consumers 570650112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back +system.cpu.iew.wb_rate 1.275121 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,182 +685,182 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093571715 # The number of ROB reads -system.cpu.rob.rob_writes 1334590067 # The number of ROB writes -system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1093559316 # The number of ROB reads +system.cpu.rob.rob_writes 1334598854 # The number of ROB writes +system.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611088796 # number of integer regfile reads -system.cpu.int_regfile_writes 328119086 # number of integer regfile writes +system.cpu.cpi 0.923550 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082779 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611100755 # number of integer regfile reads +system.cpu.int_regfile_writes 328116502 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes -system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads +system.cpu.cc_regfile_writes 376538117 # number of cc regfile writes +system.cpu.misc_regfile_reads 217976814 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820945 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631358 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169354520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821457 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.023782 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498530000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820876 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356242117 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356242117 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648793 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648793 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51725790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51725790 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166374583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166374583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166377369 # number of overall hits -system.cpu.dcache.overall_hits::total 166377369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4842267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4842267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2513516 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2513516 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits +system.cpu.dcache.overall_hits::total 166378633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7355783 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7355783 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7355794 # number of overall misses -system.cpu.dcache.overall_misses::total 7355794 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56187510500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56187510500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19050466441 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19050466441 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1271500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1271500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75237976941 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75237976941 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75237976941 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75237976941 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119491060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119491060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses +system.cpu.dcache.overall_misses::total 7357619 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173730366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173730366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173733163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173733163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046341 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042340 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042340 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042340 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7579.210334 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7579.210334 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10228.411706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10228.396410 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 931670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221105 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.213699 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2357131 # number of writebacks -system.cpu.dcache.writebacks::total 2357131 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540406 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540406 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1993903 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1993903 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks +system.cpu.dcache.writebacks::total 2352880 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4534309 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4534309 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4534309 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4534309 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821484 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821484 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28687651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28687651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4620185994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4620185994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 674500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 674500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307836994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33307836994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33308511494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33308511494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # 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mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8891.590461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8891.590461 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67450 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67450 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id @@ -867,202 +868,202 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 119 system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473514607 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473514607 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236637753 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236637753 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236637753 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236637753 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236637753 # number of overall hits -system.cpu.icache.overall_hits::total 236637753 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82554 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82554 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82554 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82554 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82554 # number of overall misses -system.cpu.icache.overall_misses::total 82554 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1566745159 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1566745159 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1566745159 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1566745159 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1566745159 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1566745159 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236720307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236720307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236720307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236720307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236720307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236720307 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473512362 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits +system.cpu.icache.overall_hits::total 236636536 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses +system.cpu.icache.overall_misses::total 82647 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18978.428168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18978.428168 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 198034 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7006 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.266343 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18934.319128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18934.319128 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18934.319128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18934.319128 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 190768 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6939 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.492146 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8560 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8560 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8560 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8560 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8560 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8560 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73994 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73994 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73994 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73994 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73994 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73994 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1278636265 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1278636265 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1278636265 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1278636265 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1278636265 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1278636265 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8650 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8650 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8650 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8650 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8650 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8650 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 73997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 73997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 73997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 73997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 73997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1275745779 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1275745779 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1275745779 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1275745779 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1275745779 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1275745779 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17280.269549 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17280.269549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17240.506764 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17240.506764 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8511909 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8513040 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 167 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8512194 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8513359 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 195 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743544 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401080 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15418.085448 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5068240 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.141911 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34601120500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8466.854939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 473.689855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4911.860449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1565.680205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.516776 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1090 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15247 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 243 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 815 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1541 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3332 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930603 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 93191002 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 93191002 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2357131 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2357131 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 25 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 25 # 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number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 718484 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 717772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 408504 # Transaction distribution -system.membus.trans_dist::Writeback 292410 # Transaction distribution -system.membus.trans_dist::CleanEvict 103085 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3721 # Transaction distribution -system.membus.trans_dist::ReadExResp 3721 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 408044 # Transaction distribution +system.membus.trans_dist::Writeback 292231 # Transaction distribution +system.membus.trans_dist::CleanEvict 102781 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 3660 # Transaction distribution +system.membus.trans_dist::ReadExResp 3660 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 807723 # Request fanout histogram +system.membus.snoop_fanout::samples 806718 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 807723 # Request fanout histogram -system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 806718 # Request fanout histogram +system.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 7568a8b98..ad7524f92 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707533 # Number of seconds simulated -sim_ticks 707533448500 # Number of ticks simulated -final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707537 # Number of seconds simulated +sim_ticks 707536959500 # Number of ticks simulated +final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1147583 # Simulator instruction rate (inst/s) -host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1607870578 # Simulator tick rate (ticks/s) -host_mem_usage 316160 # Number of bytes of host memory used -host_seconds 440.04 # Real time elapsed on the host +host_inst_rate 1064510 # Simulator instruction rate (inst/s) +host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1491485099 # Simulator tick rate (ticks/s) +host_mem_usage 319084 # Number of bytes of host memory used +host_seconds 474.38 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 139793 # Nu system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415066897 # number of cpu cycles simulated +system.cpu.numCycles 1415073919 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109779 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -485,14 +485,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) @@ -523,14 +523,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,14 +559,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses @@ -585,15 +585,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution @@ -609,14 +615,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 109779 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) @@ -646,9 +652,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 251058 # Request fanout histogram -system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c2ca7f71b..987362254 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403707 # Number of seconds simulated -sim_ticks 403706643500 # Number of ticks simulated -final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403931 # Number of seconds simulated +sim_ticks 403931323500 # Number of ticks simulated +final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76271 # Simulator instruction rate (inst/s) -host_op_rate 141034 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37237827 # Simulator tick rate (ticks/s) -host_mem_usage 423672 # Number of bytes of host memory used -host_seconds 10841.31 # Real time elapsed on the host +host_inst_rate 95186 # Simulator instruction rate (inst/s) +host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46498470 # Simulator tick rate (ticks/s) +host_mem_usage 433064 # Number of bytes of host memory used +host_seconds 8686.98 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory -system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386152 # Number of read requests accepted -system.physmem.writeReqs 294833 # Number of write requests accepted -system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory +system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory +system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386228 # Number of read requests accepted +system.physmem.writeReqs 294838 # Number of write requests accepted +system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue +system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24028 # Per bank write bursts -system.physmem.perBankRdBursts::1 26400 # Per bank write bursts -system.physmem.perBankRdBursts::2 24980 # Per bank write bursts -system.physmem.perBankRdBursts::3 24600 # Per bank write bursts -system.physmem.perBankRdBursts::4 23395 # Per bank write bursts -system.physmem.perBankRdBursts::5 23728 # Per bank write bursts -system.physmem.perBankRdBursts::6 24595 # Per bank write bursts -system.physmem.perBankRdBursts::7 24357 # Per bank write bursts -system.physmem.perBankRdBursts::8 23707 # Per bank write bursts -system.physmem.perBankRdBursts::9 23543 # Per bank write bursts -system.physmem.perBankRdBursts::10 24760 # Per bank write bursts -system.physmem.perBankRdBursts::11 23969 # Per bank write bursts -system.physmem.perBankRdBursts::12 23156 # Per bank write bursts -system.physmem.perBankRdBursts::13 22899 # Per bank write bursts -system.physmem.perBankRdBursts::14 23872 # Per bank write bursts -system.physmem.perBankRdBursts::15 23880 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 19929 # Per bank write bursts -system.physmem.perBankWrBursts::2 19196 # Per bank write bursts -system.physmem.perBankWrBursts::3 18982 # Per bank write bursts -system.physmem.perBankWrBursts::4 18144 # Per bank write bursts -system.physmem.perBankWrBursts::5 18488 # Per bank write bursts -system.physmem.perBankWrBursts::6 19136 # Per bank write bursts -system.physmem.perBankWrBursts::7 19077 # Per bank write bursts -system.physmem.perBankWrBursts::8 18672 # Per bank write bursts -system.physmem.perBankWrBursts::9 17940 # Per bank write bursts -system.physmem.perBankWrBursts::10 18886 # Per bank write bursts -system.physmem.perBankWrBursts::11 17736 # Per bank write bursts -system.physmem.perBankWrBursts::12 17372 # Per bank write bursts -system.physmem.perBankWrBursts::13 16987 # Per bank write bursts -system.physmem.perBankWrBursts::14 17811 # Per bank write bursts -system.physmem.perBankWrBursts::15 17848 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24062 # Per bank write bursts +system.physmem.perBankRdBursts::1 26430 # Per bank write bursts +system.physmem.perBankRdBursts::2 24903 # Per bank write bursts +system.physmem.perBankRdBursts::3 24577 # Per bank write bursts +system.physmem.perBankRdBursts::4 23181 # Per bank write bursts +system.physmem.perBankRdBursts::5 23704 # Per bank write bursts +system.physmem.perBankRdBursts::6 24550 # Per bank write bursts +system.physmem.perBankRdBursts::7 24303 # Per bank write bursts +system.physmem.perBankRdBursts::8 23663 # Per bank write bursts +system.physmem.perBankRdBursts::9 23568 # Per bank write bursts +system.physmem.perBankRdBursts::10 24789 # Per bank write bursts +system.physmem.perBankRdBursts::11 23975 # Per bank write bursts +system.physmem.perBankRdBursts::12 23330 # Per bank write bursts +system.physmem.perBankRdBursts::13 22932 # Per bank write bursts +system.physmem.perBankRdBursts::14 24089 # Per bank write bursts +system.physmem.perBankRdBursts::15 23873 # Per bank write bursts +system.physmem.perBankWrBursts::0 18604 # Per bank write bursts +system.physmem.perBankWrBursts::1 19922 # Per bank write bursts +system.physmem.perBankWrBursts::2 19191 # Per bank write bursts +system.physmem.perBankWrBursts::3 18985 # Per bank write bursts +system.physmem.perBankWrBursts::4 18090 # Per bank write bursts +system.physmem.perBankWrBursts::5 18485 # Per bank write bursts +system.physmem.perBankWrBursts::6 19138 # Per bank write bursts +system.physmem.perBankWrBursts::7 19082 # Per bank write bursts +system.physmem.perBankWrBursts::8 18642 # Per bank write bursts +system.physmem.perBankWrBursts::9 17946 # Per bank write bursts +system.physmem.perBankWrBursts::10 18887 # Per bank write bursts +system.physmem.perBankWrBursts::11 17737 # Per bank write bursts +system.physmem.perBankWrBursts::12 17398 # Per bank write bursts +system.physmem.perBankWrBursts::13 16988 # Per bank write bursts +system.physmem.perBankWrBursts::14 17875 # Per bank write bursts +system.physmem.perBankWrBursts::15 17843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403706602500 # Total gap between requests +system.physmem.totGap 403931308500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386152 # Read request sizes (log2) +system.physmem.readPktSize::6 386228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294833 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294838 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads -system.physmem.totQLat 4289653250 # Total ticks spent queuing -system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads +system.physmem.totQLat 4291077750 # Total ticks spent queuing +system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing -system.physmem.readRowHits 317973 # Number of row buffer hits during reads -system.physmem.writeRowHits 215927 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing +system.physmem.readRowHits 317989 # Number of row buffer hits during reads +system.physmem.writeRowHits 215873 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes -system.physmem.avgGap 592827.45 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.702062 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states +system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes +system.physmem.avgGap 593086.88 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.623817 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.698075 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states +system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.740141 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219316547 # Number of BP lookups -system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits +system.cpu.branchPred.lookups 219314839 # Number of BP lookups +system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807413288 # number of cpu cycles simulated +system.cpu.numCycles 807862648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7280270 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11520759 42.69% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued -system.cpu.iq.rate 2.215765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813294148 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12920 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186084957 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued +system.cpu.iq.rate 2.214396 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123036250 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211434 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 371907 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51657418 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23176 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1099 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8890570 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97719419 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6134161 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023187408 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507138407 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200817604 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7250 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1817237 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3413935 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 371907 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4848104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4143061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8991165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1770021029 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423153321 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19017178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590346194 # number of memory reference insts executed -system.cpu.iew.exec_branches 168990321 # Number of branches executed -system.cpu.iew.exec_stores 167192873 # Number of stores executed -system.cpu.iew.exec_rate 2.192212 # Inst execution rate -system.cpu.iew.wb_sent 1766892997 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762390652 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339756908 # num instructions producing a value -system.cpu.iew.wb_consumers 2049972766 # num instructions consuming a value +system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed +system.cpu.iew.exec_branches 168980249 # Number of branches executed +system.cpu.iew.exec_stores 167188538 # Number of stores executed +system.cpu.iew.exec_rate 2.190883 # Inst execution rate +system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339663552 # num instructions producing a value +system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.182762 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653549 # average fanout of values written-back +system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 494260386 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8618895 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 739988037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.066234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575521 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 275878158 37.28% 37.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172126899 23.26% 60.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55937459 7.56% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25876597 3.50% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26568843 3.59% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,344 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78508765 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684728359 # The number of ROB reads -system.cpu.rob.rob_writes 4113896609 # The number of ROB writes -system.cpu.timesIdled 2328 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 201987 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2685200393 # The number of ROB reads +system.cpu.rob.rob_writes 4113829657 # The number of ROB writes +system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.024106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722667059 # number of integer regfile reads -system.cpu.int_regfile_writes 1435857659 # number of integer regfile writes -system.cpu.fp_regfile_reads 5817 # number of floating regfile reads -system.cpu.fp_regfile_writes 496 # number of floating regfile writes -system.cpu.cc_regfile_reads 596670071 # number of cc regfile reads -system.cpu.cc_regfile_writes 405476387 # number of cc regfile writes -system.cpu.misc_regfile_reads 971632449 # number of misc regfile reads +system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads +system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads +system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes +system.cpu.fp_regfile_reads 5969 # number of floating regfile reads +system.cpu.fp_regfile_writes 521 # number of floating regfile writes +system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads +system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes +system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530789 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.813367 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381875640 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534885 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.648112 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530897 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813367 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772839713 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772839713 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233227342 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233227342 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173773 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173773 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381401115 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381401115 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381401115 # number of overall hits -system.cpu.dcache.overall_hits::total 381401115 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2764870 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2764870 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986429 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986429 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3751299 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751299 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751299 # number of overall misses -system.cpu.dcache.overall_misses::total 3751299 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58802289500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58802289500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31059853996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31059853996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89862143496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89862143496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89862143496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89862143496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235992212 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235992212 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits +system.cpu.dcache.overall_hits::total 381356978 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses +system.cpu.dcache.overall_misses::total 3761732 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385152414 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385152414 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385152414 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385152414 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011716 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011716 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23954.940274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23954.940274 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9795 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1045 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.373206 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330774 # number of writebacks -system.cpu.dcache.writebacks::total 2330774 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000095 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1000095 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19339 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19339 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1019434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1019434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1019434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1019434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967090 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 967090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2731865 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2731865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2731865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2731865 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33541518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33541518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29840523997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29840523997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63382041997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63382041997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63382041997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63382041997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19006.115794 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19006.115794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30855.994785 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30855.994785 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks +system.cpu.dcache.writebacks::total 2330787 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6640 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.923261 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170565267 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8248 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20679.591052 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6655 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.923261 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506798 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506798 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341757570 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341757570 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170568161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170568161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170568161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170568161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170568161 # number of overall hits -system.cpu.icache.overall_hits::total 170568161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 207953 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 207953 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 207953 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 207953 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 207953 # number of overall misses -system.cpu.icache.overall_misses::total 207953 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1300977000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1300977000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1300977000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1300977000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1300977000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1300977000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170776114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170776114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170776114 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170776114 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170776114 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170776114 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001218 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001218 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001218 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001218 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001218 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001218 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6256.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6256.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6256.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6256.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 718 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits +system.cpu.icache.overall_hits::total 170580521 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses +system.cpu.icache.overall_misses::total 208882 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2609 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2609 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2609 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2609 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2609 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2609 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 976991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 976991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 976991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 976991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 976991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 976991000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4757.825892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4757.825892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 353471 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29618.497788 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3892615 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385807 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.089540 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189374171500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20946.463818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.310071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8431.723899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639235 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007334 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903885 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32336 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 353544 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13380 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986816 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43290247 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43290247 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2330774 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330774 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563945 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563945 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588121 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588121 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2152066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2156920 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2152066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2156920 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 195142 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 195142 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206554 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206554 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3382 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3382 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176265 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176265 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382819 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386201 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382819 # number of overall misses -system.cpu.l2cache.overall_misses::total 386201 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13466000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13466000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16374024500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16374024500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275872500 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 550579 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 551588 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179644 # Transaction distribution -system.membus.trans_dist::Writeback 294833 # Transaction distribution -system.membus.trans_dist::CleanEvict 57066 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution -system.membus.trans_dist::ReadExReq 206507 # Transaction distribution -system.membus.trans_dist::ReadExResp 206507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179703 # Transaction distribution +system.membus.trans_dist::Writeback 294838 # Transaction distribution +system.membus.trans_dist::CleanEvict 57117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution +system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution +system.membus.trans_dist::ReadExReq 206523 # Transaction distribution +system.membus.trans_dist::ReadExResp 206523 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 933240 # Request fanout histogram +system.membus.snoop_fanout::samples 934311 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 933240 # Request fanout histogram -system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 934311 # Request fanout histogram +system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7244d6f89..22535a108 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647861 # Nu sim_ticks 1647861059500 # Number of ticks simulated final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708384 # Simulator instruction rate (inst/s) -host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1411719986 # Simulator tick rate (ticks/s) -host_mem_usage 323600 # Number of bytes of host memory used -host_seconds 1167.27 # Real time elapsed on the host +host_inst_rate 657040 # Simulator instruction rate (inst/s) +host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1309397988 # Simulator tick rate (ticks/s) +host_mem_usage 327616 # Number of bytes of host memory used +host_seconds 1258.49 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -455,6 +455,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution @@ -470,15 +476,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 348182 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 988455083..e60710ec5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu sim_ticks 225710988500 # Number of ticks simulated final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225638 # Simulator instruction rate (inst/s) -host_op_rate 225638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127748919 # Simulator tick rate (ticks/s) -host_mem_usage 297512 # Number of bytes of host memory used -host_seconds 1766.83 # Real time elapsed on the host +host_inst_rate 311102 # Simulator instruction rate (inst/s) +host_op_rate 311102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176136084 # Simulator tick rate (ticks/s) +host_mem_usage 304484 # Number of bytes of host memory used +host_seconds 1281.46 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -661,6 +661,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 13288 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3958 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution @@ -676,15 +682,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 49a2168d9..0e0bba79f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.067874 # Nu sim_ticks 67874346000 # Number of ticks simulated final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172313 # Simulator instruction rate (inst/s) -host_op_rate 172313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31140671 # Simulator tick rate (ticks/s) -host_mem_usage 298536 # Number of bytes of host memory used -host_seconds 2179.60 # Real time elapsed on the host +host_inst_rate 238872 # Simulator instruction rate (inst/s) +host_op_rate 238872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43169272 # Simulator tick rate (ticks/s) +host_mem_usage 305488 # Number of bytes of host memory used +host_seconds 1572.28 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -955,6 +955,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 11134 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution @@ -970,15 +976,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 8c86953a0..b9717df42 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335097500 # Number of ticks simulated final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1293186 # Simulator instruction rate (inst/s) -host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1840317995 # Simulator tick rate (ticks/s) -host_mem_usage 300812 # Number of bytes of host memory used -host_seconds 308.28 # Real time elapsed on the host +host_inst_rate 1348015 # Simulator instruction rate (inst/s) +host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1918345002 # Simulator tick rate (ticks/s) +host_mem_usage 301916 # Number of bytes of host memory used +host_seconds 295.74 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -472,6 +472,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution @@ -487,15 +493,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 333ae52c9..5974a793e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215506 # Number of seconds simulated -sim_ticks 215505832500 # Number of ticks simulated -final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215510 # Number of seconds simulated +sim_ticks 215510486500 # Number of ticks simulated +final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114925 # Simulator instruction rate (inst/s) -host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90709005 # Simulator tick rate (ticks/s) -host_mem_usage 317788 # Number of bytes of host memory used -host_seconds 2375.79 # Real time elapsed on the host +host_inst_rate 166248 # Simulator instruction rate (inst/s) +host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131220473 # Simulator tick rate (ticks/s) +host_mem_usage 326292 # Number of bytes of host memory used +host_seconds 1642.35 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215505593500 # Total gap between requests +system.physmem.totGap 215510247500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 52046750 # Total ticks spent queuing -system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation +system.physmem.totQLat 52026250 # Total ticks spent queuing +system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6062 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28423317.53 # Average gap between requests -system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423931.35 # Average gap between requests +system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.715971 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806188 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.792285 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816945 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.lookups 32816918 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431011665 # number of cpu cycles simulated +system.cpu.numCycles 431020973 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578578 # CPI: cycles per instruction -system.cpu.ipc 0.633481 # IPC: instructions per cycle -system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578612 # CPI: cycles per instruction +system.cpu.ipc 0.633468 # IPC: instructions per cycle +system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -404,42 +404,42 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits -system.cpu.dcache.overall_hits::total 168693090 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits +system.cpu.dcache.overall_hits::total 168693094 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses -system.cpu.dcache.overall_misses::total 7292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508 system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36873 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses -system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits -system.cpu.icache.overall_hits::total 72548906 # number of overall hits +system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits +system.cpu.icache.overall_hits::total 72548791 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses system.cpu.icache.overall_misses::total 38810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38810 system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 7626 # nu system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.176035 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7582 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c456278d9..b3c953357 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112687 # Number of seconds simulated -sim_ticks 112687034500 # Number of ticks simulated -final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112728 # Number of seconds simulated +sim_ticks 112728298500 # Number of ticks simulated +final_tick 112728298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126437 # Simulator instruction rate (inst/s) -host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52182660 # Simulator tick rate (ticks/s) -host_mem_usage 327844 # Number of bytes of host memory used -host_seconds 2159.47 # Real time elapsed on the host +host_inst_rate 116763 # Simulator instruction rate (inst/s) +host_op_rate 140187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48207604 # Simulator tick rate (ticks/s) +host_mem_usage 330392 # Number of bytes of host memory used +host_seconds 2338.39 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory -system.physmem.bytes_read::total 468672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7323 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169408 # Number of bytes read from this memory +system.physmem.bytes_read::total 469184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2647 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7331 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1658927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1000352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1502799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4162078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1658927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1000352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1502799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4162078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7331 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7331 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,16 +50,16 @@ system.physmem.perBankRdBursts::1 789 # Pe system.physmem.perBankRdBursts::2 601 # Per bank write bursts system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::5 345 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 251 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts -system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::14 620 # Per bank write bursts system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112686876000 # Total gap between requests +system.physmem.totGap 112728140000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7323 # Read request sizes (log2) +system.physmem.readPktSize::6 7331 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,20 +94,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 95174041 # Total ticks spent queuing -system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.670794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.560456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.691004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 480 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 312 22.72% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 141 10.27% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.75% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.01% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.50% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.97% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 208 15.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.physmem.totQLat 90206647 # Total ticks spent queuing +system.physmem.totMemAccLat 227662897 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12304.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31054.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s @@ -218,50 +218,50 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5943 # Number of row buffer hits during reads +system.physmem.readRowHits 5948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15388075.38 # Average gap between requests -system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 15376911.74 # Average gap between requests +system.physmem.pageHitRate 81.13 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 28618200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.158858 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states -system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_0.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3214163025 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64813639500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75426287190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.136639 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107820696894 # Time in different power states +system.physmem_0.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1137632606 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 5511240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3007125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.247655 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states -system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_1.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3285750465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64750835250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75435654000 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.219817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107714946135 # Time in different power states +system.physmem_1.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1243230865 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37743135 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits +system.cpu.branchPred.lookups 37743002 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164593 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746138 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663724 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299181 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.688796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223599 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225374070 # number of cpu cycles simulated +system.cpu.numCycles 225456598 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12486047 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334063522 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37743002 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210891035 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510673 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2507 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89094273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21774 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.799914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229503 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51412756 22.84% 22.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42958324 19.08% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30027813 13.34% 55.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100737290 44.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167407 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.481720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27896248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63927882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108602791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23088664 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620598 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135173 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363542969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170181 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45231914 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 18002517 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341926 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113354912 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46584316 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355763735 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6625666 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177937 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803151 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21129906 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2817742 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401676 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534003745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350242817 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31171625 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55451024 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416595 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252669 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346437634 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73749076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 225136183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.538791 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099493 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40701776 18.08% 18.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78366146 34.81% 52.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60939580 27.07% 79.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34977344 15.54% 95.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9507598 4.22% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 632530 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11209 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225136183 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9586225 7.69% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7350 0.01% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 132929 0.11% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93071 0.07% 8.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 61949 0.05% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719141 0.58% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 303244 0.24% 8.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683031 0.55% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53752847 43.14% 52.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59000415 47.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655046 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148359 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798342 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667218 2.50% 37.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592517 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930304 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182327 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148965 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923294 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883494 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued -system.cpu.iq.rate 1.537170 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346437634 # Type of FU issued +system.cpu.iq.rate 1.536605 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124595964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.359649 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757212589 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223259855 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287696302 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127019209 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117423886 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303336303 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167697295 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5085757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684320 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10256 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122735 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332541 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281560 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416595 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498352 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 339026 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10256 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659723 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342447875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703562 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989759 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752726 # Number of branches executed -system.cpu.iew.exec_stores 84587405 # Number of stores executed -system.cpu.iew.exec_rate 1.519468 # Inst execution rate -system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153662647 # num instructions producing a value -system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value +system.cpu.iew.exec_refs 175290975 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752712 # Number of branches executed +system.cpu.iew.exec_stores 84587413 # Number of stores executed +system.cpu.iew.exec_rate 1.518908 # Inst execution rate +system.cpu.iew.wb_sent 340942422 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340683741 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153622639 # num instructions producing a value +system.cpu.iew.wb_consumers 266573014 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511083 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082594 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611400 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221410973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.051639 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87667745 39.60% 39.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70465931 31.83% 71.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20808534 9.40% 80.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13377083 6.04% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8762034 3.96% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4538069 2.05% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3005918 1.36% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2461295 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10324364 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221410973 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,32 +654,32 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561900565 # The number of ROB reads -system.cpu.rob.rob_writes 705520050 # The number of ROB writes -system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10324364 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561978894 # The number of ROB reads +system.cpu.rob.rob_writes 705518745 # The number of ROB writes +system.cpu.timesIdled 51182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331332035 # number of integer regfile reads -system.cpu.int_regfile_writes 136939352 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads -system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads -system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads +system.cpu.cpi 0.825736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825736 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211041 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211041 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331297 # number of integer regfile reads +system.cpu.int_regfile_writes 136939218 # number of integer regfile writes +system.cpu.fp_regfile_reads 187106677 # number of floating regfile reads +system.cpu.fp_regfile_writes 132176732 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297128117 # number of cc regfile reads +system.cpu.cc_regfile_writes 80240781 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183123878 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533845 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1533840 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843429 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163621677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.638944 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82703000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843429 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -688,148 +688,148 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336594804 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336594804 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82588364 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82588364 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941030 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70477 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70477 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits -system.cpu.dcache.overall_hits::total 163621011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163529394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163529394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163599871 # number of overall hits +system.cpu.dcache.overall_hits::total 163599871 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796859 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796859 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses -system.cpu.dcache.overall_misses::total 3908532 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8974716998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8974716998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31498705498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31498705498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85385223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85385223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70495 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70495 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167437922 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167437922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167508417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167508417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032756 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023343 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023343 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8053.315702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8053.315702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8073.191749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8073.191749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8058.968875 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8058.968875 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8058.931761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8058.931761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1061983 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.881135 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891014 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891014 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374185 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313688 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015385 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8189.927402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8189.927402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8190.313499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8190.313499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715635 # number of replacements -system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 715629 # number of replacements +system.cpu.icache.tags.tagsinuse 511.829471 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88372474 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716141 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.400942 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326432500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.829471 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -839,207 +839,208 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 246 system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits -system.cpu.icache.overall_hits::total 88370544 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses -system.cpu.icache.overall_misses::total 721792 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178904656 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178904656 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88372474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88372474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88372474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88372474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88372474 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7785.311370 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404899 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404967 # 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average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015617 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5800.587395 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64326.110162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13603.546197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 4499965 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249489 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 27801 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 27801 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2029841 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32715 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313699 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32746 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531805 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.116184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320445 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4005282 88.38% 88.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 526523 11.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4531805 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216321500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1074578268 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2302086882 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 6592 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 731 # Transaction distribution -system.membus.trans_dist::ReadExResp 731 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7324 # Request fanout histogram +system.membus.snoop_fanout::samples 7332 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7332 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7324 # Request fanout histogram -system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7332 # Request fanout histogram +system.membus.reqLayer0.occupancy 9416916 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38389399 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index b10e642ea..e29d83073 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235407500 # Number of ticks simulated -final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517243 # Number of seconds simulated +sim_ticks 517243165500 # Number of ticks simulated +final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 785915 # Simulator instruction rate (inst/s) -host_op_rate 943520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490444540 # Simulator tick rate (ticks/s) -host_mem_usage 321320 # Number of bytes of host memory used -host_seconds 347.03 # Real time elapsed on the host +host_inst_rate 702843 # Simulator instruction rate (inst/s) +host_op_rate 843789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1332923086 # Simulator tick rate (ticks/s) +host_mem_usage 322968 # Number of bytes of host memory used +host_seconds 388.05 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470815 # number of cpu cycles simulated +system.cpu.numCycles 1034486331 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy @@ -588,6 +588,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution @@ -603,14 +609,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 0cd2c8d2d..dc4595f22 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.560940 # Nu sim_ticks 560939659000 # Number of ticks simulated final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234960 # Simulator instruction rate (inst/s) -host_op_rate 234960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 141903449 # Simulator tick rate (ticks/s) -host_mem_usage 300504 # Number of bytes of host memory used -host_seconds 3952.97 # Real time elapsed on the host +host_inst_rate 314051 # Simulator instruction rate (inst/s) +host_op_rate 314051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189670339 # Simulator tick rate (ticks/s) +host_mem_usage 308244 # Number of bytes of host memory used +host_seconds 2957.45 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -693,6 +693,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution @@ -708,15 +714,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259423 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141033 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1580028 85.90% 85.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259423 14.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4ab8a79d0..4dbf3fd00 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.276406 # Nu sim_ticks 276406029500 # Number of ticks simulated final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130885 # Simulator instruction rate (inst/s) -host_op_rate 130885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42946592 # Simulator tick rate (ticks/s) -host_mem_usage 301528 # Number of bytes of host memory used -host_seconds 6436.04 # Real time elapsed on the host +host_inst_rate 172081 # Simulator instruction rate (inst/s) +host_op_rate 172081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56464121 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 4895.25 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1000,6 +1000,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution @@ -1015,15 +1021,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259305 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1569303 85.82% 85.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259305 14.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 07561ac8e..f1fff22ed 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.286279 # Nu sim_ticks 1286278511500 # Number of ticks simulated final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1355944 # Simulator instruction rate (inst/s) -host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1878251411 # Simulator tick rate (ticks/s) -host_mem_usage 303804 # Number of bytes of host memory used -host_seconds 684.83 # Real time elapsed on the host +host_inst_rate 1389844 # Simulator instruction rate (inst/s) +host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1925210162 # Simulator tick rate (ticks/s) +host_mem_usage 305148 # Number of bytes of host memory used +host_seconds 668.12 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -484,6 +484,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution @@ -499,15 +505,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258580 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 53f1e9393..ca22b895a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.542258 # Number of seconds simulated -sim_ticks 542257602500 # Number of ticks simulated -final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 542257676500 # Number of ticks simulated +final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121737 # Simulator instruction rate (inst/s) -host_op_rate 149875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103039759 # Simulator tick rate (ticks/s) -host_mem_usage 317376 # Number of bytes of host memory used -host_seconds 5262.61 # Real time elapsed on the host +host_inst_rate 169610 # Simulator instruction rate (inst/s) +host_op_rate 208813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143560034 # Simulator tick rate (ticks/s) +host_mem_usage 325880 # Number of bytes of host memory used +host_seconds 3777.22 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291175 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18134 # Per bank write bursts -system.physmem.perBankRdBursts::2 18219 # Per bank write bursts -system.physmem.perBankRdBursts::3 18172 # Per bank write bursts -system.physmem.perBankRdBursts::4 18271 # Per bank write bursts -system.physmem.perBankRdBursts::5 18399 # Per bank write bursts +system.physmem.perBankRdBursts::1 18135 # Per bank write bursts +system.physmem.perBankRdBursts::2 18220 # Per bank write bursts +system.physmem.perBankRdBursts::3 18173 # Per bank write bursts +system.physmem.perBankRdBursts::4 18273 # Per bank write bursts +system.physmem.perBankRdBursts::5 18400 # Per bank write bursts system.physmem.perBankRdBursts::6 18176 # Per bank write bursts -system.physmem.perBankRdBursts::7 17991 # Per bank write bursts -system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::8 18030 # Per bank write bursts system.physmem.perBankRdBursts::9 18057 # Per bank write bursts system.physmem.perBankRdBursts::10 18104 # Per bank write bursts system.physmem.perBankRdBursts::11 18195 # Per bank write bursts -system.physmem.perBankRdBursts::12 18215 # Per bank write bursts -system.physmem.perBankRdBursts::13 18268 # Per bank write bursts -system.physmem.perBankRdBursts::14 18078 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::12 18214 # Per bank write bursts +system.physmem.perBankRdBursts::13 18267 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18257 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4098 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542257509000 # Total gap between requests +system.physmem.totGap 542257582000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes @@ -224,12 +224,12 @@ system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Wr system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 2871354000 # Total ticks spent queuing -system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst +system.physmem.totQLat 2868100000 # Total ticks spent queuing +system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s @@ -240,47 +240,47 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing -system.physmem.readRowHits 194229 # Number of row buffer hits during reads -system.physmem.writeRowHits 51633 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes -system.physmem.avgGap 1517767.95 # Average gap between requests -system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ) +system.physmem.readRowHits 194250 # Number of row buffer hits during reads +system.physmem.writeRowHits 51642 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1517768.15 # Average gap between requests +system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.351550 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states +system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.324021 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.462409 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states +system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.447269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805772 # Number of BP lookups +system.cpu.branchPred.lookups 154805770 # Number of BP lookups system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -401,24 +401,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084515205 # number of cpu cycles simulated +system.cpu.numCycles 1084515353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692822 # CPI: cycles per instruction +system.cpu.cpi 1.692823 # CPI: cycles per instruction system.cpu.ipc 0.590729 # IPC: instructions per cycle -system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -454,14 +454,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -486,14 +486,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,16 +522,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296 system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,24 +542,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -567,44 +567,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58 system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits -system.cpu.icache.overall_hits::total 291576498 # number of overall hits +system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits +system.cpu.icache.overall_hits::total 291576499 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,37 +619,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25343 system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -686,18 +686,18 @@ system.cpu.l2cache.demand_misses::total 291208 # nu system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses system.cpu.l2cache.overall_misses::total 291208 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -724,18 +724,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360505 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,69 +746,75 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # 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number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution @@ -824,21 +830,21 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258395 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 225084 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -861,9 +867,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 547917 # Request fanout histogram -system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 85998f5be..8ea31b650 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410670 # Number of seconds simulated -sim_ticks 410669815000 # Number of ticks simulated -final_tick 410669815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410968 # Number of seconds simulated +sim_ticks 410968419000 # Number of ticks simulated +final_tick 410968419000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94058 # Simulator instruction rate (inst/s) -host_op_rate 115798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60293323 # Simulator tick rate (ticks/s) -host_mem_usage 320128 # Number of bytes of host memory used -host_seconds 6811.20 # Real time elapsed on the host +host_inst_rate 85599 # Simulator instruction rate (inst/s) +host_op_rate 105384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54910730 # Simulator tick rate (ticks/s) +host_mem_usage 322152 # Number of bytes of host memory used +host_seconds 7484.30 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 232448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7026304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12953152 # Number of bytes read from this memory -system.physmem.bytes_read::total 20211904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244928 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244928 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202393 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66327 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66327 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 566022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17109375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31541524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49216921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10336596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 566022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17109375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31541524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59553517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315811 # Number of read requests accepted -system.physmem.writeReqs 66327 # Number of write requests accepted -system.physmem.readBursts 315811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66327 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20192576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4239424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20211904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 58 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19865 # Per bank write bursts -system.physmem.perBankRdBursts::1 19533 # Per bank write bursts -system.physmem.perBankRdBursts::2 19787 # Per bank write bursts -system.physmem.perBankRdBursts::3 19881 # Per bank write bursts -system.physmem.perBankRdBursts::4 19767 # Per bank write bursts -system.physmem.perBankRdBursts::5 20312 # Per bank write bursts -system.physmem.perBankRdBursts::6 19558 # Per bank write bursts -system.physmem.perBankRdBursts::7 19499 # Per bank write bursts -system.physmem.perBankRdBursts::8 19473 # Per bank write bursts -system.physmem.perBankRdBursts::9 19475 # Per bank write bursts -system.physmem.perBankRdBursts::10 19453 # Per bank write bursts -system.physmem.perBankRdBursts::11 19704 # Per bank write bursts -system.physmem.perBankRdBursts::12 19596 # Per bank write bursts -system.physmem.perBankRdBursts::13 20052 # Per bank write bursts -system.physmem.perBankRdBursts::14 19574 # Per bank write bursts -system.physmem.perBankRdBursts::15 19980 # Per bank write bursts -system.physmem.perBankWrBursts::0 4265 # Per bank write bursts -system.physmem.perBankWrBursts::1 4106 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 226432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7007424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12927040 # Number of bytes read from this memory +system.physmem.bytes_read::total 20160896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244672 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 201985 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315014 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66323 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 550972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17051004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31455069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49057044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10328463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 550972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17051004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31455069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59385507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315014 # Number of read requests accepted +system.physmem.writeReqs 66323 # Number of write requests accepted +system.physmem.readBursts 315014 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20141440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19456 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20160896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 304 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19880 # Per bank write bursts +system.physmem.perBankRdBursts::1 19436 # Per bank write bursts +system.physmem.perBankRdBursts::2 19769 # Per bank write bursts +system.physmem.perBankRdBursts::3 19866 # Per bank write bursts +system.physmem.perBankRdBursts::4 19687 # Per bank write bursts +system.physmem.perBankRdBursts::5 20154 # Per bank write bursts +system.physmem.perBankRdBursts::6 19548 # Per bank write bursts +system.physmem.perBankRdBursts::7 19410 # Per bank write bursts +system.physmem.perBankRdBursts::8 19409 # Per bank write bursts +system.physmem.perBankRdBursts::9 19464 # Per bank write bursts +system.physmem.perBankRdBursts::10 19401 # Per bank write bursts +system.physmem.perBankRdBursts::11 19757 # Per bank write bursts +system.physmem.perBankRdBursts::12 19512 # Per bank write bursts +system.physmem.perBankRdBursts::13 19953 # Per bank write bursts +system.physmem.perBankRdBursts::14 19499 # Per bank write bursts +system.physmem.perBankRdBursts::15 19965 # Per bank write bursts +system.physmem.perBankWrBursts::0 4261 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4243 # Per bank write bursts +system.physmem.perBankWrBursts::5 4228 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4094 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4093 # Per bank write bursts -system.physmem.perBankWrBursts::15 4156 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410669760500 # Total gap between requests +system.physmem.totGap 410968364500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315811 # Read request sizes (log2) +system.physmem.readPktSize::6 315014 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66327 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9282 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1023 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,165 +148,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4657 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.756150 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.878617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.405742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53923 39.46% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57606 42.15% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14740 10.79% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1412 1.03% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1397 1.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1387 1.01% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1267 0.93% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1142 0.84% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3792 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136666 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.293227 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.720611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 661.085009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4010 99.48% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.25% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.05% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11264-12287 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4031 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4031 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.432895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.394232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.238105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3399 84.32% 84.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 453 11.24% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 84 2.08% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 29 0.72% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.42% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.32% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.25% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 136515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.576479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.708862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.239774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54117 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57190 41.89% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14847 10.88% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1353 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1460 1.07% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1428 1.05% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1211 0.89% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1099 0.81% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3810 2.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136515 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.350768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.698276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 557.584511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.48% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.22% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.07% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11264-12287 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.416708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.380496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.197000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3413 84.61% 84.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 10 0.25% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 440 10.91% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 77 1.91% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.45% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.25% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.10% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4031 # Writes before turning the bus around for reads -system.physmem.totQLat 8703208249 # Total ticks spent queuing -system.physmem.totMemAccLat 14619001999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1577545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27584.66 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 8815753021 # Total ticks spent queuing +system.physmem.totMemAccLat 14716565521 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1573550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28012.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46334.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46762.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.17 # Average write queue length when enqueuing -system.physmem.readRowHits 218486 # Number of row buffer hits during reads -system.physmem.writeRowHits 26585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.12 # Row buffer hit rate for writes -system.physmem.avgGap 1074663.50 # Average gap between requests -system.physmem.pageHitRate 64.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 519334200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 283366875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1233694800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96824469870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161463849000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287363708985 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.756123 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267972811336 # Time in different power states -system.physmem_0.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.readRowHits 218109 # Number of row buffer hits during reads +system.physmem.writeRowHits 26303 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.70 # Row buffer hit rate for writes +system.physmem.avgGap 1077703.88 # Average gap between requests +system.physmem.pageHitRate 64.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518041440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282661500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1230403200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96374724480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 162040566750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287505134730 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.583184 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 268934392735 # Time in different power states +system.physmem_0.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128976939914 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128308892015 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513679320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280281375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226604600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212718960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96486689295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161760147750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287302592820 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.607300 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 268468666587 # Time in different power states -system.physmem_1.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem_1.actEnergy 513943920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280425750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224030600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96023770920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162348426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287445609300 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.438325 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 269449023468 # Time in different power states +system.physmem_1.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128482733413 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127794271282 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234660907 # Number of BP lookups -system.cpu.branchPred.condPredicted 161885632 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514558 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122787051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 109471469 # Number of BTB hits +system.cpu.branchPred.lookups 234596987 # Number of BP lookups +system.cpu.branchPred.condPredicted 161823961 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514568 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122849584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 109536151 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.155549 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25674321 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.162818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25674290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,95 +421,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821339631 # number of cpu cycles simulated +system.cpu.numCycles 821936839 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85359172 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200831144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234660907 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135145790 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720108706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063537 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85359069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200718249 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234596987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135210441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720713354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063509 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3327 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 371279487 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652622 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.165203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3414 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 371348285 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652804 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.824964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.165392 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139284134 16.97% 16.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223266821 27.19% 44.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 99362992 12.10% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359091829 43.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139667844 17.00% 17.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223418217 27.19% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 99581089 12.12% 56.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 358942808 43.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285705 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.462040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121274951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 160921163 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660075 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631496 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518091 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25119096 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248135517 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967011 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518091 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178281745 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80150846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 211317 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82524216 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190646555 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25420306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24957441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41531798 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1705173 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225452951 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812557102 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358174955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876459 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285420 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.460840 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121271680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 161528221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660379 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518074 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181978 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13827 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248136929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39965779 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518074 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178276857 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80769172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209944 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464321622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82514289 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190649625 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25545503 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2266892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41524383 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1701930 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225389846 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812446196 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358179405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350674721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350611616 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7266 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108777970 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366242931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1613389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371796 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168681315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017114082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18565562 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379968716 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032836656 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821005776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238863 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084756 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108773290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366116518 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236097454 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1660812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5332652 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168559259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12361 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017121345 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18467813 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379846662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032147150 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 821609958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.237961 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263349245 32.08% 32.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227125536 27.66% 59.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217733280 26.52% 86.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96668881 11.77% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16128827 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263952395 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227112360 27.64% 59.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217754382 26.50% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96663071 11.77% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16127742 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821005776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821609958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63875016 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18146 0.01% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63877670 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available @@ -541,13 +537,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157510134 46.60% 65.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 115986364 34.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157438093 46.58% 65.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116037067 34.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370249 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195831 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371832 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195828 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -571,88 +567,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322123387 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215570268 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322111232 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215588105 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017114082 # Type of FU issued -system.cpu.iq.rate 1.238360 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338026549 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332339 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3149949023 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1505114950 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934262178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321330304 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960611 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017121345 # Type of FU issued +system.cpu.iq.rate 1.237469 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338007862 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332318 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3150451328 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504870795 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934275536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876995 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565857 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1321318894 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810313 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960669 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 114001993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18396 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113875580 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1094 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18373 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116958 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065819 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19975 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20149 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518091 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326945 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168699230 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518074 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35327155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46316 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168577176 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366242931 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46833 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18396 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437302 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221855 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974739392 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42374690 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 366116518 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236097454 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 106 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18373 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437332 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784565 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974752675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42368670 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497752889 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613606 # Number of branches executed -system.cpu.iew.exec_stores 194455377 # Number of stores executed -system.cpu.iew.exec_rate 1.186768 # Inst execution rate -system.cpu.iew.wb_sent 963712681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960414622 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536046271 # num instructions producing a value -system.cpu.iew.wb_consumers 893280305 # num instructions consuming a value +system.cpu.iew.exec_refs 497765117 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613949 # Number of branches executed +system.cpu.iew.exec_stores 194467406 # Number of stores executed +system.cpu.iew.exec_rate 1.185922 # Inst execution rate +system.cpu.iew.wb_sent 963726327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960427986 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536047777 # num instructions producing a value +system.cpu.iew.wb_consumers 893284950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169327 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600087 # average fanout of values written-back +system.cpu.iew.wb_rate 1.168494 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357416983 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357420302 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770184473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.024079 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.777435 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500888 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770788105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.023277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.776928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 431571304 56.03% 56.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174376243 22.64% 78.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936565 9.47% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32893073 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539337 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258396 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7274917 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974456 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360182 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 432159906 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174391468 22.63% 78.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936790 9.46% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32897876 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538896 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258442 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269703 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974810 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360214 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770184473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770788105 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,80 +694,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360182 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1893962593 # The number of ROB reads -system.cpu.rob.rob_writes 2343119332 # The number of ROB writes -system.cpu.timesIdled 647411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 333855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360214 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1894569512 # The number of ROB reads +system.cpu.rob.rob_writes 2343126520 # The number of ROB writes +system.cpu.timesIdled 647387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326881 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282043 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282043 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995778090 # number of integer regfile reads -system.cpu.int_regfile_writes 567907785 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads +system.cpu.cpi 1.282975 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282975 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803218 # number of integer regfile reads +system.cpu.int_regfile_writes 567908989 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889842 # number of floating regfile reads system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794401386 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898061 # number of cc regfile writes -system.cpu.misc_regfile_reads 715805814 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794442903 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898512 # number of cc regfile writes +system.cpu.misc_regfile_reads 715818410 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933524 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216512 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 256787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933524 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999870 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756184 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.933181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258467 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257783000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933181 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346679 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127908123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127908123 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839346712 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346712 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286294274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286294274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907939 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907939 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414201807 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414201807 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414204964 # number of overall hits -system.cpu.dcache.overall_hits::total 414204964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3034548 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3034548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043354 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043354 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414202213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414202213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414205370 # number of overall hits +system.cpu.dcache.overall_hits::total 414205370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3033975 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3033975 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043538 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043538 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4077902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4077902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078548 # number of overall misses -system.cpu.dcache.overall_misses::total 4078548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45043651350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45043651350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4077513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4077513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078159 # number of overall misses +system.cpu.dcache.overall_misses::total 4078159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45356506350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45356506350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328249 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -780,72 +776,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418279726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008092 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009749 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009749 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9608.737159 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9608.737159 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11045.790544 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11044.041004 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009750 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9602.705747 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9602.705747 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11123.571243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11121.809216 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 356457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 355417 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4792 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.360888 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 74.168823 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735102 # number of writebacks -system.cpu.dcache.writebacks::total 735102 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999338 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999338 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322490 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735485 # number of writebacks +system.cpu.dcache.writebacks::total 735485 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998769 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 998769 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322672 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322672 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30092528850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30092528850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,231 +852,233 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11703.506763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11703.506763 # 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number of cycles access was blocked @@ -1089,153 +1087,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66327 # number of writebacks -system.cpu.l2cache.writebacks::total 66327 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1069 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1069 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 66323 # number of writebacks +system.cpu.l2cache.writebacks::total 66323 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1105 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7934847500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7690370500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16906807287 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24841654787 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 2080 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2089 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8868 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8868 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202062 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202062 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3538 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3538 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108114 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108114 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3538 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109491 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 139099000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240756500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240756500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7531984000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7531984000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240756500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7671083000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7911839500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240756500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7671083000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17000279164 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24912118664 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001913 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001913 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000703 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053249 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053249 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014308 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039851 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039751 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7205861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6779490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 246291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035851 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23134825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330879552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554354688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 545836 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16398212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.033285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179381 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 15852127 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644320 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 9549 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 9495 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 54 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6778141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 245737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23134399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330871168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223499584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554370752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544470 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16396581 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.079179 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15852393 96.67% 96.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 545819 3.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 15098363 92.08% 92.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1298164 7.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 54 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16398212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8661298500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16396581 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8661548500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755038952 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754847439 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135066975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135063977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 314432 # Transaction distribution -system.membus.trans_dist::Writeback 66327 # Transaction distribution -system.membus.trans_dist::CleanEvict 232586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 314432 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24456832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24456832 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 313637 # Transaction distribution +system.membus.trans_dist::Writeback 66323 # Transaction distribution +system.membus.trans_dist::CleanEvict 231789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 313637 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24405568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24405568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 614742 # Request fanout histogram +system.membus.snoop_fanout::samples 613142 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 614742 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 613142 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 614742 # Request fanout histogram -system.membus.reqLayer0.occupancy 978145707 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 613142 # Request fanout histogram +system.membus.reqLayer0.occupancy 975944720 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1654146686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1649749525 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 627fd964a..24851d5c1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043722 # Number of seconds simulated -sim_ticks 1043722398500 # Number of ticks simulated -final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043724 # Number of seconds simulated +sim_ticks 1043723537500 # Number of ticks simulated +final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 921530 # Simulator instruction rate (inst/s) -host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504334297 # Simulator tick rate (ticks/s) -host_mem_usage 320916 # Number of bytes of host memory used -host_seconds 693.81 # Real time elapsed on the host +host_inst_rate 832063 # Simulator instruction rate (inst/s) +host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1358287943 # Simulator tick rate (ticks/s) +host_mem_usage 323064 # Number of bytes of host memory used +host_seconds 768.41 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 290359 # Nu system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087444797 # number of cpu cycles simulated +system.cpu.numCycles 2087447075 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy @@ -490,14 +490,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) @@ -528,14 +528,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,14 +564,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses @@ -590,15 +590,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution @@ -614,14 +620,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 257579 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index c8b76a216..15844baba 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.059549 # Nu sim_ticks 59549031000 # Number of ticks simulated final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231283 # Simulator instruction rate (inst/s) -host_op_rate 231283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155732739 # Simulator tick rate (ticks/s) -host_mem_usage 299636 # Number of bytes of host memory used -host_seconds 382.38 # Real time elapsed on the host +host_inst_rate 320796 # Simulator instruction rate (inst/s) +host_op_rate 320796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216005540 # Simulator tick rate (ticks/s) +host_mem_usage 307628 # Number of bytes of host memory used +host_seconds 275.68 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -696,6 +696,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution @@ -711,15 +717,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132445 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.156587 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.363411 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 713379 84.34% 84.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132445 15.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 92f71955f..bea1e6fc8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022357 # Nu sim_ticks 22356634500 # Number of ticks simulated final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154709 # Simulator instruction rate (inst/s) -host_op_rate 154709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43456447 # Simulator tick rate (ticks/s) -host_mem_usage 300660 # Number of bytes of host memory used -host_seconds 514.46 # Real time elapsed on the host +host_inst_rate 213363 # Simulator instruction rate (inst/s) +host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59931818 # Simulator tick rate (ticks/s) +host_mem_usage 308400 # Number of bytes of host memory used +host_seconds 373.03 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -994,6 +994,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution @@ -1009,15 +1015,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132064 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.182459 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.386223 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 591735 81.75% 81.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132064 18.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 227ff6a79..67f744153 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056986 # Number of seconds simulated -sim_ticks 56986224500 # Number of ticks simulated -final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056991 # Number of seconds simulated +sim_ticks 56991022500 # Number of ticks simulated +final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135704 # Simulator instruction rate (inst/s) -host_op_rate 173546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109049636 # Simulator tick rate (ticks/s) -host_mem_usage 317176 # Number of bytes of host memory used -host_seconds 522.57 # Real time elapsed on the host +host_inst_rate 186679 # Simulator instruction rate (inst/s) +host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150024942 # Simulator tick rate (ticks/s) +host_mem_usage 325676 # Number of bytes of host memory used +host_seconds 379.88 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,24 +25,24 @@ system.physmem.num_reads::cpu.data 123811 # Nu system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128791 # Number of read requests accepted system.physmem.writeReqs 86157 # Number of write requests accepted system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM +system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue @@ -66,15 +66,15 @@ system.physmem.perBankRdBursts::14 7975 # Pe system.physmem.perBankRdBursts::15 7995 # Per bank write bursts system.physmem.perBankWrBursts::0 5393 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5463 # Per bank write bursts -system.physmem.perBankWrBursts::3 5328 # Per bank write bursts +system.physmem.perBankWrBursts::2 5464 # Per bank write bursts +system.physmem.perBankWrBursts::3 5326 # Per bank write bursts system.physmem.perBankWrBursts::4 5352 # Per bank write bursts -system.physmem.perBankWrBursts::5 5545 # Per bank write bursts -system.physmem.perBankWrBursts::6 5246 # Per bank write bursts +system.physmem.perBankWrBursts::5 5547 # Per bank write bursts +system.physmem.perBankWrBursts::6 5252 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts -system.physmem.perBankWrBursts::10 5289 # Per bank write bursts +system.physmem.perBankWrBursts::10 5292 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56986193500 # Total gap between requests +system.physmem.totGap 56990990500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads -system.physmem.totQLat 1688662500 # Total ticks spent queuing -system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads +system.physmem.totQLat 1683428000 # Total ticks spent queuing +system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing -system.physmem.readRowHits 112105 # Number of row buffer hits during reads -system.physmem.writeRowHits 64137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes -system.physmem.avgGap 265116.18 # Average gap between requests +system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing +system.physmem.readRowHits 112096 # Number of row buffer hits during reads +system.physmem.writeRowHits 64153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes +system.physmem.avgGap 265138.50 # Average gap between requests system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.527477 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states +system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.591931 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.546032 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states +system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.479908 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800511 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits +system.cpu.branchPred.lookups 14800541 # Number of BP lookups +system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,67 +404,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113972449 # number of cpu cycles simulated +system.cpu.numCycles 113982045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.607167 # CPI: cycles per instruction -system.cpu.ipc 0.622213 # IPC: instructions per cycle -system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.607302 # CPI: cycles per instruction +system.cpu.ipc 0.622161 # IPC: instructions per cycle +system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 156435 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits -system.cpu.dcache.overall_hits::total 42592409 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses -system.cpu.dcache.overall_misses::total 303854 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits +system.cpu.dcache.overall_hits::total 42592256 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses +system.cpu.dcache.overall_misses::total 304005 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) @@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,14 +505,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks system.cpu.dcache.writebacks::total 128400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses @@ -523,16 +523,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136546 system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42865 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42866 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50016805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50016805 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941041 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941041 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941041 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941041 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941041 # number of overall hits -system.cpu.icache.overall_hits::total 24941041 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44908 # number of overall misses -system.cpu.icache.overall_misses::total 44908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 926324500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 926324500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 926324500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 926324500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 926324500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 926324500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24985949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24985949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24985949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24985949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24985949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24985949 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits +system.cpu.icache.overall_hits::total 24941084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses +system.cpu.icache.overall_misses::total 44909 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20627.159971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20627.159971 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,67 +615,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 881417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 881417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 881417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 881417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 881417500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 881417500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 884562000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 884562000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 884562000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 884562000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19696.764568 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95654 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29860.809495 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 161643 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.275069 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.835593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.708442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.811135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.855600 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.796365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.811134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1806 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12714 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15870 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3409200 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3409200 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39917 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 39917 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 39918 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 39918 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76572 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39917 # number of overall hits +system.cpu.l2cache.demand_hits::total 76573 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39918 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits -system.cpu.l2cache.overall_hits::total 76572 # number of overall hits +system.cpu.l2cache.overall_hits::total 76573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses @@ -688,56 +688,56 @@ system.cpu.l2cache.demand_misses::total 128867 # nu system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses system.cpu.l2cache.overall_misses::total 128867 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8274960000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8274960000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394876000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 394876000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878573500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878573500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 394876000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10153533500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10548409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 394876000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10153533500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10548409500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8273802000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8273802000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394300500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 394300500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1875098000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1875098000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394300500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10148900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10543200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394300500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10148900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10543200500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 44908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44909 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 44909 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 44909 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44908 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205440 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44909 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205440 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111138 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111138 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111136 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111136 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111138 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.627276 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111138 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.627276 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86810.092593 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,75 +772,81 @@ system.cpu.l2cache.demand_mshr_misses::total 128792 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95654 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 26515 # Transaction distribution system.membus.trans_dist::Writeback 86157 # Transaction distribution @@ -863,9 +869,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 222458 # Request fanout histogram -system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index c156cc0a5..4fc60452d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033333 # Number of seconds simulated -sim_ticks 33333078000 # Number of ticks simulated -final_tick 33333078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033346 # Number of seconds simulated +sim_ticks 33346420000 # Number of ticks simulated +final_tick 33346420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125008 # Simulator instruction rate (inst/s) -host_op_rate 159871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58765299 # Simulator tick rate (ticks/s) -host_mem_usage 325044 # Number of bytes of host memory used -host_seconds 567.22 # Real time elapsed on the host +host_inst_rate 116263 # Simulator instruction rate (inst/s) +host_op_rate 148687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54676178 # Simulator tick rate (ticks/s) +host_mem_usage 326572 # Number of bytes of host memory used +host_seconds 609.89 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 591360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2521216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6195328 # Number of bytes read from this memory -system.physmem.bytes_read::total 9307904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 591360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 591360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6264192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6264192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9240 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145436 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97878 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97878 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17740936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75637059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185861264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 279239259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17740936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17740936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187927200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187927200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187927200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17740936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75637059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185861264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 467166458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145436 # Number of read requests accepted -system.physmem.writeReqs 97878 # Number of write requests accepted -system.physmem.readBursts 145436 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97878 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9300544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6263104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9307904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6264192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 581760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2519040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6191552 # Number of bytes read from this memory +system.physmem.bytes_read::total 9292352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 581760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 581760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6257152 # Number of bytes written to this memory +system.physmem.bytes_written::total 6257152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96743 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145193 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97768 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97768 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17445951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75541542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185673665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 278661158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17445951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17445951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187640892 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187640892 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187640892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17445951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75541542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185673665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466302050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145193 # Number of read requests accepted +system.physmem.writeReqs 97768 # Number of write requests accepted +system.physmem.readBursts 145193 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97768 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9285376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 6255360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9292352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6257152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9151 # Per bank write bursts -system.physmem.perBankRdBursts::1 9416 # Per bank write bursts -system.physmem.perBankRdBursts::2 9264 # Per bank write bursts -system.physmem.perBankRdBursts::3 9524 # Per bank write bursts -system.physmem.perBankRdBursts::4 9728 # Per bank write bursts -system.physmem.perBankRdBursts::5 9774 # Per bank write bursts -system.physmem.perBankRdBursts::6 9086 # Per bank write bursts -system.physmem.perBankRdBursts::7 9016 # Per bank write bursts -system.physmem.perBankRdBursts::8 9170 # Per bank write bursts -system.physmem.perBankRdBursts::9 8620 # Per bank write bursts -system.physmem.perBankRdBursts::10 8843 # Per bank write bursts -system.physmem.perBankRdBursts::11 8715 # Per bank write bursts -system.physmem.perBankRdBursts::12 8697 # Per bank write bursts -system.physmem.perBankRdBursts::13 8672 # Per bank write bursts -system.physmem.perBankRdBursts::14 8700 # Per bank write bursts -system.physmem.perBankRdBursts::15 8945 # Per bank write bursts -system.physmem.perBankWrBursts::0 6002 # Per bank write bursts -system.physmem.perBankWrBursts::1 6227 # Per bank write bursts -system.physmem.perBankWrBursts::2 6156 # Per bank write bursts -system.physmem.perBankWrBursts::3 6165 # Per bank write bursts -system.physmem.perBankWrBursts::4 6066 # Per bank write bursts -system.physmem.perBankWrBursts::5 6338 # Per bank write bursts -system.physmem.perBankWrBursts::6 6039 # Per bank write bursts -system.physmem.perBankWrBursts::7 6021 # Per bank write bursts -system.physmem.perBankWrBursts::8 6032 # Per bank write bursts -system.physmem.perBankWrBursts::9 6183 # Per bank write bursts -system.physmem.perBankWrBursts::10 6239 # Per bank write bursts -system.physmem.perBankWrBursts::11 5928 # Per bank write bursts -system.physmem.perBankWrBursts::12 6101 # Per bank write bursts -system.physmem.perBankWrBursts::13 6124 # Per bank write bursts -system.physmem.perBankWrBursts::14 6211 # Per bank write bursts -system.physmem.perBankWrBursts::15 6029 # Per bank write bursts +system.physmem.perBankRdBursts::0 9137 # Per bank write bursts +system.physmem.perBankRdBursts::1 9395 # Per bank write bursts +system.physmem.perBankRdBursts::2 9161 # Per bank write bursts +system.physmem.perBankRdBursts::3 9548 # Per bank write bursts +system.physmem.perBankRdBursts::4 9715 # Per bank write bursts +system.physmem.perBankRdBursts::5 9765 # Per bank write bursts +system.physmem.perBankRdBursts::6 9098 # Per bank write bursts +system.physmem.perBankRdBursts::7 9032 # Per bank write bursts +system.physmem.perBankRdBursts::8 9205 # Per bank write bursts +system.physmem.perBankRdBursts::9 8593 # Per bank write bursts +system.physmem.perBankRdBursts::10 8826 # Per bank write bursts +system.physmem.perBankRdBursts::11 8653 # Per bank write bursts +system.physmem.perBankRdBursts::12 8623 # Per bank write bursts +system.physmem.perBankRdBursts::13 8667 # Per bank write bursts +system.physmem.perBankRdBursts::14 8699 # Per bank write bursts +system.physmem.perBankRdBursts::15 8967 # Per bank write bursts +system.physmem.perBankWrBursts::0 5976 # Per bank write bursts +system.physmem.perBankWrBursts::1 6230 # Per bank write bursts +system.physmem.perBankWrBursts::2 6094 # Per bank write bursts +system.physmem.perBankWrBursts::3 6205 # Per bank write bursts +system.physmem.perBankWrBursts::4 6124 # Per bank write bursts +system.physmem.perBankWrBursts::5 6340 # Per bank write bursts +system.physmem.perBankWrBursts::6 6054 # Per bank write bursts +system.physmem.perBankWrBursts::7 6041 # Per bank write bursts +system.physmem.perBankWrBursts::8 6001 # Per bank write bursts +system.physmem.perBankWrBursts::9 6103 # Per bank write bursts +system.physmem.perBankWrBursts::10 6248 # Per bank write bursts +system.physmem.perBankWrBursts::11 5916 # Per bank write bursts +system.physmem.perBankWrBursts::12 6074 # Per bank write bursts +system.physmem.perBankWrBursts::13 6102 # Per bank write bursts +system.physmem.perBankWrBursts::14 6204 # Per bank write bursts +system.physmem.perBankWrBursts::15 6028 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33332792500 # Total gap between requests +system.physmem.totGap 33346162500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145436 # Read request sizes (log2) +system.physmem.readPktSize::6 145193 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97878 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97768 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 41267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,32 +148,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7862 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 174.992388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.439382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.025071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52267 58.77% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22760 25.59% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4436 4.99% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1732 1.95% 91.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1066 1.20% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 777 0.87% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 661 0.74% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 818 0.92% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4422 4.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88939 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.584503 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.105941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.238550 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.437436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.610569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.212794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52129 58.86% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22374 25.26% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4601 5.19% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1696 1.91% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1069 1.21% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 812 0.92% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 692 0.78% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 790 0.89% 95.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4403 4.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.550271 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.061813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 186.955752 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5907 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.555744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.266741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4704 79.58% 79.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.61% 80.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 781 13.21% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 157 2.66% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 88 1.49% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 64 1.08% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 47 0.80% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 17 0.29% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5908 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5908 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.543670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.503041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.228970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4711 79.74% 79.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.59% 80.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 768 13.00% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 163 2.76% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 108 1.83% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 1.03% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.64% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.17% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads -system.physmem.totQLat 7028707749 # Total ticks spent queuing -system.physmem.totMemAccLat 9753476499 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 726605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 48366.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5908 # Writes before turning the bus around for reads +system.physmem.totQLat 7011292666 # Total ticks spent queuing +system.physmem.totMemAccLat 9731617666 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 725420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 48325.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 67116.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 279.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.89 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 279.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 67075.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 278.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtil 3.64 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing -system.physmem.readRowHits 118079 # Number of row buffer hits during reads -system.physmem.writeRowHits 36164 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.95 # Row buffer hit rate for writes -system.physmem.avgGap 136994.96 # Average gap between requests -system.physmem.pageHitRate 63.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343934640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187662750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 584680200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317610720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11782825965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9664105500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25057965135 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.742046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15979863754 # Time in different power states -system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem.avgRdQLen 1.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.60 # Average write queue length when enqueuing +system.physmem.readRowHits 118088 # Number of row buffer hits during reads +system.physmem.writeRowHits 36158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.98 # Row buffer hit rate for writes +system.physmem.avgGap 137249.03 # Average gap between requests +system.physmem.pageHitRate 63.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342241200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186738750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583385400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 317818080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11790659475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9661917750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25060414575 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.639504 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15978647517 # Time in different power states +system.physmem_0.memoryStateTime::REF 1113320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16240286246 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16249048233 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328444200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179210625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 548823600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316528560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11298113640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10089291750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24937557735 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.129809 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16691408912 # Time in different power states -system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem_1.actEnergy 326909520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178373250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 547528800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315329760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11234568330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10149705000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24930068580 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.730472 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16793127980 # Time in different power states +system.physmem_1.memoryStateTime::REF 1113320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15528741088 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15434548270 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17206633 # Number of BP lookups -system.cpu.branchPred.condPredicted 11518078 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9346074 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675410 # Number of BTB hits +system.cpu.branchPred.lookups 17208509 # Number of BP lookups +system.cpu.branchPred.condPredicted 11519539 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648302 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9342884 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675123 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.124430 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873047 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101552 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.149398 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872388 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66666157 # number of cpu cycles simulated +system.cpu.numCycles 66692841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5010938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88191821 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17206633 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548457 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60137734 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322663 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13644 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22767110 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69105 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65830648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.695372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5046776 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88195647 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17208509 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9547511 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60140641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322595 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6428 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13633 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22763338 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69414 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65868800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.694437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296898 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20050738 30.46% 30.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265796 12.56% 43.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9200690 13.98% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28313424 43.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20089005 30.50% 30.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8265359 12.55% 43.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9198123 13.96% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316313 42.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65830648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258101 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322887 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8588438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19545167 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31574635 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5630215 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492193 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3180012 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171001 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101409826 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3046686 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492193 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13345278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5337889 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 804170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32233077 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13618041 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99203464 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 983266 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3848076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66970 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4316860 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5302934 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457709098 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115412648 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65868800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8616725 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19555814 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31576285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5627882 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492094 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179727 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171045 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101400911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3043244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492094 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13372904 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5353130 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 801467 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32232883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13616322 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99196979 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981006 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3848899 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63135 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4311075 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5311261 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103921430 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457681852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115406862 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296250 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18653 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12703257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24321959 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21992794 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1408685 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2344134 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98166936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34525 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94895750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 693672 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7518876 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20249831 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65830648 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.441513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149732 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10292204 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12699652 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24320213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21993792 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1400092 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2341142 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98161647 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34523 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94891012 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 695609 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7513585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20245943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65868800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.440606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17559708 26.67% 26.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17428340 26.47% 53.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17111473 25.99% 79.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11681013 17.74% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2049145 3.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 969 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17598833 26.72% 26.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17429188 26.46% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17113322 25.98% 79.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11675618 17.73% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2050869 3.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 970 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65830648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65868800 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6713649 22.39% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11199453 37.36% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12066123 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6712111 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11183885 37.33% 59.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12062879 40.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49496629 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89874 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49494737 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89878 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24067515 25.36% 77.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241694 22.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24064392 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241967 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94895750 # Type of FU issued -system.cpu.iq.rate 1.423447 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29979264 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286294877 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105731606 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465380 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94891012 # Type of FU issued +system.cpu.iq.rate 1.422807 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29958914 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315719 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286305140 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105721004 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93462242 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124874896 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124849808 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1362273 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363438 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1455697 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11776 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1437056 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1453951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2082 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438054 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140882 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 184054 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 138729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 184462 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492193 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 620956 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 467696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98211315 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492094 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 468032 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98206039 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24321959 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21992794 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18605 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1621 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463138 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11776 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302825 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221559 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93978064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23759823 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917686 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24320213 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21993792 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18603 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1634 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463552 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221650 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524340 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93974044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23757485 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916968 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9854 # number of nop insts executed -system.cpu.iew.exec_refs 44744798 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251807 # Number of branches executed -system.cpu.iew.exec_stores 20984975 # Number of stores executed -system.cpu.iew.exec_rate 1.409682 # Inst execution rate -system.cpu.iew.wb_sent 93587077 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465437 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44977935 # num instructions producing a value -system.cpu.iew.wb_consumers 76555853 # num instructions consuming a value +system.cpu.iew.exec_nop 9869 # number of nop insts executed +system.cpu.iew.exec_refs 44742217 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251815 # Number of branches executed +system.cpu.iew.exec_stores 20984732 # Number of stores executed +system.cpu.iew.exec_rate 1.409057 # Inst execution rate +system.cpu.iew.wb_sent 93584291 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93462299 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44972986 # num instructions producing a value +system.cpu.iew.wb_consumers 76550519 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401992 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587518 # average fanout of values written-back +system.cpu.iew.wb_rate 1.401384 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587494 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6538600 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6533064 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479178 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64771963 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.400114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164673 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479099 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64811353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.399263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31176340 48.13% 48.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16804620 25.94% 74.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4339366 6.70% 80.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4157771 6.42% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1944331 3.00% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1263277 1.95% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 736800 1.14% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578701 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3770757 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31214732 48.16% 48.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16807105 25.93% 74.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4339311 6.70% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4161583 6.42% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937068 2.99% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1261836 1.95% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 738743 1.14% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580049 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3770926 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64771963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64811353 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3770757 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158202644 # The number of ROB reads -system.cpu.rob.rob_writes 195513856 # The number of ROB writes -system.cpu.timesIdled 23729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 835509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3770926 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158236329 # The number of ROB reads +system.cpu.rob.rob_writes 195501562 # The number of ROB writes +system.cpu.timesIdled 24613 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 824041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940183 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940183 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063623 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063623 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102275291 # number of integer regfile reads -system.cpu.int_regfile_writes 56793629 # number of integer regfile writes +system.cpu.cpi 0.940559 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940559 # CPI: Total CPI of All Threads +system.cpu.ipc 1.063197 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.063197 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102271310 # number of integer regfile reads +system.cpu.int_regfile_writes 56791274 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346102642 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804681 # number of cc regfile writes -system.cpu.misc_regfile_reads 44209969 # number of misc regfile reads +system.cpu.cc_regfile_reads 346086877 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805113 # number of cc regfile writes +system.cpu.misc_regfile_reads 44208470 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485047 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.741433 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40420740 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485559 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.245785 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 153056500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.741433 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997542 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997542 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485016 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.742621 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40419295 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.248124 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152905500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.742621 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997544 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997544 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615723 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21498446 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21498446 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830779 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830779 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60221 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60221 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15346 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15346 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84611982 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84611982 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21497006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21497006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830802 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830802 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60196 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60196 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15349 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15349 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40329225 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40329225 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40389446 # number of overall hits -system.cpu.dcache.overall_hits::total 40389446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 556041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 556041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019122 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019122 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68628 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68628 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 580 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 580 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1575163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643791 # number of overall misses -system.cpu.dcache.overall_misses::total 1643791 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8960046000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8960046000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14598887903 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14598887903 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23558933903 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23558933903 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23558933903 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23558933903 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40327808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40327808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40388004 # number of overall hits +system.cpu.dcache.overall_hits::total 40388004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 555640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 555640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019099 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019099 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68639 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68639 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1574739 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1574739 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1643378 # number of overall misses +system.cpu.dcache.overall_misses::total 1643378 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9002363000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9002363000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14580629410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14580629410 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5329000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5329000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23582992410 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23582992410 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23582992410 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23582992410 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22052646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22052646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128849 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128835 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128835 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033237 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033237 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025212 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051341 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532623 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532623 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036418 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036418 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037589 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037589 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039107 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039107 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9029.310345 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9029.310345 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14956.505392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14332.073787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3099418 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41902547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41902547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42031382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42031382 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025196 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025196 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051340 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051340 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532767 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532767 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036230 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036230 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039099 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9235.701906 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9235.701906 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14975.810220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14350.315271 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3096615 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130265 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.166667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.793175 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 130248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.774760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 261117 # number of writebacks -system.cpu.dcache.writebacks::total 261117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256598 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256598 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870592 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870592 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 580 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 580 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1127190 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1127190 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1127190 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1127190 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148530 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2013580000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2013580000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5545966465 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5545966465 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7559546465 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7559546465 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3220458500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3220458500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2349684961 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2349684961 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2014368500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2014368500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5570143461 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5570143461 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7584511961 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7584511961 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013578 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013578 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291807 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10664.154781 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15839.628122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15839.628122 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53556.932734 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53556.932734 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12380.135555 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12380.135555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15568.396863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15568.396863 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323114 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.416150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1108313500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.289801 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996660 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996660 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 353 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 350 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45857337 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45857337 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22432857 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22432857 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22432857 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22432857 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22432857 # number of overall hits -system.cpu.icache.overall_hits::total 22432857 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334131 # number of overall misses -system.cpu.icache.overall_misses::total 334131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372669901 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3372669901 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3372669901 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3372669901 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3372669901 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3372669901 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22763216 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22763216 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22763216 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014668 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014668 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014668 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10145.567343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10145.567343 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 275055 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16465 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.705436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10770 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10770 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10770 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323361 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323361 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323361 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323361 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323361 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323361 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3089767447 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3089767447 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3089767447 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3089767447 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3089767447 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3089767447 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9555.164188 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9555.164188 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10762 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10762 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10762 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10622734578 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 672201000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 672201000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 652903000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 652903000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2499575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2499575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 652903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3171776500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3824679500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 652903000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3171776500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10622734578 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14447414078 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028576 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060123 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092103 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092103 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059915 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.199213 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.198976 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 358995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 498597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 141207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323361 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336991 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406890 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20694144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47787264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68481408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 270774 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1887575 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.143443 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.350524 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 1616280 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 807659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 20376 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 20194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 351517 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 505600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 141126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323124 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336969 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2345110 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20679232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47313728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67992960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 270457 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1886726 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.095537 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.294284 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1616816 85.66% 85.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 270759 14.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1706655 90.46% 90.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 179889 9.53% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 182 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1887575 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1069525000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1886726 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1061889000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485192198 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485111148 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728416355 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728499095 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 137050 # Transaction distribution -system.membus.trans_dist::Writeback 97878 # Transaction distribution -system.membus.trans_dist::CleanEvict 30539 # Transaction distribution +system.membus.trans_dist::ReadResp 136869 # Transaction distribution +system.membus.trans_dist::Writeback 97768 # Transaction distribution +system.membus.trans_dist::CleanEvict 30364 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8386 # Transaction distribution -system.membus.trans_dist::ReadExResp 8386 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 137050 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 419301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 419301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15572096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15572096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8324 # Transaction distribution +system.membus.trans_dist::ReadExResp 8324 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 136869 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 418530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15549504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15549504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273859 # Request fanout histogram +system.membus.snoop_fanout::samples 273331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273859 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 273331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273859 # Request fanout histogram -system.membus.reqLayer0.occupancy 740935905 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 273331 # Request fanout histogram +system.membus.reqLayer0.occupancy 739892708 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 757820949 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 756443702 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 46df80677..617d9f369 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208801 # Nu sim_ticks 1208800797500 # Number of ticks simulated final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239332 # Simulator instruction rate (inst/s) -host_op_rate 239332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158403619 # Simulator tick rate (ticks/s) -host_mem_usage 291552 # Number of bytes of host memory used -host_seconds 7631.14 # Real time elapsed on the host +host_inst_rate 309355 # Simulator instruction rate (inst/s) +host_op_rate 309355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204748768 # Simulator tick rate (ticks/s) +host_mem_usage 299532 # Number of bytes of host memory used +host_seconds 5903.82 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -703,6 +703,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution @@ -718,15 +724,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095235 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293539 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18249028 90.48% 90.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1920882 9.52% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index cb7ba764c..bb4922b1c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669557 # Nu sim_ticks 669556582000 # Number of ticks simulated final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125035 # Simulator instruction rate (inst/s) -host_op_rate 125035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48223337 # Simulator tick rate (ticks/s) -host_mem_usage 292576 # Number of bytes of host memory used -host_seconds 13884.49 # Real time elapsed on the host +host_inst_rate 160543 # Simulator instruction rate (inst/s) +host_op_rate 160543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61918292 # Simulator tick rate (ticks/s) +host_mem_usage 299292 # Number of bytes of host memory used +host_seconds 10813.55 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1026,6 +1026,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution @@ -1041,15 +1047,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.094800 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292938 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18419494 90.52% 90.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1929031 9.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 018ebe8b0..d971ffdfc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623057 # Nu sim_ticks 2623057163500 # Number of ticks simulated final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1251674 # Simulator instruction rate (inst/s) -host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1804181213 # Simulator tick rate (ticks/s) -host_mem_usage 294596 # Number of bytes of host memory used -host_seconds 1453.88 # Real time elapsed on the host +host_inst_rate 1405944 # Simulator instruction rate (inst/s) +host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2026548224 # Simulator tick rate (ticks/s) +host_mem_usage 297224 # Number of bytes of host memory used +host_seconds 1294.35 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -478,6 +478,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution @@ -493,15 +499,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index bd1131ae5..766f60b6c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116876 # Number of seconds simulated -sim_ticks 1116876142500 # Number of ticks simulated -final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865669500 # Number of ticks simulated +final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161785 # Simulator instruction rate (inst/s) -host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116987267 # Simulator tick rate (ticks/s) -host_mem_usage 309392 # Number of bytes of host memory used -host_seconds 9546.99 # Real time elapsed on the host +host_inst_rate 226280 # Simulator instruction rate (inst/s) +host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163622006 # Simulator tick rate (ticks/s) +host_mem_usage 317884 # Number of bytes of host memory used +host_seconds 6825.89 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory -system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046592 # Number of read requests accepted -system.physmem.writeReqs 1050124 # Number of write requests accepted -system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue -system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.writeReqs 1050123 # Number of write requests accepted +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue +system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127284 # Per bank write bursts -system.physmem.perBankRdBursts::1 124662 # Per bank write bursts -system.physmem.perBankRdBursts::2 121597 # Per bank write bursts +system.physmem.perBankRdBursts::0 127282 # Per bank write bursts +system.physmem.perBankRdBursts::1 124660 # Per bank write bursts +system.physmem.perBankRdBursts::2 121599 # Per bank write bursts system.physmem.perBankRdBursts::3 123658 # Per bank write bursts -system.physmem.perBankRdBursts::4 122617 # Per bank write bursts +system.physmem.perBankRdBursts::4 122616 # Per bank write bursts system.physmem.perBankRdBursts::5 122675 # Per bank write bursts system.physmem.perBankRdBursts::6 123246 # Per bank write bursts -system.physmem.perBankRdBursts::7 123759 # Per bank write bursts +system.physmem.perBankRdBursts::7 123764 # Per bank write bursts system.physmem.perBankRdBursts::8 131397 # Per bank write bursts -system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132080 # Per bank write bursts -system.physmem.perBankRdBursts::11 133309 # Per bank write bursts -system.physmem.perBankRdBursts::12 133252 # Per bank write bursts -system.physmem.perBankRdBursts::13 133368 # Per bank write bursts -system.physmem.perBankRdBursts::14 129308 # Per bank write bursts -system.physmem.perBankRdBursts::15 129546 # Per bank write bursts +system.physmem.perBankRdBursts::9 133514 # Per bank write bursts +system.physmem.perBankRdBursts::10 132084 # Per bank write bursts +system.physmem.perBankRdBursts::11 133304 # Per bank write bursts +system.physmem.perBankRdBursts::12 133248 # Per bank write bursts +system.physmem.perBankRdBursts::13 133365 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts +system.physmem.perBankRdBursts::15 129545 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts @@ -71,34 +71,34 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65435 # Per bank write bursts -system.physmem.perBankWrBursts::8 67311 # Per bank write bursts -system.physmem.perBankWrBursts::9 67795 # Per bank write bursts -system.physmem.perBankWrBursts::10 67548 # Per bank write bursts -system.physmem.perBankWrBursts::11 67883 # Per bank write bursts -system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::11 67882 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116876049000 # Total gap between requests +system.physmem.totGap 1116865575000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046592 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1050124 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050123 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes @@ -220,76 +220,76 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads -system.physmem.totQLat 38139021250 # Total ticks spent queuing -system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads +system.physmem.totQLat 38113681000 # Total ticks spent queuing +system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 773003 # Number of row buffer hits during reads -system.physmem.writeRowHits 411872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes -system.physmem.avgGap 360664.67 # Average gap between requests +system.physmem.readRowHits 773150 # Number of row buffer hits during reads +system.physmem.writeRowHits 411758 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.183278 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.167175 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states +system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.276976 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.287251 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639069 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted +system.cpu.branchPred.lookups 239639075 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits +system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. @@ -412,68 +412,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233752285 # number of cpu cycles simulated +system.cpu.numCycles 2233731339 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446203 # CPI: cycles per instruction -system.cpu.ipc 0.691466 # IPC: instructions per cycle -system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221039 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits -system.cpu.dcache.overall_hits::total 624218783 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits +system.cpu.dcache.overall_hits::total 624218772 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses -system.cpu.dcache.overall_misses::total 9589485 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses +system.cpu.dcache.overall_misses::total 9589497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,10 +482,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -496,14 +496,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,12 +516,12 @@ system.cpu.dcache.writebacks::writebacks 3684564 # nu system.cpu.dcache.writebacks::total 3684564 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses @@ -532,16 +532,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -552,24 +552,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id @@ -577,44 +577,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits -system.cpu.icache.overall_hits::total 465281345 # number of overall hits +system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits +system.cpu.icache.overall_hits::total 465281545 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -629,35 +629,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013891 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013890 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy @@ -668,46 +668,46 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits -system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits +system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 801155 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045808 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses -system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) @@ -734,18 +734,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.221830 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks -system.cpu.l2cache.writebacks::total 1050124 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks +system.cpu.l2cache.writebacks::total 1050123 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits @@ -768,30 +768,30 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 4 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62409666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62409666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51871000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51871000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96199045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96199045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51871000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses @@ -806,21 +806,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution @@ -832,18 +838,18 @@ system.cpu.toL2Bus.pkt_count::total 27671384 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram +system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) @@ -851,29 +857,29 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 1245436 # Transaction distribution -system.membus.trans_dist::Writeback 1050124 # Transaction distribution +system.membus.trans_dist::Writeback 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962723 # Transaction distribution -system.membus.trans_dist::ReadExReq 801156 # Transaction distribution -system.membus.trans_dist::ReadExResp 801156 # Transaction distribution +system.membus.trans_dist::ReadExReq 801155 # Transaction distribution +system.membus.trans_dist::ReadExResp 801155 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059439 # Request fanout histogram +system.membus.snoop_fanout::samples 4059437 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059439 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059437 # Request fanout histogram +system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d6d64bb1d..09d71d56d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770368 # Number of seconds simulated -sim_ticks 770368138000 # Number of ticks simulated -final_tick 770368138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770336 # Number of seconds simulated +sim_ticks 770336310500 # Number of ticks simulated +final_tick 770336310500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139680 # Simulator instruction rate (inst/s) -host_op_rate 150484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69667014 # Simulator tick rate (ticks/s) -host_mem_usage 312136 # Number of bytes of host memory used -host_seconds 11057.86 # Real time elapsed on the host +host_inst_rate 130811 # Simulator instruction rate (inst/s) +host_op_rate 140929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65240720 # Simulator tick rate (ticks/s) +host_mem_usage 314688 # Number of bytes of host memory used +host_seconds 11807.60 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238160448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63905024 # Number of bytes read from this memory -system.physmem.bytes_read::total 302131264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104870272 # Number of bytes written to this memory -system.physmem.bytes_written::total 104870272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3721257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 998516 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720801 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309151477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82953877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392190758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136130074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309151477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82953877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528320833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720801 # Number of read requests accepted -system.physmem.writeReqs 1638598 # Number of write requests accepted -system.physmem.readBursts 4720801 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638598 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301683008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448256 # Total number of bytes read from write queue -system.physmem.bytesWritten 104867648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302131264 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104870272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7004 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238054976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63977600 # Number of bytes read from this memory +system.physmem.bytes_read::total 302099072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104804160 # Number of bytes written to this memory +system.physmem.bytes_written::total 104804160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3719609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 999650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1637565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1637565 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 86321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309027334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83051518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392165172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136049877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 86321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309027334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83051518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528215049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720298 # Number of read requests accepted +system.physmem.writeReqs 1637565 # Number of write requests accepted +system.physmem.readBursts 4720298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1637565 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301639360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 459712 # Total number of bytes read from write queue +system.physmem.bytesWritten 104801536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302099072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104804160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7183 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296472 # Per bank write bursts -system.physmem.perBankRdBursts::1 294660 # Per bank write bursts -system.physmem.perBankRdBursts::2 288575 # Per bank write bursts -system.physmem.perBankRdBursts::3 292960 # Per bank write bursts -system.physmem.perBankRdBursts::4 290749 # Per bank write bursts -system.physmem.perBankRdBursts::5 289530 # Per bank write bursts -system.physmem.perBankRdBursts::6 284828 # Per bank write bursts -system.physmem.perBankRdBursts::7 280913 # Per bank write bursts -system.physmem.perBankRdBursts::8 297084 # Per bank write bursts -system.physmem.perBankRdBursts::9 304004 # Per bank write bursts -system.physmem.perBankRdBursts::10 295272 # Per bank write bursts -system.physmem.perBankRdBursts::11 301446 # Per bank write bursts -system.physmem.perBankRdBursts::12 303554 # Per bank write bursts -system.physmem.perBankRdBursts::13 302544 # Per bank write bursts -system.physmem.perBankRdBursts::14 297853 # Per bank write bursts -system.physmem.perBankRdBursts::15 293353 # Per bank write bursts -system.physmem.perBankWrBursts::0 103842 # Per bank write bursts -system.physmem.perBankWrBursts::1 101847 # Per bank write bursts -system.physmem.perBankWrBursts::2 99335 # Per bank write bursts -system.physmem.perBankWrBursts::3 100097 # Per bank write bursts -system.physmem.perBankWrBursts::4 99287 # Per bank write bursts -system.physmem.perBankWrBursts::5 99035 # Per bank write bursts -system.physmem.perBankWrBursts::6 102669 # Per bank write bursts -system.physmem.perBankWrBursts::7 104576 # Per bank write bursts -system.physmem.perBankWrBursts::8 105230 # Per bank write bursts -system.physmem.perBankWrBursts::9 104522 # Per bank write bursts -system.physmem.perBankWrBursts::10 102176 # Per bank write bursts -system.physmem.perBankWrBursts::11 103126 # Per bank write bursts -system.physmem.perBankWrBursts::12 103102 # Per bank write bursts -system.physmem.perBankWrBursts::13 102725 # Per bank write bursts -system.physmem.perBankWrBursts::14 104361 # Per bank write bursts -system.physmem.perBankWrBursts::15 102627 # Per bank write bursts +system.physmem.perBankRdBursts::0 296850 # Per bank write bursts +system.physmem.perBankRdBursts::1 294498 # Per bank write bursts +system.physmem.perBankRdBursts::2 288916 # Per bank write bursts +system.physmem.perBankRdBursts::3 292682 # Per bank write bursts +system.physmem.perBankRdBursts::4 290729 # Per bank write bursts +system.physmem.perBankRdBursts::5 289596 # Per bank write bursts +system.physmem.perBankRdBursts::6 284483 # Per bank write bursts +system.physmem.perBankRdBursts::7 281209 # Per bank write bursts +system.physmem.perBankRdBursts::8 297427 # Per bank write bursts +system.physmem.perBankRdBursts::9 303552 # Per bank write bursts +system.physmem.perBankRdBursts::10 295336 # Per bank write bursts +system.physmem.perBankRdBursts::11 302232 # Per bank write bursts +system.physmem.perBankRdBursts::12 303231 # Per bank write bursts +system.physmem.perBankRdBursts::13 302345 # Per bank write bursts +system.physmem.perBankRdBursts::14 297342 # Per bank write bursts +system.physmem.perBankRdBursts::15 292687 # Per bank write bursts +system.physmem.perBankWrBursts::0 104014 # Per bank write bursts +system.physmem.perBankWrBursts::1 101992 # Per bank write bursts +system.physmem.perBankWrBursts::2 99263 # Per bank write bursts +system.physmem.perBankWrBursts::3 99947 # Per bank write bursts +system.physmem.perBankWrBursts::4 99433 # Per bank write bursts +system.physmem.perBankWrBursts::5 98879 # Per bank write bursts +system.physmem.perBankWrBursts::6 102579 # Per bank write bursts +system.physmem.perBankWrBursts::7 104318 # Per bank write bursts +system.physmem.perBankWrBursts::8 105363 # Per bank write bursts +system.physmem.perBankWrBursts::9 104471 # Per bank write bursts +system.physmem.perBankWrBursts::10 102169 # Per bank write bursts +system.physmem.perBankWrBursts::11 102930 # Per bank write bursts +system.physmem.perBankWrBursts::12 102920 # Per bank write bursts +system.physmem.perBankWrBursts::13 102581 # Per bank write bursts +system.physmem.perBankWrBursts::14 104115 # Per bank write bursts +system.physmem.perBankWrBursts::15 102550 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770367991500 # Total gap between requests +system.physmem.totGap 770336158500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720801 # Read request sizes (log2) +system.physmem.readPktSize::6 4720298 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638598 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2785137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1045602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1637565 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2783946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1045590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 328353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 151285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,115 +197,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4291005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.744514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.906714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.391830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3416666 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676199 15.76% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96816 2.26% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35217 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22960 0.54% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11971 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7013 0.16% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5097 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19066 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4291005 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.759952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.369236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.446894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 96231 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1192 1.21% 98.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 746 0.76% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 392 0.40% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 102 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 22 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.751761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.903148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.431882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3416049 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675171 15.74% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96645 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35451 0.83% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23003 0.54% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12074 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6995 0.16% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5025 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19100 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289513 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.769871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.372187 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.540692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 96215 97.52% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1195 1.21% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 729 0.74% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 403 0.41% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 87 0.09% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98697 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.601893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.567781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.107607 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72640 73.60% 73.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1756 1.78% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18593 18.84% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3904 3.96% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1031 1.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 392 0.40% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 184 0.19% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 91 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 55 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98662 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.597312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.563431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.103098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72815 73.80% 73.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1780 1.80% 75.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18354 18.60% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3927 3.98% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 986 1.00% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 404 0.41% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 201 0.20% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 116 0.12% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 44 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98697 # Writes before turning the bus around for reads -system.physmem.totQLat 131099404549 # Total ticks spent queuing -system.physmem.totMemAccLat 219483098299 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23568985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27811.85 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 98662 # Writes before turning the bus around for reads +system.physmem.totQLat 131160021238 # Total ticks spent queuing +system.physmem.totMemAccLat 219530927488 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27828.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46561.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46578.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.12 # Data bus utilization in percentage system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 1707890 # Number of row buffer hits during reads -system.physmem.writeRowHits 353447 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.57 # Row buffer hit rate for writes -system.physmem.avgGap 121138.49 # Average gap between requests -system.physmem.pageHitRate 32.45 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16077957840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8772695250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18085189200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253161040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410294660580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102310835250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611110917000 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.275483 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167665323859 # Time in different power states -system.physmem_0.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 1707273 # Number of row buffer hits during reads +system.physmem.writeRowHits 353841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.61 # Row buffer hit rate for writes +system.physmem.avgGap 121162.75 # Average gap between requests +system.physmem.pageHitRate 32.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16082924760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8775405375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087474600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5251508640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409609386630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102893262750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611014346355 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.182199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168633417027 # Time in different power states +system.physmem_0.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 576975365641 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575976400473 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16361828280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8927584875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18681803400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5364480960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 411044339970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101653218750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612349674075 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.883504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166565047661 # Time in different power states -system.physmem_1.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem_1.actEnergy 16345687680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8918778000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18674323200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5359543200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410844304170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101810001750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612267021600 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.808347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 166829398639 # Time in different power states +system.physmem_1.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 578076556839 # Time in different power states +system.physmem_1.memoryStateTime::ACT 577780670361 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286273758 # Number of BP lookups -system.cpu.branchPred.condPredicted 223402774 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14629982 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157694112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150348271 # Number of BTB hits +system.cpu.branchPred.lookups 286278310 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158227088 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150348964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.341715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640713 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.021002 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641238 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,128 +424,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540736277 # number of cpu cycles simulated +system.cpu.numCycles 1540672622 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067435227 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286273758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166988984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512088964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284609 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656921798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 960 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13926355 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067514794 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286278310 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166990202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512022873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284737 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1021 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940964 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 966 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458280922 29.75% 29.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465413379 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101412163 6.58% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515551693 33.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458181319 29.74% 29.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465421558 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101422593 6.58% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515567335 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185803 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341849 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74641640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543291473 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849963258 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58120186 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641600 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 756 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037144212 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52474408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641600 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139712786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462567620 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837837029 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85884184 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976322026 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26747258 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146985 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1471751 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25027790 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985779948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127891240 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432801848 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185814 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341956 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74646858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543216907 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849967493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58119883 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201795 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 757 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037179352 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52470113 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139717275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462450514 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837848883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85920553 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976355004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26745374 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45156757 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1486003 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25049006 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985823032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128033727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432836892 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310881003 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 151 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111429534 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542545285 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199304809 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26862690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28866621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947900293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857514523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13512332 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283868093 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647012526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540658157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150942 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310924087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 148 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111428528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542554069 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199305704 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26941972 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29270810 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947933260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857474146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283901059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647116126 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540592805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587771265 38.15% 38.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326011747 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378176386 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219651217 14.26% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29041357 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6185 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587702275 38.15% 38.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325996808 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378232244 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219639231 14.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29016078 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540658157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540592805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166072420 40.95% 40.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2002 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191493456 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47936528 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166081126 41.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1996 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191505284 47.27% 88.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47530605 11.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138226056 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801017 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138242397 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801060 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -567,90 +567,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 32 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532163815 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186323583 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532116023 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186314612 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857514523 # Type of FU issued -system.cpu.iq.rate 1.205602 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405504406 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218305 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674703700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231781287 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805692489 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 241 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263018794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17823551 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857474146 # Type of FU issued +system.cpu.iq.rate 1.205625 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405119011 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218102 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674157044 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231847189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805703414 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262593018 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811740 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84238951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66626 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13177 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24457764 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84247735 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24458659 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4548930 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4887285 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4504401 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4884981 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641600 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25334604 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297189 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947900591 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25329983 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1325123 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947933556 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542545285 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199304809 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1136868 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13177 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700706 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703944 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404650 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827845280 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516985272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29669243 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542554069 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199305704 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1165002 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13149 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699177 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705456 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404633 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827812064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516937908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 698740184 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542491 # Number of branches executed -system.cpu.iew.exec_stores 181754912 # Number of stores executed -system.cpu.iew.exec_rate 1.186345 # Inst execution rate -system.cpu.iew.wb_sent 1808718850 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805692560 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243952 # num instructions producing a value -system.cpu.iew.wb_consumers 1689620594 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698690935 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542500 # Number of branches executed +system.cpu.iew.exec_stores 181753027 # Number of stores executed +system.cpu.iew.exec_rate 1.186373 # Inst execution rate +system.cpu.iew.wb_sent 1808734068 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805703486 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169239698 # num instructions producing a value +system.cpu.iew.wb_consumers 1689624086 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.171967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692016 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172023 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257974948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258007667 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629278 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501179372 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025812 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501111622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920919616 61.35% 61.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250623048 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110074231 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55314266 3.68% 89.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29240414 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34051194 2.27% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24724968 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18102388 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58129247 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920819202 61.34% 61.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250634053 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110061016 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55281373 3.68% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29321487 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34081425 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716781 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18131809 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064476 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501179372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501111622 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -696,76 +696,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58129247 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365056908 # The number of ROB reads -system.cpu.rob.rob_writes 3883498749 # The number of ROB writes -system.cpu.timesIdled 826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78120 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064476 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365086648 # The number of ROB reads +system.cpu.rob.rob_writes 3883566462 # The number of ROB writes +system.cpu.timesIdled 859 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997522 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997522 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002484 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002484 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175832090 # number of integer regfile reads -system.cpu.int_regfile_writes 1261554579 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 53 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965806989 # number of cc regfile reads -system.cpu.cc_regfile_writes 551858746 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847493 # number of misc regfile reads +system.cpu.cpi 0.997481 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997481 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002525 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002525 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175803949 # number of integer regfile reads +system.cpu.int_regfile_writes 1261568723 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965710140 # number of cc regfile reads +system.cpu.cc_regfile_writes 551865181 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846539 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004655 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638048144 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005167 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.520840 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004606 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964973 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638063275 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005118 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.521838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77839500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964973 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335675523 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335675523 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469328921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469328921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719105 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719105 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335698850 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335698850 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469343498 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469343498 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719659 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719659 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638048026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638048026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638048026 # number of overall hits -system.cpu.dcache.overall_hits::total 638048026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17420086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17420086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3866942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3866942 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638063157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638063157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638063157 # number of overall hits +system.cpu.dcache.overall_hits::total 638063157 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417197 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417197 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3866388 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3866388 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287030 # number of overall misses -system.cpu.dcache.overall_misses::total 21287030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 565504327211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 565504327211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486749007 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486749007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283587 # number of overall misses +system.cpu.dcache.overall_misses::total 21283587 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 565378829442 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 565378829442 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486760695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486760695 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -774,74 +774,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659335054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659335054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659335056 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659335056 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659346742 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659346742 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659346744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659346744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022403 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022403 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26565.677802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26565.675306 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20779473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3451346 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 944816 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67198 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.993143 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.360844 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26564.078817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26564.076320 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20755892 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3446894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67143 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.928473 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.336610 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837348 # number of writebacks -system.cpu.dcache.writebacks::total 4837348 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835415 # number of writebacks +system.cpu.dcache.writebacks::total 4835415 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1128832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1128832 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281862 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281862 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737537 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737537 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4278468 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4278468 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737556 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737556 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17005167 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005167 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005118 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005118 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029312 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029312 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -850,361 +850,364 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 582 # number of replacements -system.cpu.icache.tags.tagsinuse 445.815002 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656920172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1070 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 613944.085981 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 592 # number of replacements +system.cpu.icache.tags.tagsinuse 446.127099 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656939322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1080 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 608277.150000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.815002 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.127099 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313844660 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313844660 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656920172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656920172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656920172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656920172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656920172 # number of overall hits -system.cpu.icache.overall_hits::total 656920172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1623 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1623 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1623 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1623 # number of overall misses -system.cpu.icache.overall_misses::total 1623 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104193985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104193985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104193985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104193985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104193985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104193985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656921795 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656921795 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656921795 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656921795 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656921795 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656921795 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313883006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313883006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656939322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656939322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656939322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656939322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656939322 # number of overall hits +system.cpu.icache.overall_hits::total 656939322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1641 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1641 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1641 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1641 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1641 # number of overall misses +system.cpu.icache.overall_misses::total 1641 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 107375484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 107375484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 107375484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 107375484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 107375484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 107375484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656940963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656940963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656940963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656940963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656940963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656940963 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64198.388786 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64198.388786 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64198.388786 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64198.388786 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17135 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 748 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.184211 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65432.957952 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65432.957952 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65432.957952 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65432.957952 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18112 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1654 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 165.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 553 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 553 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 553 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 553 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 553 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 553 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1070 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1070 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1070 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1070 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1070 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1070 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75689488 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75689488 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75689488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75689488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75689488 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75689488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 561 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 561 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 561 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 561 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 561 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 561 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1080 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1080 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1080 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1080 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1080 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1080 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76771987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76771987 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11618797 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638031 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 14266 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11620529 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640215 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 14721 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4656553 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4712696 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16129.917520 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27373018 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4728623 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.788793 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29478535500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5230.477637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.698420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7539.676601 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3341.064863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.319243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.460185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.203922 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 811 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 615 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1857 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049500 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922607 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 551304223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 551304223 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 4837348 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4837348 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752512 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312623157999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 312691326499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68168500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312623157999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72748405464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 385439731963 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1637565 # number of writebacks +system.cpu.l2cache.writebacks::total 1637565 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 4105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45593 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45593 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49698 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49698 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 49698 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49698 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100082 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 100082 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1001959 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1001959 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 980506 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 980506 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1039 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1039 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2738435 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2738435 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1039 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3718941 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3719980 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1039 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3718941 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1001959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4721939 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72923665986 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72923665986 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93548158999 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93548158999 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 69146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 69146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218917649000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218917649000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312465807999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 312534953999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312465807999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72923665986 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385458619985 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960748 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.218848 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.962037 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.191935 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.191935 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.218743 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277745 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277660 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 14268653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6475946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15220389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1280497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993396 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50996114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397921024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397989504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 5993194 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40004669 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.149812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.356887 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34011398 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17005208 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21592 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 111772 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 111653 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14268599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6472980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15222988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1281199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267519 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50996002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397794112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397863232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 5993561 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40004959 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062190 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34011476 85.02% 85.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5993193 14.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 39849994 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 154846 0.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 119 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40004669 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21843087497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40004959 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21841114998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1605000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1620000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507754991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25507681990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3739456 # Transaction distribution -system.membus.trans_dist::Writeback 1638598 # Transaction distribution -system.membus.trans_dist::CleanEvict 3064906 # Transaction distribution -system.membus.trans_dist::ReadExReq 981345 # Transaction distribution -system.membus.trans_dist::ReadExResp 981345 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3739456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407001536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 407001536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3739654 # Transaction distribution +system.membus.trans_dist::Writeback 1637565 # Transaction distribution +system.membus.trans_dist::CleanEvict 3065415 # Transaction distribution +system.membus.trans_dist::ReadExReq 980644 # Transaction distribution +system.membus.trans_dist::ReadExResp 980644 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3739654 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406903232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406903232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9424305 # Request fanout histogram +system.membus.snoop_fanout::samples 9423278 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9424305 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9423278 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9424305 # Request fanout histogram -system.membus.reqLayer0.occupancy 17323735553 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9423278 # Request fanout histogram +system.membus.reqLayer0.occupancy 17318873513 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25676323677 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25673835894 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 939603453..3fad64f8d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363367 # Number of seconds simulated -sim_ticks 2363367211500 # Number of ticks simulated -final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363368 # Number of seconds simulated +sim_ticks 2363368369500 # Number of ticks simulated +final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1091670 # Simulator instruction rate (inst/s) -host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1676685643 # Simulator tick rate (ticks/s) -host_mem_usage 312924 # Number of bytes of host memory used -host_seconds 1409.55 # Real time elapsed on the host +host_inst_rate 1008024 # Simulator instruction rate (inst/s) +host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1548215415 # Simulator tick rate (ticks/s) +host_mem_usage 315828 # Number of bytes of host memory used +host_seconds 1526.51 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1951712 # Nu system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4726734423 # number of cpu cycles simulated +system.cpu.numCycles 4726736739 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,34 +411,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy @@ -482,14 +482,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) @@ -520,14 +520,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,14 +556,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses @@ -582,15 +582,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution @@ -606,15 +612,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 6d8265542..c34bcec93 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882285 # Nu sim_ticks 5882284743500 # Number of ticks simulated final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 724530 # Simulator instruction rate (inst/s) -host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1416814365 # Simulator tick rate (ticks/s) -host_mem_usage 314268 # Number of bytes of host memory used -host_seconds 4151.77 # Real time elapsed on the host +host_inst_rate 704974 # Simulator instruction rate (inst/s) +host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1378571885 # Simulator tick rate (ticks/s) +host_mem_usage 317252 # Number of bytes of host memory used +host_seconds 4266.94 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 5fb393485..11356e644 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229005 # Simulator instruction rate (inst/s) -host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129351336 # Simulator tick rate (ticks/s) -host_mem_usage 295204 # Number of bytes of host memory used -host_seconds 401.31 # Real time elapsed on the host +host_inst_rate 339215 # Simulator instruction rate (inst/s) +host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191602600 # Simulator tick rate (ticks/s) +host_mem_usage 303192 # Number of bytes of host memory used +host_seconds 270.93 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -663,6 +663,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution @@ -678,15 +684,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f7c0c31d6..cc5b93144 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021919 # Nu sim_ticks 21919473500 # Number of ticks simulated final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134628 # Simulator instruction rate (inst/s) -host_op_rate 134628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35055621 # Simulator tick rate (ticks/s) -host_mem_usage 296224 # Number of bytes of host memory used -host_seconds 625.28 # Real time elapsed on the host +host_inst_rate 199769 # Simulator instruction rate (inst/s) +host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52017673 # Simulator tick rate (ticks/s) +host_mem_usage 302932 # Number of bytes of host memory used +host_seconds 421.39 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -971,6 +971,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution @@ -986,15 +992,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 396e2f8dd..13ae4452a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772636500 # Number of ticks simulated -final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 130772642500 # Number of ticks simulated +final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167747 # Simulator instruction rate (inst/s) -host_op_rate 176832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127303889 # Simulator tick rate (ticks/s) -host_mem_usage 312696 # Number of bytes of host memory used -host_seconds 1027.25 # Real time elapsed on the host +host_inst_rate 233615 # Simulator instruction rate (inst/s) +host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177290947 # Simulator tick rate (ticks/s) +host_mem_usage 321196 # Number of bytes of host memory used +host_seconds 737.62 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,12 +22,12 @@ system.physmem.num_reads::cpu.inst 2158 # Nu system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772543000 # Total gap between requests +system.physmem.totGap 130772548000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # By system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 28055750 # Total ticks spent queuing -system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 27654500 # Total ticks spent queuing +system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 2957 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826317.38 # Average gap between requests +system.physmem.avgGap 33826318.68 # Average gap between requests system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826718 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states +system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.826558 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811822 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states +system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811714 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49732170 # Number of BP lookups system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted @@ -377,7 +377,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545273 # number of cpu cycles simulated +system.cpu.numCycles 261545285 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed @@ -386,15 +386,15 @@ system.cpu.discardedOps 11660914 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.517808 # CPI: cycles per instruction system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 2442 # n system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,24 +518,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -559,12 +559,12 @@ system.cpu.icache.demand_misses::cpu.inst 4685 # n system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses @@ -577,12 +577,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4685 system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 3883 # nu system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3883 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.597844 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3867 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b0d8b3c34..7a60aaca0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085022 # Number of seconds simulated -sim_ticks 85021523000 # Number of ticks simulated -final_tick 85021523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085039 # Number of seconds simulated +sim_ticks 85038866000 # Number of ticks simulated +final_tick 85038866000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136979 # Simulator instruction rate (inst/s) -host_op_rate 144399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67591393 # Simulator tick rate (ticks/s) -host_mem_usage 315696 # Number of bytes of host memory used -host_seconds 1257.88 # Real time elapsed on the host +host_inst_rate 124768 # Simulator instruction rate (inst/s) +host_op_rate 131526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61578459 # Simulator tick rate (ticks/s) +host_mem_usage 316956 # Number of bytes of host memory used +host_seconds 1380.98 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71104 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1111 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 562305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 836306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2892068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 562305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 836306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2892068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71424 # Number of bytes read from this memory +system.physmem.bytes_read::total 246336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3849 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 562943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2896746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 562943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2896746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3849 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3849 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246336 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246336 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 220 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts -system.physmem.perBankRdBursts::4 307 # Per bank write bursts +system.physmem.perBankRdBursts::3 318 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 232 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85021379500 # Total gap between requests +system.physmem.totGap 85038722500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3849 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.174026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.484323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.262764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239 31.04% 31.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 25.19% 56.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 10.65% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.17% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 3.64% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 4.94% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 1.95% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 2.08% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 9.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 770 # Bytes accessed per row activation -system.physmem.totQLat 41378240 # Total ticks spent queuing -system.physmem.totMemAccLat 113415740 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10769.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.357050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.451466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.377497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 239 30.92% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 25.10% 56.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.87% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 11.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.75% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.79% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 2.07% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.68% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 74 9.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 773 # Bytes accessed per row activation +system.physmem.totQLat 41463141 # Total ticks spent queuing +system.physmem.totMemAccLat 113631891 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10772.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29519.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29522.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.83 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3065 # Number of row buffer hits during reads +system.physmem.readRowHits 3069 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22129458.49 # Average gap between requests -system.physmem.pageHitRate 79.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2766960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1509750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22093718.50 # Average gap between requests +system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2789640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1522125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338310430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48959844750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56871567930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.933066 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81449206260 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_0.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338576335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48968955000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56882066460 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.934025 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81466129254 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 731844740 # Time in different power states +system.physmem_0.memoryStateTime::ACT 731738246 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3039120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1658250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13579800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3031560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1654125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13525200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293221150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48999396750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56863861710 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.842424 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81513735655 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_1.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2304071955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48999213750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56875480350 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.856680 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81513506905 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665661845 # Time in different power states +system.physmem_1.memoryStateTime::ACT 681039595 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85912132 # Number of BP lookups -system.cpu.branchPred.condPredicted 68393043 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40101121 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39014567 # Number of BTB hits +system.cpu.branchPred.lookups 85929659 # Number of BP lookups +system.cpu.branchPred.condPredicted 68408036 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6017804 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40110757 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39021888 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290465 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703090 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.285344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703815 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81895 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170043047 # number of cpu cycles simulated +system.cpu.numCycles 170077733 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613517 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349250630 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85912132 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42717657 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158263984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5627528 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349301730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42725703 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158283885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12049307 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78950646 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18010 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169904018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2380 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78962015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169940212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047263 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361437 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30204201 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31835536 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90502844 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17375065 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30210489 17.78% 28.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838895 18.74% 46.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90515763 53.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169904018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169940212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053895 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17563904 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17112948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122657441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847562 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11134700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306600022 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639979 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847562 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37746058 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8470500 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579781 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108923622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8336495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278650706 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13412569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051463 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842712 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2185705 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36039 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483080897 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196921555 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297573893 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups +system.cpu.fetch.rate 2.053777 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17579546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17112098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122676977 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6721861 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5849730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135516 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190121 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306633664 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649172 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5849730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37767470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8469466 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579515 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108936835 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8337196 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278676031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415385 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051308 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187025 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37328 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483141060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1197017326 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297598208 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006154 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190103968 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336341 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34142087 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2549378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214902707 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219925371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169904018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017464 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190164131 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23437 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13334158 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476937 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2547302 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809047 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264833552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45866 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214914716 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5193890 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83243464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219964835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169940212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52834646 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36093194 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65784220 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574325 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570253 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47194 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52857789 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36101949 21.24% 52.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65794996 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13566772 7.98% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571259 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47259 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169904018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169940212 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605027 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605031 66.12% 66.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152953 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1062 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35733 0.07% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 238 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1038 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1040 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34389 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078476 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945873 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14077055 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945216 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167344168 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167357469 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918949 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165195 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245712 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460561 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206706 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32006913 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373527 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005826 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373316 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214902707 # Type of FU issued -system.cpu.iq.rate 1.263814 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53854783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654801069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204597399 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953766 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266623022 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134468 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601145 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214914716 # Type of FU issued +system.cpu.iq.rate 1.263626 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53852922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250578 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654863168 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346117768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204606131 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011882 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806358 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266633604 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134034 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600995 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6245943 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831898 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7621 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6899 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832303 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25728 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 844 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847562 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681846 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37059 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5849730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682254 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37001 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264895393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34142087 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207521845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720947 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7380862 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476937 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23458 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6899 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482739 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207531016 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721231 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7383700 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15987 # number of nop insts executed -system.cpu.iew.exec_refs 43860767 # number of memory reference insts executed -system.cpu.iew.exec_branches 44934593 # Number of branches executed -system.cpu.iew.exec_stores 13139820 # Number of stores executed -system.cpu.iew.exec_rate 1.220408 # Inst execution rate -system.cpu.iew.wb_sent 206738836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206403842 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129472696 # num instructions producing a value -system.cpu.iew.wb_consumers 221699614 # num instructions consuming a value +system.cpu.iew.exec_nop 15975 # number of nop insts executed +system.cpu.iew.exec_refs 43860800 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937472 # Number of branches executed +system.cpu.iew.exec_stores 13139569 # Number of stores executed +system.cpu.iew.exec_rate 1.220213 # Inst execution rate +system.cpu.iew.wb_sent 206747617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206412489 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129477272 # num instructions producing a value +system.cpu.iew.wb_consumers 221702085 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213833 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584001 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213636 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532937 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69549191 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158463001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646694 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5842881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158496522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646497 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73683575 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276323 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553918 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626893 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2147765 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1281178 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356648 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73710350 46.51% 46.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41283484 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22554549 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626760 6.07% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551822 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2145509 1.35% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989155 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3354602 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158463001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158496522 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,381 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356648 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406284431 # The number of ROB reads -system.cpu.rob.rob_writes 513821512 # The number of ROB writes -system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3354602 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406336252 # The number of ROB reads +system.cpu.rob.rob_writes 513856795 # The number of ROB writes +system.cpu.timesIdled 3529 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 137521 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986884 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986884 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013291 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013291 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218956389 # number of integer regfile reads -system.cpu.int_regfile_writes 114512069 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes -system.cpu.cc_regfile_reads 709567724 # number of cc regfile reads -system.cpu.cc_regfile_writes 229536137 # number of cc regfile writes -system.cpu.misc_regfile_reads 59314172 # number of misc regfile reads +system.cpu.cpi 0.987085 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987085 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013084 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013084 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218963852 # number of integer regfile reads +system.cpu.int_regfile_writes 114515225 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904259 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441612 # number of floating regfile writes +system.cpu.cc_regfile_reads 709595430 # number of cc regfile reads +system.cpu.cc_regfile_writes 229551730 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313283 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72862 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115433 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73374 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.354254 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 72876 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.418230 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73388 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.254401 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.418230 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82529738 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82529738 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729196 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729196 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82530918 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82530918 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341303 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341303 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070516 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070516 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070877 # number of overall hits -system.cpu.dcache.overall_hits::total 41070877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89406 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89406 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41071033 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41071033 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071394 # number of overall hits +system.cpu.dcache.overall_hits::total 41071394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89456 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89456 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22984 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112490 # number of overall misses -system.cpu.dcache.overall_misses::total 112490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 857195000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 857195000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 240069999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 240069999 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 112440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112556 # number of overall misses +system.cpu.dcache.overall_misses::total 112556 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 857049000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 857049000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246637999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246637999 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1097264999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1097264999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28818602 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28818602 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1103686999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1103686999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183367 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183367 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41183473 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41183473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183950 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183950 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9587.667494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9587.667494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10452.823573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10452.823573 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9580.676534 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9580.676534 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9764.489682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9764.489682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9754.333710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9754.333710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9815.786188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9815.786188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9805.670058 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9805.670058 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10364 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11592 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 859 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.967667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.494761 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks -system.cpu.dcache.writebacks::total 64850 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24708 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24708 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64866 # number of writebacks +system.cpu.dcache.writebacks::total 64866 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24759 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24759 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14406 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14406 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73374 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73374 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 646595499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 646595499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39165 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39165 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64697 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64697 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8578 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73388 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73388 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 647585999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 647585999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8812.796874 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8812.796874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8812.324515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8812.324515 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8824.619570 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8824.619570 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8824.140173 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8824.140173 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54433 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603635 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78892635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.847393 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84266921500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603635 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 54478 # number of replacements +system.cpu.icache.tags.tagsinuse 510.603674 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78903878 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54990 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1434.876850 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84285313500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.603674 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157956195 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157956195 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78892635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78892635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78892635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78892635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78892635 # number of overall hits -system.cpu.icache.overall_hits::total 78892635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57990 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57990 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57990 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57990 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57990 # number of overall misses -system.cpu.icache.overall_misses::total 57990 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 602731956 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 602731956 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 602731956 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 602731956 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78950625 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78950625 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78950625 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78950625 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10393.722297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10393.722297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10393.722297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10393.722297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59431 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157978976 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157978976 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78903878 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78903878 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78903878 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78903878 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78903878 # number of overall hits +system.cpu.icache.overall_hits::total 78903878 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 58115 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 58115 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 58115 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 58115 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 58115 # number of overall misses +system.cpu.icache.overall_misses::total 58115 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 612004953 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 612004953 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 612004953 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 612004953 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 612004953 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 612004953 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78961993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78961993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78961993 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78961993 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78961993 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78961993 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10530.929244 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10530.929244 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10530.929244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10530.929244 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 59295 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2848 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2885 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.867626 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.552860 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2293 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016174 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202698 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3935898 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3935898 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 64866 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 64866 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8409 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8409 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52999 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 52999 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 64221 # 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number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2749 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1991 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses +system.cpu.l2cache.overall_misses::total 2749 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19008500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 19008500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 136250000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 136250000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38006500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38006500 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54990 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64740 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 64740 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54945 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73374 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128319 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54945 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73374 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128319 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027102 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027102 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77602.564103 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68600.251256 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68600.251256 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74950.191571 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74950.191571 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68600.251256 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75771.164021 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70574.471959 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68600.251256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75771.164021 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68432.948267 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73230.250482 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73230.250482 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68432.948267 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75217.678100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70303.746817 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68432.948267 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75217.678100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70303.746817 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1038,133 +1037,139 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 6 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 176401000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 124261000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52140000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 69341141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 245742141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1765 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1765 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 237 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 237 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1985 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1985 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2733 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1765 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4498 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70524171 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70524171 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 124005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 124005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34486500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34486500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 124005500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51650000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 175655500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 124005500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51650000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70524171 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 246179671 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027405 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027405 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036097 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021289 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035521 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37953.552819 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71047.210300 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71047.210300 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62631.552419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62631.552419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69233.463035 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69233.463035 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.090809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53914.467091 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035037 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 119685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 255732 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 127373 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 649 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 119730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54990 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217447 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373421 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2169 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257783 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.008414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.091342 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 156105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3519360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8848256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2111 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257843 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.084059 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 255614 99.16% 99.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2169 0.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 236169 91.59% 91.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21674 8.41% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257783 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 257843 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192732000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82431971 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82511447 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110065491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110086990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3609 # Transaction distribution -system.membus.trans_dist::ReadExReq 233 # Transaction distribution -system.membus.trans_dist::ReadExResp 233 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3609 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3612 # Transaction distribution +system.membus.trans_dist::ReadExReq 237 # Transaction distribution +system.membus.trans_dist::ReadExResp 237 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3612 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3849 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3849 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4994667 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3849 # Request fanout histogram +system.membus.reqLayer0.occupancy 5019167 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20261553 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20293808 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cd6ba3bb4..fda8a8b37 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079147 # Number of seconds simulated -sim_ticks 79147317000 # Number of ticks simulated -final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079190 # Number of seconds simulated +sim_ticks 79190347500 # Number of ticks simulated +final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70947 # Simulator instruction rate (inst/s) -host_op_rate 118914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42517019 # Simulator tick rate (ticks/s) -host_mem_usage 343896 # Number of bytes of host memory used -host_seconds 1861.54 # Real time elapsed on the host +host_inst_rate 91850 # Simulator instruction rate (inst/s) +host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55073733 # Simulator tick rate (ticks/s) +host_mem_usage 350132 # Number of bytes of host memory used +host_seconds 1437.90 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory -system.physmem.bytes_read::total 346304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5413 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory +system.physmem.bytes_read::total 345920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5405 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side +system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 299 # Per bank write bursts -system.physmem.perBankRdBursts::1 344 # Per bank write bursts +system.physmem.perBankRdBursts::1 345 # Per bank write bursts system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 354 # Per bank write bursts -system.physmem.perBankRdBursts::4 343 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 401 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts -system.physmem.perBankRdBursts::8 338 # Per bank write bursts +system.physmem.perBankRdBursts::3 350 # Per bank write bursts +system.physmem.perBankRdBursts::4 340 # Per bank write bursts +system.physmem.perBankRdBursts::5 325 # Per bank write bursts +system.physmem.perBankRdBursts::6 403 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts +system.physmem.perBankRdBursts::8 342 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 237 # Per bank write bursts -system.physmem.perBankRdBursts::11 285 # Per bank write bursts -system.physmem.perBankRdBursts::12 221 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 386 # Per bank write bursts -system.physmem.perBankRdBursts::15 284 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 217 # Per bank write bursts +system.physmem.perBankRdBursts::13 467 # Per bank write bursts +system.physmem.perBankRdBursts::14 385 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79147284500 # Total gap between requests +system.physmem.totGap 79190259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5413 # Read request sizes (log2) +system.physmem.readPktSize::6 5405 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,313 +186,313 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation -system.physmem.totQLat 39588000 # Total ticks spent queuing -system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation +system.physmem.totQLat 39419500 # Total ticks spent queuing +system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4302 # Number of row buffer hits during reads +system.physmem.readRowHits 4299 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14621704.14 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14651296.76 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.540663 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.530615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.168172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.149179 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20588400 # Number of BP lookups -system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits +system.cpu.branchPred.lookups 20589195 # Number of BP lookups +system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158294635 # number of cpu cycles simulated +system.cpu.numCycles 158380696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued -system.cpu.iq.rate 1.638335 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued +system.cpu.iq.rate 1.637565 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed -system.cpu.iew.exec_branches 14325599 # Number of branches executed -system.cpu.iew.exec_stores 22279058 # Number of stores executed -system.cpu.iew.exec_rate 1.625313 # Inst execution rate -system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204329368 # num instructions producing a value -system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value +system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed +system.cpu.iew.exec_branches 14327856 # Number of branches executed +system.cpu.iew.exec_stores 22278532 # Number of stores executed +system.cpu.iew.exec_rate 1.624539 # Inst execution rate +system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204348842 # num instructions producing a value +system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,75 +538,75 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455708112 # The number of ROB reads -system.cpu.rob.rob_writes 648756933 # The number of ROB writes -system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455802776 # The number of ROB reads +system.cpu.rob.rob_writes 648723400 # The number of ROB writes +system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads -system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448462774 # number of integer regfile reads -system.cpu.int_regfile_writes 232558570 # number of integer regfile writes -system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads -system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes -system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads -system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes -system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads +system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads +system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448507967 # number of integer regfile reads +system.cpu.int_regfile_writes 232568909 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads +system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes +system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads +system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes +system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 53 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131411014 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131411014 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45187780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45187780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513887 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65701667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65701667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65701667 # number of overall hits -system.cpu.dcache.overall_hits::total 65701667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1844 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1844 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2842 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2842 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2842 # number of overall misses -system.cpu.dcache.overall_misses::total 2842 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65947500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65947500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129226000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129226000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits +system.cpu.dcache.overall_hits::total 65736393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses +system.cpu.dcache.overall_misses::total 2848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses @@ -615,262 +615,262 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 12 # number of writebacks -system.cpu.dcache.writebacks::total 12 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 10 # number of writebacks +system.cpu.dcache.writebacks::total 10 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5044 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4970 # number of replacements +system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits -system.cpu.icache.overall_hits::total 24246303 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9495 # number of overall misses -system.cpu.icache.overall_misses::total 9495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 408233999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 408233999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 408233999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 408233999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24255798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24255798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24255798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24255798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000391 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24244955 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 305 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 299 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3877 # Transaction distribution -system.membus.trans_dist::UpgradeReq 303 # Transaction distribution -system.membus.trans_dist::UpgradeResp 303 # Transaction distribution +system.membus.trans_dist::ReadResp 3871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 296 # Transaction distribution system.membus.trans_dist::ReadExReq 1534 # Transaction distribution system.membus.trans_dist::ReadExResp 1534 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5716 # Request fanout histogram +system.membus.snoop_fanout::samples 5701 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5716 # Request fanout histogram -system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5701 # Request fanout histogram +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a85398f56..59ee1a74c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2452265 # Simulator instruction rate (inst/s) -host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524991939 # Simulator tick rate (ticks/s) -host_mem_usage 374768 # Number of bytes of host memory used -host_seconds 26.51 # Real time elapsed on the host +host_inst_rate 2397277 # Simulator instruction rate (inst/s) +host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68943602925 # Simulator tick rate (ticks/s) +host_mem_usage 377676 # Number of bytes of host memory used +host_seconds 27.11 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -737,20 +737,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.replacements 999687 # number of replacements system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. +system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy @@ -761,8 +761,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 49101323 # Number of tag accesses -system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.tags.tag_accesses 46365678 # Number of tag accesses +system.l2c.tags.data_accesses 46365678 # Number of data accesses system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits @@ -774,22 +774,22 @@ system.l2c.SCUpgradeReq_hits::total 50 # nu system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits system.l2c.overall_hits::cpu0.data 738161 # number of overall hits system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910322 # number of overall hits +system.l2c.overall_hits::total 1910319 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses @@ -799,22 +799,22 @@ system.l2c.SCUpgradeReq_misses::total 2285 # nu system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.overall_misses::total 1066180 # number of overall misses system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) @@ -851,22 +851,22 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # mi system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,49 +879,55 @@ system.l2c.writebacks::writebacks 80913 # nu system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948863 # Transaction distribution +system.membus.trans_dist::ReadResp 948866 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 922490 # Transaction distribution +system.membus.trans_dist::CleanEvict 917961 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution system.membus.trans_dist::ReadExReq 126472 # Transaction distribution system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2210194 # Request fanout histogram +system.membus.snoop_fanout::samples 2205834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -929,30 +935,30 @@ system.toL2Bus.trans_dist::ReadExReq 295246 # Tr system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram +system.toL2Bus.snoops 1083281 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 60a4f6e98..34e6d6348 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2495393 # Simulator instruction rate (inst/s) -host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76033049021 # Simulator tick rate (ticks/s) -host_mem_usage 371696 # Number of bytes of host memory used -host_seconds 24.06 # Real time elapsed on the host +host_inst_rate 2390951 # Simulator instruction rate (inst/s) +host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72850763127 # Simulator tick rate (ticks/s) +host_mem_usage 374092 # Number of bytes of host memory used +host_seconds 25.11 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,9 +338,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 992219 # number of replacements system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor @@ -356,8 +356,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits @@ -429,36 +429,42 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram +system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -561,7 +567,7 @@ system.membus.trans_dist::ReadResp 948374 # Tr system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 918371 # Transaction distribution +system.membus.trans_dist::CleanEvict 917156 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution system.membus.trans_dist::ReadExReq 116946 # Transaction distribution @@ -570,11 +576,11 @@ system.membus.trans_dist::ReadSharedReq 941190 # Tr system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) @@ -582,17 +588,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2151059 # Request fanout histogram +system.membus.snoop_fanout::samples 2150005 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2151059 # Request fanout histogram +system.membus.snoop_fanout::total 2150005 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 67605a567..69fe46592 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962608 # Number of seconds simulated -sim_ticks 1962608482500 # Number of ticks simulated -final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982585 # Number of seconds simulated +sim_ticks 1982585357000 # Number of ticks simulated +final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019388 # Simulator instruction rate (inst/s) -host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32859851956 # Simulator tick rate (ticks/s) -host_mem_usage 375280 # Number of bytes of host memory used -host_seconds 59.73 # Real time elapsed on the host -sim_insts 60884587 # Number of instructions simulated -sim_ops 60884587 # Number of ops (including micro ops) simulated +host_inst_rate 1043358 # Simulator instruction rate (inst/s) +host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33918612914 # Simulator tick rate (ticks/s) +host_mem_usage 377952 # Number of bytes of host memory used +host_seconds 58.45 # Real time elapsed on the host +sim_insts 60985541 # Number of instructions simulated +sim_ops 60985541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory -system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory +system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406729 # Number of read requests accepted -system.physmem.writeReqs 120393 # Number of write requests accepted -system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407445 # Number of read requests accepted +system.physmem.writeReqs 120910 # Number of write requests accepted +system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25025 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25447 # Per bank write bursts -system.physmem.perBankRdBursts::3 24899 # Per bank write bursts -system.physmem.perBankRdBursts::4 25181 # Per bank write bursts -system.physmem.perBankRdBursts::5 25235 # Per bank write bursts -system.physmem.perBankRdBursts::6 25799 # Per bank write bursts -system.physmem.perBankRdBursts::7 25539 # Per bank write bursts -system.physmem.perBankRdBursts::8 25681 # Per bank write bursts -system.physmem.perBankRdBursts::9 25348 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 25592 # Per bank write bursts -system.physmem.perBankRdBursts::12 25653 # Per bank write bursts -system.physmem.perBankRdBursts::13 25554 # Per bank write bursts -system.physmem.perBankRdBursts::14 25887 # Per bank write bursts -system.physmem.perBankRdBursts::15 25094 # Per bank write bursts -system.physmem.perBankWrBursts::0 7701 # Per bank write bursts -system.physmem.perBankWrBursts::1 7641 # Per bank write bursts -system.physmem.perBankWrBursts::2 7454 # Per bank write bursts -system.physmem.perBankWrBursts::3 6926 # Per bank write bursts -system.physmem.perBankWrBursts::4 7165 # Per bank write bursts -system.physmem.perBankWrBursts::5 7117 # Per bank write bursts -system.physmem.perBankWrBursts::6 7626 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7527 # Per bank write bursts -system.physmem.perBankWrBursts::9 7238 # Per bank write bursts -system.physmem.perBankWrBursts::10 7225 # Per bank write bursts -system.physmem.perBankWrBursts::11 7418 # Per bank write bursts -system.physmem.perBankWrBursts::12 7843 # Per bank write bursts -system.physmem.perBankWrBursts::13 8207 # Per bank write bursts -system.physmem.perBankWrBursts::14 8447 # Per bank write bursts -system.physmem.perBankWrBursts::15 7584 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25232 # Per bank write bursts +system.physmem.perBankRdBursts::1 25377 # Per bank write bursts +system.physmem.perBankRdBursts::2 25433 # Per bank write bursts +system.physmem.perBankRdBursts::3 24853 # Per bank write bursts +system.physmem.perBankRdBursts::4 25156 # Per bank write bursts +system.physmem.perBankRdBursts::5 25421 # Per bank write bursts +system.physmem.perBankRdBursts::6 25501 # Per bank write bursts +system.physmem.perBankRdBursts::7 25341 # Per bank write bursts +system.physmem.perBankRdBursts::8 25248 # Per bank write bursts +system.physmem.perBankRdBursts::9 25578 # Per bank write bursts +system.physmem.perBankRdBursts::10 25745 # Per bank write bursts +system.physmem.perBankRdBursts::11 25922 # Per bank write bursts +system.physmem.perBankRdBursts::12 25991 # Per bank write bursts +system.physmem.perBankRdBursts::13 25558 # Per bank write bursts +system.physmem.perBankRdBursts::14 25312 # Per bank write bursts +system.physmem.perBankRdBursts::15 25655 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts +system.physmem.perBankWrBursts::1 7774 # Per bank write bursts +system.physmem.perBankWrBursts::2 7467 # Per bank write bursts +system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::4 7102 # Per bank write bursts +system.physmem.perBankWrBursts::5 7345 # Per bank write bursts +system.physmem.perBankWrBursts::6 7434 # Per bank write bursts +system.physmem.perBankWrBursts::7 7145 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7306 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 8153 # Per bank write bursts +system.physmem.perBankWrBursts::12 8257 # Per bank write bursts +system.physmem.perBankWrBursts::13 7909 # Per bank write bursts +system.physmem.perBankWrBursts::14 7539 # Per bank write bursts +system.physmem.perBankWrBursts::15 7820 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1962561950500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 1982577992500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406729 # Read request sizes (log2) +system.physmem.readPktSize::6 407445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120393 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,181 +158,177 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads -system.physmem.totQLat 2204423500 # Total ticks spent queuing -system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads +system.physmem.totQLat 2792890500 # Total ticks spent queuing +system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 363741 # Number of row buffer hits during reads -system.physmem.writeRowHits 96228 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes -system.physmem.avgGap 3723164.56 # Average gap between requests -system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.630269 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 363877 # Number of row buffer hits during reads +system.physmem.writeRowHits 96767 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3752359.67 # Average gap between requests +system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.011108 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states +system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.683332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.118945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states +system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7500026 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5074087 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.read_accesses 490672 # DTB read accesses +system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12574113 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.write_accesses 187451 # DTB write accesses +system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3504450 # ITB hits +system.cpu0.dtb.data_accesses 678123 # DTB accesses +system.cpu0.itb.fetch_hits 3482641 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3508321 # ITB accesses +system.cpu0.itb.fetch_accesses 3486512 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -345,91 +341,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838721 # number of cpu cycles simulated +system.cpu0.numCycles 3964851833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47783493 # Number of instructions committed -system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses -system.cpu0.num_func_calls 1203861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44315744 # number of integer instructions -system.cpu0.num_fp_insts 211234 # number of float instructions -system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written -system.cpu0.num_mem_refs 12614351 # number of memory refs -system.cpu0.num_load_insts 7527207 # Number of load instructions -system.cpu0.num_store_insts 5087144 # Number of store instructions -system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles -system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles -system.cpu0.Branches 7204257 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction -system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47325532 # Number of instructions committed +system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses +system.cpu0.num_func_calls 1185742 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43895499 # number of integer instructions +system.cpu0.num_fp_insts 207106 # number of float instructions +system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written +system.cpu0.num_mem_refs 12461430 # number of memory refs +system.cpu0.num_load_insts 7443904 # Number of load instructions +system.cpu0.num_store_insts 5017526 # Number of store instructions +system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles +system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles +system.cpu0.Branches 7135463 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47792093 # Class of executed instruction +system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -461,124 +457,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150081 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.callpal::total 147613 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1281 +system.cpu0.kern.mode_good::user 1281 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3073 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1181794 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits -system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses -system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.kern.swap_context 3027 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1172695 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10944485 # 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miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks +system.cpu0.dcache.writebacks::total 672708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183219 # 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number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 700401 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 686863 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits -system.cpu0.icache.overall_hits::total 47091062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses -system.cpu0.icache.overall_misses::total 701031 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits +system.cpu0.icache.overall_hits::total 46646633 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses +system.cpu0.icache.overall_misses::total 687497 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -715,51 +711,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2409623 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1749165 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.read_accesses 239364 # DTB read accesses +system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4158788 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.write_accesses 105248 # DTB write accesses +system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1960477 # ITB hits +system.cpu1.dtb.data_accesses 344612 # DTB accesses +system.cpu1.itb.fetch_hits 1989876 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1961693 # ITB accesses +system.cpu1.itb.fetch_accesses 1991092 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925216965 # number of cpu cycles simulated +system.cpu1.numCycles 3965170714 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13101094 # Number of instructions committed -system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses -system.cpu1.num_func_calls 409417 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12083765 # number of integer instructions -system.cpu1.num_fp_insts 172106 # number of float instructions -system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written -system.cpu1.num_mem_refs 4182249 # number of memory refs -system.cpu1.num_load_insts 2423870 # Number of load instructions -system.cpu1.num_store_insts 1758379 # Number of store instructions -system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles -system.cpu1.Branches 1864071 # Number of branches fetched -system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction -system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13660009 # Number of instructions committed +system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses +system.cpu1.num_func_calls 429702 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12598388 # number of integer instructions +system.cpu1.num_fp_insts 178445 # number of float instructions +system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written +system.cpu1.num_mem_refs 4361445 # number of memory refs +system.cpu1.num_load_insts 2523214 # Number of load instructions +system.cpu1.num_store_insts 1838231 # Number of store instructions +system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles +system.cpu1.Branches 1945174 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction +system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13104456 # Class of executed instruction +system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -868,124 +864,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed -system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed +system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71137 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73942 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 911 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 447 +system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1986 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 165381 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2065 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 173710 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits -system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses -system.cpu1.dcache.overall_misses::total 179876 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits +system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses +system.cpu1.dcache.overall_misses::total 189082 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,128 +990,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks -system.cpu1.dcache.writebacks::total 113645 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks +system.cpu1.dcache.writebacks::total 119711 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 313887 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331160 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits -system.cpu1.icache.overall_hits::total 12790016 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses -system.cpu1.icache.overall_misses::total 314441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits +system.cpu1.icache.overall_hits::total 13331662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses +system.cpu1.icache.overall_misses::total 331712 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,30 +1120,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1161,45 +1157,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55595 # Transaction distribution -system.iobus.trans_dist::WriteResp 55595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55683 # Transaction distribution +system.iobus.trans_dist::WriteResp 55683 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1209,9 +1205,9 @@ system.iobus.reqLayer22.occupancy 155000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1219,52 +1215,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1273,40 +1269,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1315,195 +1311,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341250 # number of replacements -system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use -system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35905885 # Number of tag accesses -system.l2c.tags.data_accesses 35905885 # Number of data accesses -system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits -system.l2c.Writeback_hits::total 793586 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.tags.replacements 341926 # number of replacements +system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use +system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35906123 # Number of tag accesses +system.l2c.tags.data_accesses 35906123 # Number of data accesses +system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits +system.l2c.Writeback_hits::total 792419 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292720 # Transaction distribution -system.membus.trans_dist::WriteReq 14043 # Transaction distribution -system.membus.trans_dist::WriteResp 14043 # Transaction distribution -system.membus.trans_dist::Writeback 120393 # Transaction distribution -system.membus.trans_dist::CleanEvict 261901 # Transaction distribution -system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution -system.membus.trans_dist::ReadExReq 122456 # Transaction distribution -system.membus.trans_dist::ReadExResp 121630 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14131 # Transaction distribution +system.membus.trans_dist::WriteResp 14131 # Transaction distribution +system.membus.trans_dist::Writeback 120910 # Transaction distribution +system.membus.trans_dist::CleanEvict 262059 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution +system.membus.trans_dist::ReadExReq 123180 # Transaction distribution +system.membus.trans_dist::ReadExResp 122316 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21449 # Total snoops (count) -system.membus.snoop_fanout::samples 880387 # Request fanout histogram +system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22736 # Total snoops (count) +system.membus.snoop_fanout::samples 883364 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 880387 # Request fanout histogram -system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883364 # Request fanout histogram +system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 480853 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484490 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5922aa080..2decdfb20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922397 # Number of seconds simulated -sim_ticks 1922397182500 # Number of ticks simulated -final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941266 # Number of seconds simulated +sim_ticks 1941266487500 # Number of ticks simulated +final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1085217 # Simulator instruction rate (inst/s) -host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37124537063 # Simulator tick rate (ticks/s) -host_mem_usage 372212 # Number of bytes of host memory used -host_seconds 51.78 # Real time elapsed on the host -sim_insts 56195121 # Number of instructions simulated -sim_ops 56195121 # Number of ops (including micro ops) simulated +host_inst_rate 1056307 # Simulator instruction rate (inst/s) +host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36524098946 # Simulator tick rate (ticks/s) +host_mem_usage 374096 # Number of bytes of host memory used +host_seconds 53.15 # Real time elapsed on the host +sim_insts 56143021 # Number of instructions simulated +sim_ops 56143021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401684 # Number of read requests accepted -system.physmem.writeReqs 115767 # Number of write requests accepted -system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401645 # Number of read requests accepted +system.physmem.writeReqs 115743 # Number of write requests accepted +system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25233 # Per bank write bursts -system.physmem.perBankRdBursts::1 25641 # Per bank write bursts -system.physmem.perBankRdBursts::2 25574 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24973 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24501 # Per bank write bursts -system.physmem.perBankRdBursts::8 25169 # Per bank write bursts -system.physmem.perBankRdBursts::9 24770 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 24898 # Per bank write bursts -system.physmem.perBankRdBursts::12 24500 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25653 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7624 # Per bank write bursts -system.physmem.perBankWrBursts::1 7642 # Per bank write bursts -system.physmem.perBankWrBursts::2 7864 # Per bank write bursts -system.physmem.perBankWrBursts::3 7542 # Per bank write bursts -system.physmem.perBankWrBursts::4 7123 # Per bank write bursts -system.physmem.perBankWrBursts::5 6988 # Per bank write bursts -system.physmem.perBankWrBursts::6 6319 # Per bank write bursts -system.physmem.perBankWrBursts::7 6328 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 6525 # Per bank write bursts -system.physmem.perBankWrBursts::10 7109 # Per bank write bursts -system.physmem.perBankWrBursts::11 6927 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7867 # Per bank write bursts -system.physmem.perBankWrBursts::15 7675 # Per bank write bursts +system.physmem.perBankRdBursts::0 25168 # Per bank write bursts +system.physmem.perBankRdBursts::1 25510 # Per bank write bursts +system.physmem.perBankRdBursts::2 25518 # Per bank write bursts +system.physmem.perBankRdBursts::3 25527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25065 # Per bank write bursts +system.physmem.perBankRdBursts::5 24960 # Per bank write bursts +system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.perBankRdBursts::7 24604 # Per bank write bursts +system.physmem.perBankRdBursts::8 25078 # Per bank write bursts +system.physmem.perBankRdBursts::9 24653 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 24824 # Per bank write bursts +system.physmem.perBankRdBursts::12 24407 # Per bank write bursts +system.physmem.perBankRdBursts::13 25357 # Per bank write bursts +system.physmem.perBankRdBursts::14 25770 # Per bank write bursts +system.physmem.perBankRdBursts::15 25486 # Per bank write bursts +system.physmem.perBankWrBursts::0 7561 # Per bank write bursts +system.physmem.perBankWrBursts::1 7519 # Per bank write bursts +system.physmem.perBankWrBursts::2 7810 # Per bank write bursts +system.physmem.perBankWrBursts::3 7560 # Per bank write bursts +system.physmem.perBankWrBursts::4 7221 # Per bank write bursts +system.physmem.perBankWrBursts::5 6978 # Per bank write bursts +system.physmem.perBankWrBursts::6 6351 # Per bank write bursts +system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankWrBursts::8 7248 # Per bank write bursts +system.physmem.perBankWrBursts::9 6410 # Per bank write bursts +system.physmem.perBankWrBursts::10 7207 # Per bank write bursts +system.physmem.perBankWrBursts::11 6855 # Per bank write bursts +system.physmem.perBankWrBursts::12 6980 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1922385313500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1941254508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401684 # Read request sizes (log2) +system.physmem.readPktSize::6 401645 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115743 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,195 +148,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6311 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads -system.physmem.totQLat 2147063750 # Total ticks spent queuing -system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads +system.physmem.totQLat 2705942000 # Total ticks spent queuing +system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359411 # Number of row buffer hits during reads -system.physmem.writeRowHits 93558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3715106.00 # Average gap between requests -system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.604667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states -system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 358859 # Number of row buffer hits during reads +system.physmem.writeRowHits 93466 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes +system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.035450 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109115 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066440 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9058452 # DTB read hits +system.cpu.dtb.read_misses 10327 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6357400 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728858 # DTB read accesses +system.cpu.dtb.write_hits 6353129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15423840 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15411581 # DTB hits +system.cpu.dtb.data_misses 11470 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973902 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020790 # DTB accesses +system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978899 # ITB accesses +system.cpu.itb.fetch_accesses 4980143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,37 +333,37 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844794365 # number of cpu cycles simulated +system.cpu.numCycles 3882532975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195121 # Number of instructions committed -system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483708 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066883 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15476411 # number of memory refs -system.cpu.num_load_insts 9103258 # Number of load instructions -system.cpu.num_store_insts 6373153 # Number of store instructions -system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles -system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933163 # Percentage of idle cycles -system.cpu.Branches 8423975 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.committedInsts 56143021 # Number of instructions committed +system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1482534 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls +system.cpu.num_int_insts 52016582 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read +system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15464199 # number of memory refs +system.cpu.num_load_insts 9095305 # Number of load instructions +system.cpu.num_store_insts 6368894 # Number of store instructions +system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923212 # Percentage of idle cycles +system.cpu.Branches 8418668 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction @@ -402,34 +386,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206940 # Class of executed instruction +system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -465,113 +449,113 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu.kern.callpal::total 192944 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390740 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390004 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits -system.cpu.dcache.overall_hits::total 13669354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses -system.cpu.dcache.overall_misses::total 1374026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13657808 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,120 +564,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks -system.cpu.dcache.writebacks::total 835293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374026 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374026 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374026 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374026 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834533 # number of writebacks +system.cpu.dcache.writebacks::total 834533 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069028 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069028 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304257 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304257 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373285 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373285 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373285 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373285 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29660270500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091363 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40861.052751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40861.052751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56891.562068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56891.562068 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.448084 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.448084 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928306 # number of replacements -system.cpu.icache.tags.tagsinuse 508.094938 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277964 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928817 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.514376 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41861098500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.094938 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992373 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928672 # number of replacements +system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57135918 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57135918 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55277964 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277964 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277964 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277964 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277964 # number of overall hits -system.cpu.icache.overall_hits::total 55277964 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928977 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928977 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928977 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928977 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13997.161394 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13997.161394 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57084202 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57084202 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55225516 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55225516 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55225516 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55225516 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55225516 # number of overall hits +system.cpu.icache.overall_hits::total 55225516 # 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Occupied blocks per task id +system.cpu.l2cache.tags.replacements 336158 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65233.633295 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3929109 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401321 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.790440 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10607812000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 54990.166282 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4743.088898 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5500.378115 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.839083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072374 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.083929 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419768 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -979,9 +969,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51205 # Transaction distribution +system.iobus.trans_dist::WriteResp 51205 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -993,11 +983,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1009,11 +999,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1035,23 +1025,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1065,14 +1055,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1089,14 +1079,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,14 +1105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1131,59 +1121,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292339 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115767 # Transaction distribution -system.membus.trans_dist::CleanEvict 261512 # Transaction distribution +system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::WriteReq 9653 # Transaction distribution +system.membus.trans_dist::WriteResp 9653 # Transaction distribution +system.membus.trans_dist::Writeback 115743 # Transaction distribution +system.membus.trans_dist::CleanEvict 261495 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116704 # Transaction distribution -system.membus.trans_dist::ReadExResp 116704 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::ReadExReq 116679 # Transaction distribution +system.membus.trans_dist::ReadExResp 116679 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837831 # Request fanout histogram +system.membus.snoop_fanout::samples 837762 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837831 # Request fanout histogram -system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837762 # Request fanout histogram +system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 80deda855..14fab3b83 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 714694 # Simulator instruction rate (inst/s) -host_op_rate 870026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13935517761 # Simulator tick rate (ticks/s) -host_mem_usage 573808 # Number of bytes of host memory used -host_seconds 199.77 # Real time elapsed on the host +host_inst_rate 1159279 # Simulator instruction rate (inst/s) +host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22604281025 # Simulator tick rate (ticks/s) +host_mem_usage 628452 # Number of bytes of host memory used +host_seconds 123.16 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index b13c4e56a..6c9ee9f79 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,66 +4,70 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1155692 # Simulator instruction rate (inst/s) -host_op_rate 1408193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22061708570 # Simulator tick rate (ticks/s) -host_mem_usage 584036 # Number of bytes of host memory used -host_seconds 127.05 # Real time elapsed on the host +host_inst_rate 1151168 # Simulator instruction rate (inst/s) +host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21975358508 # Simulator tick rate (ticks/s) +host_mem_usage 637292 # Number of bytes of host memory used +host_seconds 127.55 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory +system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory +system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -367,8 +371,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks -system.cpu0.dcache.writebacks::total 511204 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks +system.cpu0.dcache.writebacks::total 511149 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -427,9 +431,9 @@ system.cpu0.l2cache.prefetcher.pfRemovedFull 0 system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252605 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor @@ -454,13 +458,13 @@ system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses +system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits @@ -505,8 +509,8 @@ system.cpu0.l2cache.overall_misses::total 348765 # n system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) @@ -558,15 +562,21 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks -system.cpu0.l2cache.writebacks::total 192999 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks +system.cpu0.l2cache.writebacks::total 192992 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution @@ -574,28 +584,28 @@ system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # T system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 327822 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -873,8 +883,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks -system.cpu1.dcache.writebacks::total 120813 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks +system.cpu1.dcache.writebacks::total 120812 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -932,9 +942,9 @@ system.cpu1.l2cache.prefetcher.pfRemovedFull 0 system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48465 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor @@ -957,13 +967,13 @@ system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses +system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits @@ -1008,8 +1018,8 @@ system.cpu1.l2cache.overall_misses::total 131449 # n system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) @@ -1061,15 +1071,21 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks -system.cpu1.l2cache.writebacks::total 32917 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks +system.cpu1.l2cache.writebacks::total 32915 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution @@ -1077,28 +1093,28 @@ system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # T system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 568500 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1202,109 +1218,114 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106825 # number of replacements -system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use -system.l2c.tags.total_refs 288805 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. +system.l2c.tags.replacements 106968 # number of replacements +system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use +system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5581048 # Number of tag accesses -system.l2c.tags.data_accesses 5581048 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits -system.l2c.Writeback_hits::total 225916 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits +system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5237373 # Number of tag accesses +system.l2c.tags.data_accesses 5237373 # Number of data accesses +system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits +system.l2c.Writeback_hits::total 225907 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits +system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits -system.l2c.demand_hits::total 145090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits +system.l2c.demand_hits::total 144985 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits -system.l2c.overall_hits::cpu0.data 90500 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits +system.l2c.overall_hits::cpu0.data 90498 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits -system.l2c.overall_hits::cpu1.data 14467 # number of overall hits -system.l2c.overall_hits::total 145090 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits +system.l2c.overall_hits::cpu1.data 14469 # number of overall hits +system.l2c.overall_hits::total 144985 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses -system.l2c.demand_misses::total 183538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses +system.l2c.demand_misses::total 183648 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses -system.l2c.overall_misses::cpu0.data 147794 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses -system.l2c.overall_misses::cpu1.data 16974 # number of overall misses -system.l2c.overall_misses::total 183538 # number of overall misses -system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses +system.l2c.overall_misses::cpu0.data 147797 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses +system.l2c.overall_misses::cpu1.data 16975 # number of overall misses +system.l2c.overall_misses::total 183648 # number of overall misses +system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) @@ -1317,60 +1338,63 @@ system.l2c.ReadExReq_accesses::total 169587 # nu system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses +system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1379,51 +1403,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96236 # number of writebacks -system.l2c.writebacks::total 96236 # number of writebacks +system.l2c.writebacks::writebacks 96112 # number of writebacks +system.l2c.writebacks::total 96112 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75378 # Transaction distribution +system.membus.trans_dist::ReadResp 75496 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132426 # Transaction distribution -system.membus.trans_dist::CleanEvict 15452 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution -system.membus.trans_dist::ReadExReq 196055 # Transaction distribution -system.membus.trans_dist::ReadExResp 151973 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution +system.membus.trans_dist::Writeback 132302 # Transaction distribution +system.membus.trans_dist::CleanEvict 8413 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution +system.membus.trans_dist::ReadExReq 196047 # Transaction distribution +system.membus.trans_dist::ReadExResp 151965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 587659 # Request fanout histogram +system.membus.snoop_fanout::samples 580848 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587659 # Request fanout histogram +system.membus.snoop_fanout::total 580848 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1455,45 +1479,51 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180140 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 33ede6cdf..8e10ef807 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1188421 # Simulator instruction rate (inst/s) -host_op_rate 1446712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23172506899 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 120.14 # Real time elapsed on the host +host_inst_rate 1171566 # Simulator instruction rate (inst/s) +host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22843865684 # Simulator tick rate (ticks/s) +host_mem_usage 624228 # Number of bytes of host memory used +host_seconds 121.87 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 2deca7899..719058a40 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868749 # Number of seconds simulated -sim_ticks 2868748596000 # Number of ticks simulated -final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871120 # Number of seconds simulated +sim_ticks 2871119862000 # Number of ticks simulated +final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 740337 # Simulator instruction rate (inst/s) -host_op_rate 895502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16150564794 # Simulator tick rate (ticks/s) -host_mem_usage 599396 # Number of bytes of host memory used -host_seconds 177.63 # Real time elapsed on the host -sim_insts 131502488 # Number of instructions simulated -sim_ops 159063828 # Number of ops (including micro ops) simulated +host_inst_rate 654504 # Simulator instruction rate (inst/s) +host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14285860596 # Simulator tick rate (ticks/s) +host_mem_usage 653456 # Number of bytes of host memory used +host_seconds 200.98 # Real time elapsed on the host +sim_insts 131539806 # Number of instructions simulated +sim_ops 159111212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory +system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory +system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198852 # Number of read requests accepted -system.physmem.writeReqs 140577 # Number of write requests accepted -system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 196438 # Number of read requests accepted +system.physmem.writeReqs 139355 # Number of write requests accepted +system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12039 # Per bank write bursts -system.physmem.perBankRdBursts::1 11932 # Per bank write bursts -system.physmem.perBankRdBursts::2 12219 # Per bank write bursts -system.physmem.perBankRdBursts::3 12193 # Per bank write bursts -system.physmem.perBankRdBursts::4 20606 # Per bank write bursts -system.physmem.perBankRdBursts::5 12429 # Per bank write bursts -system.physmem.perBankRdBursts::6 12151 # Per bank write bursts -system.physmem.perBankRdBursts::7 12313 # Per bank write bursts -system.physmem.perBankRdBursts::8 12521 # Per bank write bursts -system.physmem.perBankRdBursts::9 12643 # Per bank write bursts -system.physmem.perBankRdBursts::10 11981 # Per bank write bursts -system.physmem.perBankRdBursts::11 11107 # Per bank write bursts -system.physmem.perBankRdBursts::12 11212 # Per bank write bursts -system.physmem.perBankRdBursts::13 11639 # Per bank write bursts -system.physmem.perBankRdBursts::14 10708 # Per bank write bursts -system.physmem.perBankRdBursts::15 11019 # Per bank write bursts -system.physmem.perBankWrBursts::0 8788 # Per bank write bursts -system.physmem.perBankWrBursts::1 8813 # Per bank write bursts -system.physmem.perBankWrBursts::2 9145 # Per bank write bursts -system.physmem.perBankWrBursts::3 8891 # Per bank write bursts -system.physmem.perBankWrBursts::4 8356 # Per bank write bursts -system.physmem.perBankWrBursts::5 8969 # Per bank write bursts -system.physmem.perBankWrBursts::6 8864 # Per bank write bursts -system.physmem.perBankWrBursts::7 8722 # Per bank write bursts -system.physmem.perBankWrBursts::8 9036 # Per bank write bursts -system.physmem.perBankWrBursts::9 9148 # Per bank write bursts -system.physmem.perBankWrBursts::10 8611 # Per bank write bursts -system.physmem.perBankWrBursts::11 8177 # Per bank write bursts -system.physmem.perBankWrBursts::12 8063 # Per bank write bursts -system.physmem.perBankWrBursts::13 7981 # Per bank write bursts -system.physmem.perBankWrBursts::14 7509 # Per bank write bursts -system.physmem.perBankWrBursts::15 7576 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11406 # Per bank write bursts +system.physmem.perBankRdBursts::1 11655 # Per bank write bursts +system.physmem.perBankRdBursts::2 11752 # Per bank write bursts +system.physmem.perBankRdBursts::3 11575 # Per bank write bursts +system.physmem.perBankRdBursts::4 20585 # Per bank write bursts +system.physmem.perBankRdBursts::5 12467 # Per bank write bursts +system.physmem.perBankRdBursts::6 12095 # Per bank write bursts +system.physmem.perBankRdBursts::7 12222 # Per bank write bursts +system.physmem.perBankRdBursts::8 12044 # Per bank write bursts +system.physmem.perBankRdBursts::9 12120 # Per bank write bursts +system.physmem.perBankRdBursts::10 11627 # Per bank write bursts +system.physmem.perBankRdBursts::11 11103 # Per bank write bursts +system.physmem.perBankRdBursts::12 11588 # Per bank write bursts +system.physmem.perBankRdBursts::13 11719 # Per bank write bursts +system.physmem.perBankRdBursts::14 10853 # Per bank write bursts +system.physmem.perBankRdBursts::15 11470 # Per bank write bursts +system.physmem.perBankWrBursts::0 8250 # Per bank write bursts +system.physmem.perBankWrBursts::1 8603 # Per bank write bursts +system.physmem.perBankWrBursts::2 8782 # Per bank write bursts +system.physmem.perBankWrBursts::3 8359 # Per bank write bursts +system.physmem.perBankWrBursts::4 8401 # Per bank write bursts +system.physmem.perBankWrBursts::5 9093 # Per bank write bursts +system.physmem.perBankWrBursts::6 8866 # Per bank write bursts +system.physmem.perBankWrBursts::7 8828 # Per bank write bursts +system.physmem.perBankWrBursts::8 8708 # Per bank write bursts +system.physmem.perBankWrBursts::9 8716 # Per bank write bursts +system.physmem.perBankWrBursts::10 8411 # Per bank write bursts +system.physmem.perBankWrBursts::11 8212 # Per bank write bursts +system.physmem.perBankWrBursts::12 8400 # Per bank write bursts +system.physmem.perBankWrBursts::13 8108 # Per bank write bursts +system.physmem.perBankWrBursts::14 7766 # Per bank write bursts +system.physmem.perBankWrBursts::15 7939 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 39 # Number of times write queue was full causing retry -system.physmem.totGap 2868748135500 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 2871119474000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189093 # Read request sizes (log2) +system.physmem.readPktSize::6 186679 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136186 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 134964 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -180,158 +180,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads -system.physmem.totQLat 4722732900 # Total ticks spent queuing -system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads +system.physmem.totQLat 4505900396 # Total ticks spent queuing +system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing -system.physmem.readRowHits 166188 # Number of row buffer hits during reads -system.physmem.writeRowHits 81139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes -system.physmem.avgGap 8451688.38 # Average gap between requests -system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.555658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states -system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 163849 # Number of row buffer hits during reads +system.physmem.writeRowHits 80221 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes +system.physmem.avgGap 8550266.01 # Average gap between requests +system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.601510 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states +system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466501 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states -system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.513716 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states +system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -387,57 +390,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7824 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 5019 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25236580 # DTB read hits -system.cpu0.dtb.read_misses 6707 # DTB read misses -system.cpu0.dtb.write_hits 18793560 # DTB write hits -system.cpu0.dtb.write_misses 1117 # DTB write misses +system.cpu0.dtb.read_hits 23515104 # DTB read hits +system.cpu0.dtb.read_misses 4346 # DTB read misses +system.cpu0.dtb.write_hits 17278792 # DTB write hits +system.cpu0.dtb.write_misses 673 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25243287 # DTB read accesses -system.cpu0.dtb.write_accesses 18794677 # DTB write accesses +system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23519450 # DTB read accesses +system.cpu0.dtb.write_accesses 17279465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44030140 # DTB hits -system.cpu0.dtb.misses 7824 # DTB misses -system.cpu0.dtb.accesses 44037964 # DTB accesses +system.cpu0.dtb.hits 40793896 # DTB hits +system.cpu0.dtb.misses 5019 # DTB misses +system.cpu0.dtb.accesses 40798915 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,40 +469,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3348 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2305 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119342617 # ITB inst hits -system.cpu0.itb.inst_misses 3348 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 111711640 # ITB inst hits +system.cpu0.itb.inst_misses 2305 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,179 +509,178 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses -system.cpu0.itb.hits 119342617 # DTB hits -system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 119345965 # DTB accesses -system.cpu0.numCycles 5737497192 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses +system.cpu0.itb.hits 111711640 # DTB hits +system.cpu0.itb.misses 2305 # DTB misses +system.cpu0.itb.accesses 111713945 # DTB accesses +system.cpu0.numCycles 5741309822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 115654281 # Number of instructions committed -system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12768418 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123734710 # number of integer instructions -system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written -system.cpu0.num_mem_refs 45168124 # number of memory refs -system.cpu0.num_load_insts 25488908 # Number of load instructions -system.cpu0.num_store_insts 19679216 # Number of store instructions -system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles -system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles -system.cpu0.Branches 29223626 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction -system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 108455216 # Number of instructions committed +system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses +system.cpu0.num_func_calls 12371356 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls +system.cpu0.num_int_insts 115934267 # number of integer instructions +system.cpu0.num_fp_insts 4495 # number of float instructions +system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read +system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written +system.cpu0.num_mem_refs 41877995 # number of memory refs +system.cpu0.num_load_insts 23749275 # Number of load instructions +system.cpu0.num_store_insts 18128720 # Number of store instructions +system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles +system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles +system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles +system.cpu0.Branches 27818534 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction +system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143560148 # Class of executed instruction +system.cpu0.op_class::total 134599461 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 696532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18061887 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318120 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318120 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365603 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365603 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362648 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362648 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42033935 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42033935 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42352055 # number of overall hits -system.cpu0.dcache.overall_hits::total 42352055 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398676 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 398676 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324664 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324664 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21706 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21706 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19707 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19707 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 723340 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 723340 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 851983 # number of overall misses -system.cpu0.dcache.overall_misses::total 851983 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # 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Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 300494 # 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average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14142.749606 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14142.749606 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12007.301202 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12007.301202 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16820.653674 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16820.653674 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -690,147 +689,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 508357 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6198 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19364 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19364 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 604987 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 604987 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 691818 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 691818 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31738 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28393 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60131 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4148741500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4148741500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5419061500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5419061500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1553984000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1553984000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101488000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101488000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434796500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 434796500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1527000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1527000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9567803000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9567803000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11121787000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11121787000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6274722500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # 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average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1105972 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 987035 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # 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miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009272 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009272 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009272 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009272 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9885.312876 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9885.312876 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9885.312876 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9885.312876 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,448 +840,451 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106493 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1106493 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106493 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1106493 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106493 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1106493 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 987556 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 987556 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 987556 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 987556 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 987556 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 987556 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009272 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009272 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009272 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9385.312876 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008840 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.008840 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.008840 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 269395 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 245604 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7689 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3966 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066956 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922485 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60150726 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60150726 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7925 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3539 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11464 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 508356 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 508356 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28387 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28387 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1736 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1736 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 229125 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 229125 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1058458 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1058458 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 386565 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 386565 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7925 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3539 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1058458 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 615690 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1685612 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7925 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3539 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1058458 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 615690 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1685612 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 220 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25774 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 25774 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17960 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17960 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41378 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 41378 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 48035 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 48035 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94511 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94511 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 220 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 48035 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2775342500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2775342500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5406500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2600000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385304000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4779688500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7172999000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5406500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2600000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385304000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4779688500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7172999000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8145 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3653 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11798 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 508356 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 508356 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54161 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54161 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19696 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19696 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270503 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 270503 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1106493 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1106493 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 481076 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 481076 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8145 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3653 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1106493 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 751579 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1869870 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8145 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3653 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1106493 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 751579 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1869870 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031207 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.028310 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.475877 # 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mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.475877 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911860 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911860 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.474752 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.474752 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921289 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.921289 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148708 # 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mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158123 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158123 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041613 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222954 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.222954 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1311,60 +1315,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3357 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6206 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3844486 # DTB read hits -system.cpu1.dtb.read_misses 2847 # DTB read misses -system.cpu1.dtb.write_hits 3369243 # DTB write hits -system.cpu1.dtb.write_misses 510 # DTB write misses +system.cpu1.dtb.read_hits 5575996 # DTB read hits +system.cpu1.dtb.read_misses 5233 # DTB read misses +system.cpu1.dtb.write_hits 4889133 # DTB write hits +system.cpu1.dtb.write_misses 973 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3847333 # DTB read accesses -system.cpu1.dtb.write_accesses 3369753 # DTB write accesses +system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5581229 # DTB read accesses +system.cpu1.dtb.write_accesses 4890106 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7213729 # DTB hits -system.cpu1.dtb.misses 3357 # DTB misses -system.cpu1.dtb.accesses 7217086 # DTB accesses +system.cpu1.dtb.hits 10465129 # DTB hits +system.cpu1.dtb.misses 6206 # DTB misses +system.cpu1.dtb.accesses 10471335 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1394,43 +1402,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2787 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16180944 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 23850368 # ITB inst hits +system.cpu1.itb.inst_misses 2787 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1439,178 +1450,179 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses -system.cpu1.itb.hits 16180944 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16182690 # DTB accesses -system.cpu1.numCycles 5736568944 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses +system.cpu1.itb.hits 23850368 # DTB hits +system.cpu1.itb.misses 2787 # DTB misses +system.cpu1.itb.accesses 23853155 # DTB accesses +system.cpu1.numCycles 5742239724 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15848207 # Number of instructions committed -system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 938177 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17383760 # number of integer instructions -system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written -system.cpu1.num_mem_refs 7446495 # number of memory refs -system.cpu1.num_load_insts 3955836 # Number of load instructions -system.cpu1.num_store_insts 3490659 # Number of store instructions -system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles -system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles -system.cpu1.Branches 2803460 # Number of branches fetched -system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction -system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction -system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction +system.cpu1.committedInsts 23084590 # Number of instructions committed +system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses +system.cpu1.num_func_calls 1341368 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25227117 # number of integer instructions +system.cpu1.num_fp_insts 6988 # number of float instructions +system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written +system.cpu1.num_mem_refs 10752307 # number of memory refs +system.cpu1.num_load_insts 5706058 # Number of load instructions +system.cpu1.num_store_insts 5046249 # Number of store instructions +system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles +system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles +system.cpu1.Branches 4219564 # Number of branches fetched +system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction +system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 19620755 # Class of executed instruction +system.cpu1.op_class::total 28630613 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 186869 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits -system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses -system.cpu1.dcache.overall_misses::total 255272 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 292035 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits +system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses +system.cpu1.dcache.overall_misses::total 361088 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1619,147 +1631,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116740 # number of writebacks -system.cpu1.dcache.writebacks::total 116740 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 267 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 267 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 267 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks +system.cpu1.dcache.writebacks::total 180790 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 501529 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 622414 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits -system.cpu1.icache.overall_hits::total 15678898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses -system.cpu1.icache.overall_misses::total 502041 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4374235500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4374235500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16180939 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16180939 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16180939 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16180939 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031027 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031027 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031027 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031027 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8712.904922 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8712.904922 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8712.904922 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits +system.cpu1.icache.overall_hits::total 23227437 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 622926 # 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number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1768,237 +1780,240 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 502041 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 502041 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 502041 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 502041 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 61752 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 45885 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14962.501141 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1260771 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 60629 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.794851 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 65711 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.992983 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.872865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.082863 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2870.067957 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2148.313714 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 992.170760 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.546020 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # 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average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # 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average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59423 # Transaction distribution -system.iobus.trans_dist::WriteResp 59423 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31011 # Transaction distribution +system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2232,11 +2253,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2257,11 +2278,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2301,52 +2322,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use +system.iocache.tags.replacements 36460 # number of replacements +system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328302 # Number of tag accesses +system.iocache.tags.data_accesses 328302 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses +system.iocache.ReadReq_misses::total 254 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses +system.iocache.demand_misses::total 254 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 254 # number of overall misses +system.iocache.overall_misses::total 254 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2355,40 +2376,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19907877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19907877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19907877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 254 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 254 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 254 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 254 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20310877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20310877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906590097 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2906590097 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20310877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20310877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20310877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20310877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2397,289 +2418,289 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78070.105882 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78070.105882 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68085.697742 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68085.697742 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130014 # number of replacements -system.l2c.tags.tagsinuse 63961.093315 # Cycle average of tags in use -system.l2c.tags.total_refs 392369 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 194378 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.018587 # Average number of references to valid blocks. +system.l2c.tags.replacements 127982 # number of replacements +system.l2c.tags.tagsinuse 63841.400540 # Cycle average of tags in use +system.l2c.tags.total_refs 386797 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 192628 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.008000 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12058.686901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.020417 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045313 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7839.345721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2905.478880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 950.717991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 465.629828 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2237.479906 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1406.932882 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 489.801266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2179.617757 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.183960 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.119619 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044334 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.014507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975969 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32308 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974142 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31928 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32052 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4677 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27406 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32714 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 74 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27529 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5325589 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 30090 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 45920 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45888 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 41 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11628 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 8389 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5369 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 147495 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 55 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 30090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49835 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45888 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11628 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5369 # number of demand (read+write) hits -system.l2c.demand_hits::total 152830 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 55 # number of overall hits -system.l2c.overall_hits::cpu0.inst 30090 # number of overall hits -system.l2c.overall_hits::cpu0.data 49835 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45888 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 41 # 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number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5585 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 55 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 33 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 23888 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 41259 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 41598 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 52 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 64 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 16804 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11932 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 9486 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 145171 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 55 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808854 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758929 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.877509 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.844389 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.754840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.803361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774644 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078610 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44038 # Transaction distribution -system.membus.trans_dist::ReadResp 214387 # Transaction distribution -system.membus.trans_dist::WriteReq 30874 # Transaction distribution -system.membus.trans_dist::WriteResp 30874 # Transaction distribution -system.membus.trans_dist::Writeback 136186 # Transaction distribution -system.membus.trans_dist::CleanEvict 15507 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 39841 # Transaction distribution -system.membus.trans_dist::ReadExResp 19332 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution +system.membus.trans_dist::ReadReq 44076 # Transaction distribution +system.membus.trans_dist::ReadResp 212234 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::Writeback 134964 # Transaction distribution +system.membus.trans_dist::CleanEvict 15319 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution +system.membus.trans_dist::ReadExReq 39815 # Transaction distribution +system.membus.trans_dist::ReadExResp 19093 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123030 # Total snoops (count) -system.membus.snoop_fanout::samples 587901 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123434 # Total snoops (count) +system.membus.snoop_fanout::samples 584834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587901 # Request fanout histogram -system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 584834 # Request fanout histogram +system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2973,56 +2993,62 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449881 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 449108 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 2f0ebe667..79e3a7b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903468 # Number of seconds simulated -sim_ticks 2903467553500 # Number of ticks simulated -final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909343 # Number of seconds simulated +sim_ticks 2909343316500 # Number of ticks simulated +final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 455888 # Simulator instruction rate (inst/s) -host_op_rate 549660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11767164312 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 246.74 # Real time elapsed on the host -sim_insts 112487279 # Number of instructions simulated -sim_ops 135624752 # Number of ops (including micro ops) simulated +host_inst_rate 666869 # Simulator instruction rate (inst/s) +host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17251437084 # Simulator tick rate (ticks/s) +host_mem_usage 624248 # Number of bytes of host memory used +host_seconds 168.64 # Real time elapsed on the host +sim_insts 112463069 # Number of instructions simulated +sim_ops 135595282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168877 # Number of read requests accepted -system.physmem.writeReqs 123875 # Number of write requests accepted -system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166592 # Number of read requests accepted +system.physmem.writeReqs 121840 # Number of write requests accepted +system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10018 # Per bank write bursts -system.physmem.perBankRdBursts::1 9658 # Per bank write bursts -system.physmem.perBankRdBursts::2 10300 # Per bank write bursts -system.physmem.perBankRdBursts::3 9945 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10302 # Per bank write bursts -system.physmem.perBankRdBursts::7 10601 # Per bank write bursts -system.physmem.perBankRdBursts::8 9921 # Per bank write bursts -system.physmem.perBankRdBursts::9 10207 # Per bank write bursts -system.physmem.perBankRdBursts::10 9962 # Per bank write bursts -system.physmem.perBankRdBursts::11 9026 # Per bank write bursts -system.physmem.perBankRdBursts::12 9868 # Per bank write bursts -system.physmem.perBankRdBursts::13 10473 # Per bank write bursts -system.physmem.perBankRdBursts::14 9981 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7412 # Per bank write bursts -system.physmem.perBankWrBursts::1 7255 # Per bank write bursts -system.physmem.perBankWrBursts::2 8123 # Per bank write bursts -system.physmem.perBankWrBursts::3 7537 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7577 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7853 # Per bank write bursts -system.physmem.perBankWrBursts::10 7551 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7397 # Per bank write bursts -system.physmem.perBankWrBursts::13 7831 # Per bank write bursts -system.physmem.perBankWrBursts::14 7359 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10226 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10496 # Per bank write bursts +system.physmem.perBankRdBursts::4 18505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10179 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9478 # Per bank write bursts +system.physmem.perBankRdBursts::9 10041 # Per bank write bursts +system.physmem.perBankRdBursts::10 9320 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9424 # Per bank write bursts +system.physmem.perBankRdBursts::13 10229 # Per bank write bursts +system.physmem.perBankRdBursts::14 9340 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7577 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8049 # Per bank write bursts +system.physmem.perBankWrBursts::4 7151 # Per bank write bursts +system.physmem.perBankWrBursts::5 7579 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::12 7200 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6925 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2903467231500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909342872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159305 # Read request sizes (log2) +system.physmem.readPktSize::6 157020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119494 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # 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What write queue length does an incoming req see system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads -system.physmem.totQLat 1515248250 # Total ticks spent queuing -system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads +system.physmem.totQLat 1636363750 # Total ticks spent queuing +system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing -system.physmem.readRowHits 138696 # Number of row buffer hits during reads -system.physmem.writeRowHits 90730 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes -system.physmem.avgGap 9917839.10 # Average gap between requests -system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.494214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states -system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing +system.physmem.readRowHits 136200 # Number of row buffer hits during reads +system.physmem.writeRowHits 89619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes +system.physmem.avgGap 10086754.84 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.621597 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.405084 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478544 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -361,56 +354,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9548 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9555 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24527083 # DTB read hits -system.cpu.dtb.read_misses 8134 # DTB read misses -system.cpu.dtb.write_hits 19611642 # DTB write hits -system.cpu.dtb.write_misses 1414 # DTB write misses +system.cpu.dtb.read_hits 24521784 # DTB read hits +system.cpu.dtb.read_misses 8135 # DTB read misses +system.cpu.dtb.write_hits 19607400 # DTB write hits +system.cpu.dtb.write_misses 1420 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24535217 # DTB read accesses -system.cpu.dtb.write_accesses 19613056 # DTB write accesses +system.cpu.dtb.read_accesses 24529919 # DTB read accesses +system.cpu.dtb.write_accesses 19608820 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44138725 # DTB hits -system.cpu.dtb.misses 9548 # DTB misses -system.cpu.dtb.accesses 44148273 # DTB accesses +system.cpu.dtb.hits 44129184 # DTB hits +system.cpu.dtb.misses 9555 # DTB misses +system.cpu.dtb.accesses 44138739 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,38 +432,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115585268 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,38 +477,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115590030 # ITB inst accesses -system.cpu.itb.hits 115585268 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115590030 # DTB accesses -system.cpu.numCycles 5806935107 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 115565407 # ITB inst accesses +system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115565407 # DTB accesses +system.cpu.numCycles 5818686633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112487279 # Number of instructions committed -system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses +system.cpu.committedInsts 112463069 # Number of instructions committed +system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9895067 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls -system.cpu.num_int_insts 119926396 # number of integer instructions +system.cpu.num_func_calls 9893453 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls +system.cpu.num_int_insts 119900050 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read -system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written +system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read +system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written -system.cpu.num_mem_refs 45420046 # number of memory refs -system.cpu.num_load_insts 24850080 # Number of load instructions -system.cpu.num_store_insts 20569966 # Number of store instructions -system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles -system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles -system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927415 # Percentage of idle cycles -system.cpu.Branches 25923230 # Number of branches fetched +system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written +system.cpu.num_mem_refs 45409486 # number of memory refs +system.cpu.num_load_insts 24844046 # Number of load instructions +system.cpu.num_store_insts 20565440 # Number of store instructions +system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles +system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924573 # Percentage of idle cycles +system.cpu.Branches 25918657 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,110 +536,110 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138745790 # Class of executed instruction +system.cpu.op_class::total 138715716 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 820821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 821347 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits -system.cpu.dcache.overall_hits::total 42339568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118314 # 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number of cycles access was blocked @@ -658,144 +648,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682374 # number of writebacks -system.cpu.dcache.writebacks::total 682374 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14211 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14211 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # 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mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24885644000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24885644000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26503143500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26503143500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5936758500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5936758500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4791465500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4791465500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10728224000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10728224000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016397 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016397 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018897 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018897 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13867.215701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13867.215701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41098.111161 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41098.111161 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13154.531148 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23738.923670 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189708.897951 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189708.897951 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165709.665145 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165709.665145 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178434.128984 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178434.128984 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # 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number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699351 # number of overall misses -system.cpu.icache.overall_misses::total 1699351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23351891000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23351891000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23351891000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23351891000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23351891000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23351891000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115585268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115585268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115585268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115585268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115585268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115585268 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.652549 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21652540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21652540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21652540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21652540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # 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average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16590689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18770822000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5547532500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6577298500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4474192000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4474192000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10021724500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11051490500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000762 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991301 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063749 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 179423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175948 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1211,9 +1207,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1236,9 +1232,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1279,52 +1275,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1333,14 +1329,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1351,22 +1347,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1375,68 +1371,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 40164 # Transaction distribution -system.membus.trans_dist::ReadResp 70750 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 119494 # Transaction distribution -system.membus.trans_dist::CleanEvict 6493 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 117459 # Transaction distribution +system.membus.trans_dist::CleanEvict 6342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129215 # Transaction distribution -system.membus.trans_dist::ReadExResp 129215 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 127038 # Transaction distribution +system.membus.trans_dist::ReadExResp 127038 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394512 # Request fanout histogram +system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 390004 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394512 # Request fanout histogram -system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390004 # Request fanout histogram +system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1469,13 +1465,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 86f263873..83f940052 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1097147 # Simulator instruction rate (inst/s) -host_op_rate 1335600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21392785088 # Simulator tick rate (ticks/s) -host_mem_usage 571732 # Number of bytes of host memory used -host_seconds 130.13 # Real time elapsed on the host +host_inst_rate 1174884 # Simulator instruction rate (inst/s) +host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22908545755 # Simulator tick rate (ticks/s) +host_mem_usage 623708 # Number of bytes of host memory used +host_seconds 121.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -763,9 +763,9 @@ system.iocache.writebacks::total 36190 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.l2c.tags.total_refs 4567770 # Total number of references to valid blocks. +system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.073532 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor @@ -794,8 +794,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40922425 # Number of tag accesses -system.l2c.tags.data_accesses 40922425 # Number of data accesses +system.l2c.tags.tag_accesses 40608233 # Number of tag accesses +system.l2c.tags.data_accesses 40608233 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits @@ -956,7 +956,7 @@ system.membus.trans_dist::ReadResp 74196 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -970,9 +970,9 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -1024,22 +1024,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1836352 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1047,27 +1053,27 @@ system.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7761036 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5176290 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013064 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113547 # Request fanout histogram +system.toL2Bus.snoops 182968 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5108669 98.69% 98.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 67621 1.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5176290 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cda6fdde5..a4264e923 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903518 # Number of seconds simulated -sim_ticks 2903517798500 # Number of ticks simulated -final_tick 2903517798500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909388 # Number of seconds simulated +sim_ticks 2909387991500 # Number of ticks simulated +final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 703123 # Simulator instruction rate (inst/s) -host_op_rate 847748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18151522616 # Simulator tick rate (ticks/s) -host_mem_usage 572756 # Number of bytes of host memory used -host_seconds 159.96 # Real time elapsed on the host -sim_insts 112471533 # Number of instructions simulated -sim_ops 135605825 # Number of ops (including micro ops) simulated +host_inst_rate 670421 # Simulator instruction rate (inst/s) +host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17345176485 # Simulator tick rate (ticks/s) +host_mem_usage 625252 # Number of bytes of host memory used +host_seconds 167.73 # Real time elapsed on the host +sim_insts 112452815 # Number of instructions simulated +sim_ops 135583410 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 588836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3938784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 600704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5102020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10231944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 588836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 600704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189540 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7646016 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7663540 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17654 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 62062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 79720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168847 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119469 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123850 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 202801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1356556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 206888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1757186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3523982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 202801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 206888 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409689 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 202801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1362589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 206888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1757188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6163380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168847 # Number of read requests accepted -system.physmem.writeReqs 123850 # Number of write requests accepted -system.physmem.readBursts 168847 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123850 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10798016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10231944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7663540 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166585 # Number of read requests accepted +system.physmem.writeReqs 121838 # Number of write requests accepted +system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10014 # Per bank write bursts -system.physmem.perBankRdBursts::1 9659 # Per bank write bursts -system.physmem.perBankRdBursts::2 10299 # Per bank write bursts -system.physmem.perBankRdBursts::3 9948 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10301 # Per bank write bursts -system.physmem.perBankRdBursts::7 10599 # Per bank write bursts -system.physmem.perBankRdBursts::8 9915 # Per bank write bursts -system.physmem.perBankRdBursts::9 10209 # Per bank write bursts -system.physmem.perBankRdBursts::10 9947 # Per bank write bursts -system.physmem.perBankRdBursts::11 9027 # Per bank write bursts -system.physmem.perBankRdBursts::12 9869 # Per bank write bursts -system.physmem.perBankRdBursts::13 10471 # Per bank write bursts -system.physmem.perBankRdBursts::14 9980 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7419 # Per bank write bursts -system.physmem.perBankWrBursts::1 7262 # Per bank write bursts -system.physmem.perBankWrBursts::2 8122 # Per bank write bursts -system.physmem.perBankWrBursts::3 7539 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7576 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7846 # Per bank write bursts -system.physmem.perBankWrBursts::10 7540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7394 # Per bank write bursts -system.physmem.perBankWrBursts::13 7835 # Per bank write bursts -system.physmem.perBankWrBursts::14 7358 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10228 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10495 # Per bank write bursts +system.physmem.perBankRdBursts::4 18506 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10178 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9477 # Per bank write bursts +system.physmem.perBankRdBursts::9 10047 # Per bank write bursts +system.physmem.perBankRdBursts::10 9317 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9423 # Per bank write bursts +system.physmem.perBankRdBursts::13 10228 # Per bank write bursts +system.physmem.perBankRdBursts::14 9339 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7595 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8047 # Per bank write bursts +system.physmem.perBankWrBursts::4 7152 # Per bank write bursts +system.physmem.perBankWrBursts::5 7580 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6806 # Per bank write bursts +system.physmem.perBankWrBursts::11 7096 # Per bank write bursts +system.physmem.perBankWrBursts::12 7204 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6924 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2903517476500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909387547000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159275 # Read request sizes (log2) +system.physmem.readPktSize::6 157013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,178 +161,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8053 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.674753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.487125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.482596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21806 36.79% 36.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14989 25.29% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5586 9.42% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 5.51% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2330 3.93% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1628 2.75% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1108 1.87% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.79% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7500 12.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59278 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.683781 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 547.352228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5880 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5882 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.394594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.624984 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.894436 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.14% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.12% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.17% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4921 83.66% 84.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 66 1.12% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 241 4.10% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 88 1.50% 91.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 1.31% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 178 3.03% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.22% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 174 2.96% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 1493162250 # Total ticks spent queuing -system.physmem.totMemAccLat 4656643500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8849.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads +system.physmem.totQLat 1603192250 # Total ticks spent queuing +system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27599.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.20 # Average write queue length when enqueuing -system.physmem.readRowHits 138806 # Number of row buffer hits during reads -system.physmem.writeRowHits 90595 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 9919874.40 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229302360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125115375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700237200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392208480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87298782345 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665531858750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943921054190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.505834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770598960250 # Time in different power states -system.physmem_0.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing +system.physmem.readRowHits 136293 # Number of row buffer hits during reads +system.physmem.writeRowHits 89580 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes +system.physmem.avgGap 10087224.48 # Average gap between requests +system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.628037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states +system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35962503500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615763200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385138800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86123693430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666562638500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943669029305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.419034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772326743250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.490585 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states +system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34236177250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -382,60 +379,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6827 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6827 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2216 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walks 6929 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6703.217150 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4631 80.04% 80.04% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1152 19.91% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.765375 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 925400000 -76.54% -76.54% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -2134480312 176.54% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3595 62.14% 62.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2190 37.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5785 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6827 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6827 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5785 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12612 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12507441 # DTB read hits -system.cpu0.dtb.read_misses 5917 # DTB read misses -system.cpu0.dtb.write_hits 9856816 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12044488 # DTB read hits +system.cpu0.dtb.read_misses 5975 # DTB read misses +system.cpu0.dtb.write_hits 9654865 # DTB write hits +system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4603 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12513358 # DTB read accesses -system.cpu0.dtb.write_accesses 9857726 # DTB write accesses +system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12050463 # DTB read accesses +system.cpu0.dtb.write_accesses 9655819 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22364257 # DTB hits -system.cpu0.dtb.misses 6827 # DTB misses -system.cpu0.dtb.accesses 22371084 # DTB accesses +system.cpu0.dtb.hits 21699353 # DTB hits +system.cpu0.dtb.misses 6929 # DTB misses +system.cpu0.dtb.accesses 21706282 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,254 +460,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3521 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3521 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 830 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2691 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3521 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6917.920498 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 769 28.80% 28.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1283 48.05% 76.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 616 23.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1840 68.91% 68.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 830 31.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2670 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3426 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6191 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58595537 # ITB inst hits -system.cpu0.itb.inst_misses 3521 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56823446 # ITB inst hits +system.cpu0.itb.inst_misses 3426 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2691 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58599058 # ITB inst accesses -system.cpu0.itb.hits 58595537 # DTB hits -system.cpu0.itb.misses 3521 # DTB misses -system.cpu0.itb.accesses 58599058 # DTB accesses -system.cpu0.numCycles 2904052506 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses +system.cpu0.itb.hits 56823446 # DTB hits +system.cpu0.itb.misses 3426 # DTB misses +system.cpu0.itb.accesses 56826872 # DTB accesses +system.cpu0.numCycles 2910048510 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57017963 # Number of instructions committed -system.cpu0.committedOps 68702056 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60736686 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5415 # Number of float alu accesses -system.cpu0.num_func_calls 5101109 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7710665 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60736686 # number of integer instructions -system.cpu0.num_fp_insts 5415 # number of float instructions -system.cpu0.num_int_register_reads 110496547 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42022968 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4193 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 248490103 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26091255 # number of times the CC registers were written -system.cpu0.num_mem_refs 23020484 # number of memory refs -system.cpu0.num_load_insts 12672781 # Number of load instructions -system.cpu0.num_store_insts 10347703 # Number of store instructions -system.cpu0.num_idle_cycles 2689228469.175671 # Number of idle cycles -system.cpu0.num_busy_cycles 214824036.824329 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926026 # Percentage of idle cycles -system.cpu0.Branches 13203328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2205 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47217639 67.16% 67.16% # Class of executed instruction -system.cpu0.op_class::IntMult 59885 0.09% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4420 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 12672781 18.03% 85.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 10347703 14.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55288600 # Number of instructions committed +system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses +system.cpu0.num_func_calls 4809440 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58931600 # number of integer instructions +system.cpu0.num_fp_insts 5354 # number of float instructions +system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written +system.cpu0.num_mem_refs 22316238 # number of memory refs +system.cpu0.num_load_insts 12197914 # Number of load instructions +system.cpu0.num_store_insts 10118324 # Number of store instructions +system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles +system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles +system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles +system.cpu0.Branches 12750711 # Number of branches fetched +system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction +system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction +system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 70304633 # Class of executed instruction +system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3029 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 820099 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.829843 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241744 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 820611 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.694570 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 401.515698 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 110.314145 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.784210 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.215457 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821400 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 174.965504 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 336.736532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.341730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177137427 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177137427 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11786116 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11329399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115515 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9461522 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9365348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18826870 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201006 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191753 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392759 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 231308 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212173 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443481 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239891 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220488 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29820.218002 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31251.644707 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -721,201 +718,201 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 683625 # number of writebacks -system.cpu0.dcache.writebacks::total 683625 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 291 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 369 # 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number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5546086000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10728204000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017035 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017054 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015217 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015635 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230689 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.224470 # 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018883 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228 # 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mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25050.026809 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23722.338878 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183023.161278 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196696.745465 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189729.093070 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145348.540832 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 193742.319938 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165732.900794 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164126.087639 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 195420.031980 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178456.067907 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37180.146542 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 33892.999089 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35530.620263 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33904.704683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31006.127998 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32448.350937 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190199.669421 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191093.892462 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.531762 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173647.785478 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173695.207154 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173672.387546 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182462.518925 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182882.213282 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182679.244640 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # 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miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014780 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014615 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014780 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014615 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014780 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13704.620373 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.726858 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13741.360814 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10879995500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10760237500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21640233000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 676974000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12741.360814 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1002,60 +1005,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6604 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6604 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1835 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4768 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6603 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6472.015315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1651 30.12% 30.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2769 50.52% 80.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1058 19.30% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.995586 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000200000 -99.56% -99.56% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2004834564 199.56% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3666 66.90% 66.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1814 33.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5480 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6604 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6703 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6604 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5480 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12084 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12016469 # DTB read hits -system.cpu1.dtb.read_misses 5667 # DTB read misses -system.cpu1.dtb.write_hits 9752712 # DTB write hits -system.cpu1.dtb.write_misses 937 # DTB write misses -system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12475099 # DTB read hits +system.cpu1.dtb.read_misses 5811 # DTB read misses +system.cpu1.dtb.write_hits 9951122 # DTB write hits +system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4084 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12022136 # DTB read accesses -system.cpu1.dtb.write_accesses 9753649 # DTB write accesses +system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12480910 # DTB read accesses +system.cpu1.dtb.write_accesses 9952014 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21769181 # DTB hits -system.cpu1.dtb.misses 6604 # DTB misses -system.cpu1.dtb.accesses 21775785 # DTB accesses +system.cpu1.dtb.hits 22426221 # DTB hits +system.cpu1.dtb.misses 6703 # DTB misses +system.cpu1.dtb.accesses 22432924 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1085,122 +1082,119 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3234 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3234 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 677 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3234 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6613.791032 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 712 29.30% 29.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.04% 29.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.70% 57.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 477 19.63% 76.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 16 0.66% 77.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 551 22.67% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.14% 72.14% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 677 27.86% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3400 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3234 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3234 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5664 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 56973488 # ITB inst hits -system.cpu1.itb.inst_misses 3234 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58726785 # ITB inst hits +system.cpu1.itb.inst_misses 3400 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2428 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 56976722 # ITB inst accesses -system.cpu1.itb.hits 56973488 # DTB hits -system.cpu1.itb.misses 3234 # DTB misses -system.cpu1.itb.accesses 56976722 # DTB accesses -system.cpu1.numCycles 2902983091 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses +system.cpu1.itb.hits 58726785 # DTB hits +system.cpu1.itb.misses 3400 # DTB misses +system.cpu1.itb.accesses 58730185 # DTB accesses +system.cpu1.numCycles 2908727473 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55453570 # Number of instructions committed -system.cpu1.committedOps 66903769 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59172733 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5746 # Number of float alu accesses -system.cpu1.num_func_calls 4791563 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7521701 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59172733 # number of integer instructions -system.cpu1.num_fp_insts 5746 # number of float instructions -system.cpu1.num_int_register_reads 107592864 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40634379 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4256 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 241317525 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25809860 # number of times the CC registers were written -system.cpu1.num_mem_refs 22393766 # number of memory refs -system.cpu1.num_load_insts 12173697 # Number of load instructions -system.cpu1.num_store_insts 10220069 # Number of store instructions -system.cpu1.num_idle_cycles 2697480671.520393 # Number of idle cycles -system.cpu1.num_busy_cycles 205502419.479607 # Number of busy cycles -system.cpu1.not_idle_fraction 0.070790 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.929210 # Percentage of idle cycles -system.cpu1.Branches 12715726 # Number of branches fetched -system.cpu1.op_class::No_OpClass 132 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45969122 67.18% 67.19% # Class of executed instruction -system.cpu1.op_class::IntMult 54656 0.08% 67.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4033 0.01% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::MemRead 12173697 17.79% 85.06% # Class of executed instruction -system.cpu1.op_class::MemWrite 10220069 14.94% 100.00% # Class of executed instruction +system.cpu1.committedInsts 57164215 # Number of instructions committed +system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses +system.cpu1.num_func_calls 5082908 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60957593 # number of integer instructions +system.cpu1.num_fp_insts 5807 # number of float instructions +system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written +system.cpu1.num_mem_refs 23089661 # number of memory refs +system.cpu1.num_load_insts 12644031 # Number of load instructions +system.cpu1.num_store_insts 10445630 # Number of store instructions +system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles +system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles +system.cpu1.Branches 13165858 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction +system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68421709 # Class of executed instruction +system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1225,9 +1219,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1250,9 +1244,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1293,52 +1287,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187451467 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.079135 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309074032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079135 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067446 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271859590 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271859590 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1347,14 +1341,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1365,22 +1359,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16961877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16961877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16961877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16961877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1389,262 +1383,262 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74394.197368 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74394.197368 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79664.508227 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79664.508227 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 89754 # number of replacements -system.l2c.tags.tagsinuse 64926.218037 # Cycle average of tags in use -system.l2c.tags.total_refs 4554949 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154987 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.389233 # Average number of references to valid blocks. +system.l2c.tags.replacements 87592 # number of replacements +system.l2c.tags.tagsinuse 64865.832577 # Cycle average of tags in use +system.l2c.tags.total_refs 4555575 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152761 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.821584 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50375.736083 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.809030 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965062 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4670.410821 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2880.132547 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.905198 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4955.443121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2037.816176 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.768673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000058 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6959 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56093 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995285 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40606108 # Number of tag accesses -system.l2c.tags.data_accesses 40606108 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5766 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3120 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2899 # number of ReadReq hits -system.l2c.ReadReq_hits::total 17310 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 683625 # number of Writeback hits -system.l2c.Writeback_hits::total 683625 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.034183 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.084248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40610992 # Number of tag accesses +system.l2c.tags.data_accesses 40610992 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3376 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18903 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 685305 # number of Writeback hits +system.l2c.Writeback_hits::total 685305 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 80673 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167416 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 834184 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 844481 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1678665 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 252476 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 260979 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 513455 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3132 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 834184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 333149 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3376 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 844481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 347722 # number of demand (read+write) hits +system.l2c.demand_hits::total 2378439 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6164 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3132 # number of overall hits +system.l2c.overall_hits::cpu0.inst 834184 # number of overall hits +system.l2c.overall_hits::cpu0.data 333149 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6231 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3376 # number of overall hits +system.l2c.overall_hits::cpu1.inst 844481 # number of overall hits +system.l2c.overall_hits::cpu1.data 347722 # number of overall hits +system.l2c.overall_hits::total 2378439 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::total 10 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1366 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 8 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1339 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70721 # Transaction distribution +system.membus.trans_dist::ReadResp 70627 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 119469 # Transaction distribution -system.membus.trans_dist::CleanEvict 6488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution +system.membus.trans_dist::CleanEvict 6338 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129210 # Transaction distribution -system.membus.trans_dist::ReadExResp 129210 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30561 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution +system.membus.trans_dist::ReadExReq 127036 # Transaction distribution +system.membus.trans_dist::ReadExResp 127036 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 445477 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 553069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 661969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15578364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15741717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18058837 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394437 # Request fanout histogram +system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 389991 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394437 # Request fanout histogram -system.membus.reqLayer0.occupancy 90486000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389991 # Request fanout histogram +system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1696500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834684564 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964305240 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64480996 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1910,63 +1910,69 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 74970 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2298377 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 803098 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1802826 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1698424 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 524998 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5081680 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2577380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711190 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108733880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96470557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45196 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205273717 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180370 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5305015 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.037219 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.189299 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176740 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5107565 96.28% 96.28% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 197450 3.72% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5305015 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3268607000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2556658000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1277273499 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12003000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22807000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fee5e3090..838105743 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1340669 # Simulator instruction rate (inst/s) -host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257071569 # Simulator tick rate (ticks/s) -host_mem_usage 654012 # Number of bytes of host memory used -host_seconds 149.23 # Real time elapsed on the host +host_inst_rate 1349307 # Simulator instruction rate (inst/s) +host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34477807791 # Simulator tick rate (ticks/s) +host_mem_usage 659588 # Number of bytes of host memory used +host_seconds 148.27 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -337,9 +337,9 @@ system.cpu.itb_walker_cache.writebacks::total 545 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106193 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor @@ -359,8 +359,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits @@ -456,42 +456,48 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks system.cpu.l2cache.writebacks::total 98168 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 49698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram +system.cpu.toL2Bus.snoops 203459 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -600,7 +606,7 @@ system.membus.trans_dist::ReadResp 13903747 # Tr system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 9844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8392 # Transaction distribution system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution system.membus.trans_dist::ReadExReq 134360 # Transaction distribution @@ -614,11 +620,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) @@ -629,17 +635,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14257691 # Request fanout histogram +system.membus.snoop_fanout::samples 14256770 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14257691 # Request fanout histogram +system.membus.snoop_fanout::total 14256770 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 2f3799b17..aa1e69b35 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.184733 # Number of seconds simulated -sim_ticks 5184732721500 # Number of ticks simulated -final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194921 # Number of seconds simulated +sim_ticks 5194921252500 # Number of ticks simulated +final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808289 # Simulator instruction rate (inst/s) -host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32570584041 # Simulator tick rate (ticks/s) -host_mem_usage 654268 # Number of bytes of host memory used -host_seconds 159.18 # Real time elapsed on the host -sim_insts 128667033 # Number of instructions simulated -sim_ops 248022101 # Number of ops (including micro ops) simulated +host_inst_rate 862150 # Simulator instruction rate (inst/s) +host_op_rate 1661827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34815163679 # Simulator tick rate (ticks/s) +host_mem_usage 660376 # Number of bytes of host memory used +host_seconds 149.21 # Real time elapsed on the host +sim_insts 128645146 # Number of instructions simulated +sim_ops 247968367 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory +system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory +system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory +system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154671 # Number of read requests accepted -system.physmem.writeReqs 127079 # Number of write requests accepted -system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153570 # Number of read requests accepted +system.physmem.writeReqs 126163 # Number of write requests accepted +system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side +system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9772 # Per bank write bursts -system.physmem.perBankRdBursts::1 9412 # Per bank write bursts -system.physmem.perBankRdBursts::2 9829 # Per bank write bursts -system.physmem.perBankRdBursts::3 9622 # Per bank write bursts -system.physmem.perBankRdBursts::4 9563 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 9720 # Per bank write bursts -system.physmem.perBankRdBursts::7 9664 # Per bank write bursts -system.physmem.perBankRdBursts::8 9219 # Per bank write bursts -system.physmem.perBankRdBursts::9 9313 # Per bank write bursts -system.physmem.perBankRdBursts::10 9431 # Per bank write bursts -system.physmem.perBankRdBursts::11 9415 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10194 # Per bank write bursts -system.physmem.perBankRdBursts::14 10163 # Per bank write bursts -system.physmem.perBankRdBursts::15 9855 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 7960 # Per bank write bursts -system.physmem.perBankWrBursts::2 8144 # Per bank write bursts -system.physmem.perBankWrBursts::3 8236 # Per bank write bursts -system.physmem.perBankWrBursts::4 8504 # Per bank write bursts -system.physmem.perBankWrBursts::5 7731 # Per bank write bursts -system.physmem.perBankWrBursts::6 7974 # Per bank write bursts -system.physmem.perBankWrBursts::7 7835 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 7555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7609 # Per bank write bursts -system.physmem.perBankWrBursts::11 7637 # Per bank write bursts -system.physmem.perBankWrBursts::12 8092 # Per bank write bursts -system.physmem.perBankWrBursts::13 8095 # Per bank write bursts -system.physmem.perBankWrBursts::14 8240 # Per bank write bursts -system.physmem.perBankWrBursts::15 8007 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9606 # Per bank write bursts +system.physmem.perBankRdBursts::1 9083 # Per bank write bursts +system.physmem.perBankRdBursts::2 10021 # Per bank write bursts +system.physmem.perBankRdBursts::3 9578 # Per bank write bursts +system.physmem.perBankRdBursts::4 9425 # Per bank write bursts +system.physmem.perBankRdBursts::5 9133 # Per bank write bursts +system.physmem.perBankRdBursts::6 9428 # Per bank write bursts +system.physmem.perBankRdBursts::7 9379 # Per bank write bursts +system.physmem.perBankRdBursts::8 9296 # Per bank write bursts +system.physmem.perBankRdBursts::9 9532 # Per bank write bursts +system.physmem.perBankRdBursts::10 9485 # Per bank write bursts +system.physmem.perBankRdBursts::11 9788 # Per bank write bursts +system.physmem.perBankRdBursts::12 9982 # Per bank write bursts +system.physmem.perBankRdBursts::13 10070 # Per bank write bursts +system.physmem.perBankRdBursts::14 9926 # Per bank write bursts +system.physmem.perBankRdBursts::15 9679 # Per bank write bursts +system.physmem.perBankWrBursts::0 8208 # Per bank write bursts +system.physmem.perBankWrBursts::1 7344 # Per bank write bursts +system.physmem.perBankWrBursts::2 8031 # Per bank write bursts +system.physmem.perBankWrBursts::3 7623 # Per bank write bursts +system.physmem.perBankWrBursts::4 7645 # Per bank write bursts +system.physmem.perBankWrBursts::5 7565 # Per bank write bursts +system.physmem.perBankWrBursts::6 7708 # Per bank write bursts +system.physmem.perBankWrBursts::7 7791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7759 # Per bank write bursts +system.physmem.perBankWrBursts::9 7930 # Per bank write bursts +system.physmem.perBankWrBursts::10 7732 # Per bank write bursts +system.physmem.perBankWrBursts::11 7853 # Per bank write bursts +system.physmem.perBankWrBursts::12 8038 # Per bank write bursts +system.physmem.perBankWrBursts::13 8512 # Per bank write bursts +system.physmem.perBankWrBursts::14 8378 # Per bank write bursts +system.physmem.perBankWrBursts::15 8027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5184732588500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5194921069000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154671 # Read request sizes (log2) +system.physmem.readPktSize::6 153570 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127079 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,189 +152,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2863 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads -system.physmem.totQLat 1454171981 # Total ticks spent queuing -system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads +system.physmem.totQLat 1519267484 # Total ticks spent queuing +system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 126926 # Number of row buffer hits during reads -system.physmem.writeRowHits 98756 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes -system.physmem.avgGap 18401890.29 # Average gap between requests -system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.747605 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states -system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 125316 # Number of row buffer hits during reads +system.physmem.writeRowHits 98271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes +system.physmem.avgGap 18570998.31 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136710410535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997028289250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474354711360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798995 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985717898976 # Time in different power states +system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35728624774 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.760386 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states -system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137303657415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996507897250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474476838525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.822504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984854152228 # Time in different power states +system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36597268272 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10369465443 # number of cpu cycles simulated +system.cpu.numCycles 10389842505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128667033 # Number of instructions committed -system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses +system.cpu.committedInsts 128645146 # Number of instructions committed +system.cpu.committedOps 247968367 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232546073 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2317363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls -system.cpu.num_int_insts 232599125 # number of integer instructions +system.cpu.num_func_calls 2315361 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls +system.cpu.num_int_insts 232546073 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read -system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written +system.cpu.num_int_register_reads 435625867 # number of times the integer registers were read +system.cpu.num_int_register_writes 198317571 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written -system.cpu.num_mem_refs 22356642 # number of memory refs -system.cpu.num_load_insts 13946240 # Number of load instructions -system.cpu.num_store_insts 8410402 # Number of store instructions -system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942137 # Percentage of idle cycles -system.cpu.Branches 26370667 # Number of branches fetched -system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133116487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95666128 # number of times the CC registers were written +system.cpu.num_mem_refs 22339099 # number of memory refs +system.cpu.num_load_insts 13935933 # Number of load instructions +system.cpu.num_store_insts 8403166 # Number of store instructions +system.cpu.num_idle_cycles 9774871363.998119 # Number of idle cycles +system.cpu.num_busy_cycles 614971141.001882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940810 # Percentage of idle cycles +system.cpu.Branches 26367781 # Number of branches fetched +system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225200251 90.82% 90.89% # Class of executed instruction +system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -361,215 +360,215 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13930961 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8403166 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248023648 # Class of executed instruction +system.cpu.op_class::total 247969928 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1621027 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20151381 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621539 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.427318 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1623328 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20131143 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.397245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59170 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20090042 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20090042 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20149212 # number of overall hits -system.cpu.dcache.overall_hits::total 20149212 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905821 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905821 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324802 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324802 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402538 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402538 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1230623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1230623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633161 # number of overall misses -system.cpu.dcache.overall_misses::total 1633161 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12812474000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12812474000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12127378479 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12127378479 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24939852479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24939852479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24939852479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24939852479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12918257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12918257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20266.037998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15270.908673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5798 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88683234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88683234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12000893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12000893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8069415 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8069415 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58662 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58662 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20070308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20070308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20128970 # number of overall hits +system.cpu.dcache.overall_hits::total 20128970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1635865 # number of overall misses +system.cpu.dcache.overall_misses::total 1635865 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13550557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13550557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18295357977 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18295357977 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31845914977 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31845914977 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31845914977 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31845914977 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12907776 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12907776 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21302963 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21302963 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764835 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764835 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075161 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075161 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25835.221515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19467.324612 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15094 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # 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average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8927 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8927 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2877 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2877 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792637 # number of replacements -system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 789867 # number of replacements +system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144930127 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.367887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits -system.cpu.icache.overall_hits::total 144952019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses -system.cpu.icache.overall_misses::total 793156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146510899 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146510899 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144930127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144930127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144930127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144930127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144930127 # number of overall hits +system.cpu.icache.overall_hits::total 144930127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 790386 # number of overall misses +system.cpu.icache.overall_misses::total 790386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11833714500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11833714500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11833714500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11833714500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145720513 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145720513 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145720513 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145720513 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14972.069976 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790386 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790386 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790386 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790386 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3784 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.071212 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7587 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3797 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.998156 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071212 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29077 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29077 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7587 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7587 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7589 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7589 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4633 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4633 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,169 +755,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 721 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 721 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87263 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86240 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64592.333945 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4367637 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 150989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.926856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3457.643805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764977 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89985064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89985064500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063575 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063575 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 189246 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 188441 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226549 # Transaction distribution -system.iobus.trans_dist::ReadResp 226549 # Transaction distribution +system.iobus.trans_dist::ReadReq 226550 # Transaction distribution +system.iobus.trans_dist::ReadResp 226550 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1652 # Transaction distribution -system.iobus.trans_dist::MessageResp 1652 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1095,11 +1100,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1119,12 +1124,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1160,54 +1165,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428085 # Number of tag accesses -system.iocache.tags.data_accesses 428085 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses -system.iocache.ReadReq_misses::total 845 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses -system.iocache.demand_misses::total 845 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses -system.iocache.overall_misses::total 845 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles -system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1216,40 +1221,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1258,73 +1263,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615177 # Transaction distribution -system.membus.trans_dist::WriteReq 13916 # Transaction distribution -system.membus.trans_dist::WriteResp 13916 # Transaction distribution -system.membus.trans_dist::Writeback 127079 # Transaction distribution -system.membus.trans_dist::CleanEvict 7222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution -system.membus.trans_dist::ReadExReq 113502 # Transaction distribution -system.membus.trans_dist::ReadExResp 113502 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution -system.membus.trans_dist::MessageReq 1652 # Transaction distribution -system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::WriteReq 13920 # Transaction distribution +system.membus.trans_dist::WriteResp 13920 # Transaction distribution +system.membus.trans_dist::Writeback 126163 # Transaction distribution +system.membus.trans_dist::CleanEvict 7113 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution +system.membus.trans_dist::ReadExReq 112377 # Transaction distribution +system.membus.trans_dist::ReadExResp 112377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1580 # Total snoops (count) -system.membus.snoop_fanout::samples 927896 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram +system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1565 # Total snoops (count) +system.membus.snoop_fanout::samples 925791 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram -system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 927896 # Request fanout histogram -system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 925791 # Request fanout histogram +system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 1a6e00d22..e3deed2b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37552000 # Number of ticks simulated -final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37553000 # Number of ticks simulated +final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72134 # Simulator instruction rate (inst/s) -host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423067865 # Simulator tick rate (ticks/s) -host_mem_usage 288748 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 161315 # Simulator instruction rate (inst/s) +host_op_rate 161262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 945919395 # Simulator tick rate (ticks/s) +host_mem_usage 296228 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37447500 # Total gap between requests +system.physmem.totGap 37448500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.10 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70257.97 # Average gap between requests +system.physmem.avgGap 70259.85 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -293,24 +293,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75104 # number of cpu cycles simulated +system.cpu.numCycles 75106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.735000 # CPI: cycles per instruction -system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.cpi 11.735312 # CPI: cycles per instruction +system.cpu.ipc 0.085213 # IPC: instructions per cycle system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id @@ -443,12 +443,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses @@ -461,12 +461,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,33 +481,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy @@ -640,6 +640,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -653,14 +659,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 85a8b430a..58b2620bf 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43231 # Simulator instruction rate (inst/s) -host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148545474 # Simulator tick rate (ticks/s) -host_mem_usage 289772 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 94413 # Simulator instruction rate (inst/s) +host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 324370159 # Simulator tick rate (ticks/s) +host_mem_usage 297000 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -698,12 +698,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -724,12 +724,12 @@ system.cpu.icache.demand_misses::cpu.inst 459 # n system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses system.cpu.icache.overall_misses::total 459 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses @@ -742,12 +742,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,24 +768,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311 system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use @@ -927,6 +927,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -940,14 +946,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2c1174c59..e7401ee31 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544500 # Number of ticks simulated -final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32545500 # Number of ticks simulated +final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 619666 # Simulator instruction rate (inst/s) -host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3148046044 # Simulator tick rate (ticks/s) -host_mem_usage 291528 # Number of bytes of host memory used +host_inst_rate 507828 # Simulator instruction rate (inst/s) +host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581337246 # Simulator tick rate (ticks/s) +host_mem_usage 294696 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65089 # number of cpu cycles simulated +system.cpu.numCycles 65091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65089 # Number of busy cycles +system.cpu.num_busy_cycles 65091 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id @@ -226,14 +226,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,36 +290,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -462,14 +468,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 2f7c0906a..a420f2b35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20075000 # Number of ticks simulated final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42420 # Simulator instruction rate (inst/s) -host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329231154 # Simulator tick rate (ticks/s) -host_mem_usage 287436 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 131673 # Simulator instruction rate (inst/s) +host_op_rate 131586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1021264689 # Simulator tick rate (ticks/s) +host_mem_usage 295944 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -634,6 +634,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -647,15 +653,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6ee889334..c4983f8bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20992 # Simulator instruction rate (inst/s) -host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108692792 # Simulator tick rate (ticks/s) -host_mem_usage 288464 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 79745 # Simulator instruction rate (inst/s) +host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412680664 # Simulator tick rate (ticks/s) +host_mem_usage 295680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -919,6 +919,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -932,15 +938,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 7411927e4..6bacfac4e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 374183 # Simulator instruction rate (inst/s) -host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2390351512 # Simulator tick rate (ticks/s) -host_mem_usage 291260 # Number of bytes of host memory used +host_inst_rate 315037 # Simulator instruction rate (inst/s) +host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2013954906 # Simulator tick rate (ticks/s) +host_mem_usage 293376 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -456,15 +462,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 3e86bd3ac..ffa31a0bc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29941500 # Number of ticks simulated -final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29949500 # Number of ticks simulated +final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58660 # Simulator instruction rate (inst/s) -host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381226078 # Simulator tick rate (ticks/s) -host_mem_usage 304332 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 110305 # Simulator instruction rate (inst/s) +host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 716958322 # Simulator tick rate (ticks/s) +host_mem_usage 313816 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29851000 # Total gap between requests +system.physmem.totGap 29858000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2218000 # Total ticks spent queuing -system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2201000 # Total ticks spent queuing +system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70904.99 # Average gap between requests +system.physmem.avgGap 70921.62 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59883 # number of cpu cycles simulated +system.cpu.numCycles 59899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.003909 # CPI: cycles per instruction -system.cpu.ipc 0.076900 # IPC: instructions per cycle +system.cpu.cpi 13.007383 # CPI: cycles per instruction +system.cpu.ipc 0.076879 # IPC: instructions per cycle system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id @@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -499,24 +499,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,34 +573,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id @@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 # system.cpu.l2cache.overall_misses::total 429 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116 system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -731,17 +731,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -756,14 +762,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) @@ -791,7 +797,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index be50d79db..0d7cf1bb4 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17163000 # Number of ticks simulated -final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17170000 # Number of ticks simulated +final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25428 # Simulator instruction rate (inst/s) -host_op_rate 29777 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95019968 # Simulator tick rate (ticks/s) -host_mem_usage 305352 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 50361 # Simulator instruction rate (inst/s) +host_op_rate 58973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188251031 # Simulator tick rate (ticks/s) +host_mem_usage 313812 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17090000 # Total gap between requests +system.physmem.totGap 17097000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # By system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3055250 # Total ticks spent queuing -system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3045250 # Total ticks spent queuing +system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.54 # Data bus utilization in percentage -system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.53 # Data bus utilization in percentage +system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,21 +220,21 @@ system.physmem.readRowHits 330 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43156.57 # Average gap between requests +system.physmem.avgGap 43174.24 # Average gap between requests system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.198611 # Core power per rank (mW) +system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.108972 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) @@ -245,18 +245,18 @@ system.physmem_1.actBackEnergy 10407915 # En system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) system.physmem_1.averagePower 807.028896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2533 # Number of BP lookups -system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups -system.cpu.branchPred.BTBHits 812 # Number of BTB hits +system.cpu.branchPred.lookups 2537 # Number of BP lookups +system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups +system.cpu.branchPred.BTBHits 814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -496,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34327 # number of cpu cycles simulated +system.cpu.numCycles 34341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2063 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1964 # Number of cycles rename is running +system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1962 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 42 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available @@ -620,69 +620,69 @@ system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7972 # Type of FU issued -system.cpu.iq.rate 0.232237 # Inst issue rate +system.cpu.iq.FU_type_0::total 7975 # Type of FU issued +system.cpu.iq.rate 0.232230 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall @@ -690,43 +690,43 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2930 # number of memory reference insts executed -system.cpu.iew.exec_branches 1433 # Number of branches executed -system.cpu.iew.exec_stores 1194 # Number of stores executed -system.cpu.iew.exec_rate 0.224226 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3456 # num instructions producing a value -system.cpu.iew.wb_consumers 6757 # num instructions consuming a value +system.cpu.iew.exec_refs 2933 # number of memory reference insts executed +system.cpu.iew.exec_branches 1435 # Number of branches executed +system.cpu.iew.exec_stores 1197 # Number of stores executed +system.cpu.iew.exec_rate 0.224251 # Inst execution rate +system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3459 # num instructions producing a value +system.cpu.iew.wb_consumers 6763 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back +system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -773,32 +773,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21783 # The number of ROB reads -system.cpu.rob.rob_writes 20313 # The number of ROB writes -system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21787 # The number of ROB reads +system.cpu.rob.rob_writes 20281 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7631 # number of integer regfile reads +system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7636 # number of integer regfile reads system.cpu.int_regfile_writes 4176 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27375 # number of cc regfile reads -system.cpu.cc_regfile_writes 3204 # number of cc regfile writes -system.cpu.misc_regfile_reads 3054 # number of misc regfile reads +system.cpu.cc_regfile_reads 27387 # number of cc regfile reads +system.cpu.cc_regfile_writes 3201 # number of cc regfile writes +system.cpu.misc_regfile_reads 3057 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id @@ -827,16 +827,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -859,16 +859,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -895,14 +895,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses @@ -911,66 +911,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4229 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits -system.cpu.icache.overall_hits::total 1582 # number of overall hits +system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4235 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits +system.cpu.icache.overall_hits::total 1585 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses system.cpu.icache.overall_misses::total 386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -991,33 +991,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 293 system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy @@ -1051,16 +1051,16 @@ system.cpu.l2cache.overall_misses::cpu.data 126 # system.cpu.l2cache.overall_misses::total 401 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) @@ -1087,16 +1087,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1125,16 +1125,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 121 system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses @@ -1149,17 +1149,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1173,14 +1179,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index c7177147a..8015f8322 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17777000 # Number of ticks simulated -final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17778000 # Number of ticks simulated +final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63242 # Simulator instruction rate (inst/s) -host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244740900 # Simulator tick rate (ticks/s) -host_mem_usage 307828 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58925 # Simulator instruction rate (inst/s) +host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228057572 # Simulator tick rate (ticks/s) +host_mem_usage 310616 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17763500 # Total gap between requests +system.physmem.totGap 17764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3130500 # Total ticks spent queuing -system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3121500 # Total ticks spent queuing +system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.45 # Data bus utilization in percentage @@ -224,35 +224,35 @@ system.physmem.readRowHits 340 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43644.96 # Average gap between requests +system.physmem.avgGap 43647.42 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.346375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states +system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.276555 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.767883 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states +system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.747987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2336 # Number of BP lookups system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35555 # number of cpu cycles simulated +system.cpu.numCycles 35557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5038 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5040 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4094 # Number of cycles rename is running +system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4096 # Number of cycles rename is running system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7146 # Type of FU issued -system.cpu.iq.rate 0.200984 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7148 # Type of FU issued +system.cpu.iq.rate 0.201029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed @@ -561,9 +561,9 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -572,7 +572,7 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -580,35 +580,35 @@ system.cpu.iew.exec_nop 14 # nu system.cpu.iew.exec_refs 2427 # number of memory reference insts executed system.cpu.iew.exec_branches 1272 # Number of branches executed system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189622 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2975 # num instructions producing a value -system.cpu.iew.wb_consumers 5372 # num instructions consuming a value +system.cpu.iew.exec_rate 0.189667 # Inst execution rate +system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6569 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2977 # num instructions producing a value +system.cpu.iew.wb_consumers 5378 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22320 # The number of ROB reads -system.cpu.rob.rob_writes 16439 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22343 # The number of ROB reads +system.cpu.rob.rob_writes 16451 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6718 # number of integer regfile reads -system.cpu.int_regfile_writes 3745 # number of integer regfile writes +system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6720 # number of integer regfile reads +system.cpu.int_regfile_writes 3747 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23959 # number of cc regfile reads +system.cpu.cc_regfile_reads 23965 # number of cc regfile reads system.cpu.cc_regfile_writes 2898 # number of cc regfile writes system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -709,16 +709,16 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -741,16 +741,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,14 +777,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -793,71 +793,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits -system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7943 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits +system.cpu.icache.overall_hits::total 3460 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296 system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -947,16 +947,16 @@ system.cpu.l2cache.overall_misses::cpu.data 113 # system.cpu.l2cache.overall_misses::total 386 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) @@ -983,16 +983,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,17 +1030,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1060,18 +1060,24 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution @@ -1087,15 +1093,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) @@ -1122,9 +1128,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 85d747802..d4b2570c8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25816500 # Number of ticks simulated -final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25848500 # Number of ticks simulated +final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428411 # Simulator instruction rate (inst/s) -host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2416370273 # Simulator tick rate (ticks/s) -host_mem_usage 308620 # Number of bytes of host memory used +host_inst_rate 341128 # Simulator instruction rate (inst/s) +host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1927554064 # Simulator tick rate (ticks/s) +host_mem_usage 312280 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51633 # number of cpu cycles simulated +system.cpu.numCycles 51697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy @@ -547,6 +547,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution @@ -560,14 +566,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index d3878acf4..c52a652eb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22451000 # Number of ticks simulated final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41665 # Simulator instruction rate (inst/s) -host_op_rate 41658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187549895 # Simulator tick rate (ticks/s) -host_mem_usage 287968 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 76638 # Simulator instruction rate (inst/s) +host_op_rate 76622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344943613 # Simulator tick rate (ticks/s) +host_mem_usage 294148 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -912,6 +912,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -926,15 +932,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 7140a68cc..d99d61508 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30902500 # Number of ticks simulated final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339265 # Simulator instruction rate (inst/s) -host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1861147916 # Simulator tick rate (ticks/s) -host_mem_usage 289452 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 459853 # Simulator instruction rate (inst/s) +host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2521006690 # Simulator tick rate (ticks/s) +host_mem_usage 291832 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -435,6 +435,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -449,15 +455,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 585054648..1b72b1558 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19922000 # Number of ticks simulated -final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19923000 # Number of ticks simulated +final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38523 # Simulator instruction rate (inst/s) -host_op_rate 38518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132470471 # Simulator tick rate (ticks/s) -host_mem_usage 286104 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 93968 # Simulator instruction rate (inst/s) +host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323084408 # Simulator tick rate (ticks/s) +host_mem_usage 291680 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19782500 # Total gap between requests +system.physmem.totGap 19783500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # By system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3750750 # Total ticks spent queuing -system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3746750 # Total ticks spent queuing +system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.14 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 359 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44555.18 # Average gap between requests +system.physmem.avgGap 44557.43 # Average gap between requests system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) @@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 7628310 # En system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) system.physmem_1.averagePower 748.283278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states @@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 39845 # number of cpu cycles simulated +system.cpu.numCycles 39847 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss @@ -310,8 +310,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1924 # Number of cycles decode is running @@ -437,7 +437,7 @@ system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8840 # Type of FU issued -system.cpu.iq.rate 0.221860 # Inst issue rate +system.cpu.iq.rate 0.221849 # Inst issue rate system.cpu.iq.fu_busy_cnt 201 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads @@ -481,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3121 # number of memory reference insts executed system.cpu.iew.exec_branches 1355 # Number of branches executed system.cpu.iew.exec_stores 1414 # Number of stores executed -system.cpu.iew.exec_rate 0.212950 # Inst execution rate +system.cpu.iew.exec_rate 0.212939 # Inst execution rate system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8147 # cumulative count of insts written-back system.cpu.iew.wb_producers 4452 # num instructions producing a value system.cpu.iew.wb_consumers 7114 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle +system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit @@ -559,24 +559,24 @@ system.cpu.commit.bw_lim_events 110 # nu system.cpu.rob.rob_reads 21420 # The number of ROB reads system.cpu.rob.rob_writes 21108 # The number of ROB writes system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads +system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13451 # number of integer regfile reads system.cpu.int_regfile_writes 7138 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id @@ -601,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 433 # n system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses system.cpu.dcache.overall_misses::total 433 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -625,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 103 system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -673,22 +673,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 433 # n system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses @@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -753,39 +753,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses @@ -813,16 +813,16 @@ system.cpu.l2cache.overall_misses::cpu.data 101 # system.cpu.l2cache.overall_misses::total 445 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -849,16 +849,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -881,16 +881,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 101 system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -905,17 +905,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -929,14 +935,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index fd8319ed7..a369fae45 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800500 # Number of ticks simulated -final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27803500 # Number of ticks simulated +final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428112 # Simulator instruction rate (inst/s) -host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2229390537 # Simulator tick rate (ticks/s) -host_mem_usage 290104 # Number of bytes of host memory used +host_inst_rate 506128 # Simulator instruction rate (inst/s) +host_op_rate 505504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2635153066 # Simulator tick rate (ticks/s) +host_mem_usage 292480 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55601 # number of cpu cycles simulated +system.cpu.numCycles 55607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id @@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -258,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy @@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index e476df038..b13c74560 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20817000 # Number of ticks simulated -final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20818000 # Number of ticks simulated +final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31285 # Simulator instruction rate (inst/s) -host_op_rate 56673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121026192 # Simulator tick rate (ticks/s) -host_mem_usage 306568 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 48919 # Simulator instruction rate (inst/s) +host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189245943 # Simulator tick rate (ticks/s) +host_mem_usage 313416 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory system.physmem.num_reads::total 415 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20721000 # Total gap between requests +system.physmem.totGap 20722000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2075000 # To system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.97 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 309 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49930.12 # Average gap between requests +system.physmem.avgGap 49932.53 # Average gap between requests system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) @@ -262,7 +262,7 @@ system.cpu.branchPred.RASInCorrect 86 # Nu system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41635 # number of cpu cycles simulated +system.cpu.numCycles 41637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss @@ -293,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3206 # Number of cycles decode is running @@ -417,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17161 # Type of FU issued -system.cpu.iq.rate 0.412177 # Inst issue rate +system.cpu.iq.rate 0.412157 # Inst issue rate system.cpu.iq.fu_busy_cnt 212 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads @@ -461,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3175 # number of memory reference insts executed system.cpu.iew.exec_branches 1626 # Number of branches executed system.cpu.iew.exec_stores 1262 # Number of stores executed -system.cpu.iew.exec_rate 0.390657 # Inst execution rate +system.cpu.iew.exec_rate 0.390638 # Inst execution rate system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit system.cpu.iew.wb_count 15771 # cumulative count of insts written-back system.cpu.iew.wb_producers 10637 # num instructions producing a value system.cpu.iew.wb_consumers 16589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle +system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit @@ -539,13 +539,13 @@ system.cpu.commit.bw_lim_events 255 # nu system.cpu.rob.rob_reads 41158 # The number of ROB reads system.cpu.rob.rob_writes 42744 # The number of ROB writes system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads +system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 20871 # number of integer regfile reads system.cpu.int_regfile_writes 12651 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -554,12 +554,12 @@ system.cpu.cc_regfile_writes 4880 # nu system.cpu.misc_regfile_reads 7277 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id @@ -664,17 +664,17 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.298609 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.298609 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063622 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063622 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses system.cpu.icache.tags.data_accesses 4427 # Number of data accesses @@ -690,12 +690,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28131500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28131500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28131500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28131500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses @@ -708,12 +708,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76237.127371 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -734,33 +734,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 277 system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22318000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22318000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 162.374270 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.338432 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.035838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy @@ -893,6 +893,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution @@ -906,14 +912,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index ef7ce3c79..a52dc699f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358500 # Number of ticks simulated -final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28359500 # Number of ticks simulated +final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304372 # Simulator instruction rate (inst/s) -host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1601632215 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used +host_inst_rate 279983 # Simulator instruction rate (inst/s) +host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1473373857 # Simulator tick rate (ticks/s) +host_mem_usage 311136 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56717 # number of cpu cycles simulated +system.cpu.numCycles 56719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id @@ -197,14 +197,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -420,6 +420,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -433,14 +439,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 3cf449dc8..9d107898a 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24832500 # Number of ticks simulated final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45282 # Simulator instruction rate (inst/s) -host_op_rate 45279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88223588 # Simulator tick rate (ticks/s) -host_mem_usage 290360 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 79921 # Simulator instruction rate (inst/s) +host_op_rate 79915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155707227 # Simulator tick rate (ticks/s) +host_mem_usage 297588 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -298,59 +298,59 @@ system.cpu.numCycles 49666 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 39559 # Number of instructions fetch has processed +system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10834 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.436733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.801651 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20750 75.36% 75.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 584 2.12% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 571 2.07% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 560 2.03% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3127 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.796501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37298 # Number of cycles decode is idle +system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked system.cpu.decode.RunCycles 5112 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 613 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32201 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37873 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5149 # Number of cycles rename is running +system.cpu.rename.RunCycles 5150 # Number of cycles rename is running system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30276 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22817 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37691 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13677 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 60 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer @@ -847,12 +847,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 8 # number of replacements -system.cpu.icache.tags.tagsinuse 317.015033 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 317.015033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id @@ -873,12 +873,12 @@ system.cpu.icache.demand_misses::cpu.inst 935 # n system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses system.cpu.icache.overall_misses::total 935 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70145997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70145997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70145997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70145997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70145997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70145997 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses @@ -891,12 +891,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75022.456684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75022.456684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75022.456684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75022.456684 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked @@ -917,24 +917,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 634 system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51559499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51559499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51559499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51559499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51559499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51559499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81324.130915 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81324.130915 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements @@ -1078,6 +1078,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution @@ -1092,14 +1098,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 986 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 82d581de7..dca96be88 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26943000 # Number of ticks simulated -final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26944000 # Number of ticks simulated +final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30305 # Simulator instruction rate (inst/s) -host_op_rate 30304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56555572 # Simulator tick rate (ticks/s) -host_mem_usage 288252 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_inst_rate 95332 # Simulator instruction rate (inst/s) +host_op_rate 95323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177899852 # Simulator tick rate (ticks/s) +host_mem_usage 294468 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21888 # Nu system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 489 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26890000 # Total gap between requests +system.physmem.totGap 26891000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2445000 # To system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.07 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 409 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54989.78 # Average gap between requests +system.physmem.avgGap 54991.82 # Average gap between requests system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) @@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 15637950 # En system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ) system.physmem_1.averagePower 817.549616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states @@ -261,14 +261,14 @@ system.cpu.branchPred.usedRAS 554 # Nu system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53887 # number of cpu cycles simulated +system.cpu.numCycles 53889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps @@ -291,8 +291,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked system.cpu.decode.RunCycles 6549 # Number of cycles decode is running @@ -413,7 +413,7 @@ system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 20835 # Type of FU issued -system.cpu.iq.rate 0.386642 # Inst issue rate +system.cpu.iq.rate 0.386628 # Inst issue rate system.cpu.iq.fu_busy_cnt 177 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads @@ -457,13 +457,13 @@ system.cpu.iew.exec_nop 1117 # nu system.cpu.iew.exec_refs 5240 # number of memory reference insts executed system.cpu.iew.exec_branches 4296 # Number of branches executed system.cpu.iew.exec_stores 1999 # Number of stores executed -system.cpu.iew.exec_rate 0.371370 # Inst execution rate +system.cpu.iew.exec_rate 0.371356 # Inst execution rate system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19408 # cumulative count of insts written-back system.cpu.iew.wb_producers 9326 # num instructions producing a value system.cpu.iew.wb_consumers 12017 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle +system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit @@ -535,24 +535,24 @@ system.cpu.commit.bw_lim_events 290 # nu system.cpu.rob.rob_reads 52271 # The number of ROB reads system.cpu.rob.rob_writes 49405 # The number of ROB writes system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.732821 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.732821 # CPI: Total CPI of All Threads -system.cpu.ipc 0.267894 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.267894 # IPC: Total IPC of All Threads +system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads +system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32029 # number of integer regfile reads system.cpu.int_regfile_writes 17799 # number of integer regfile writes system.cpu.misc_regfile_reads 6992 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.068517 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.068517 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id @@ -663,14 +663,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 190.286110 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 190.286110 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.092913 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.092913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id @@ -689,12 +689,12 @@ system.cpu.icache.demand_misses::cpu.inst 519 # n system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses system.cpu.icache.overall_misses::total 519 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36198500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36198500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36198500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36198500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36198500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36198500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses @@ -707,12 +707,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69746.628131 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69746.628131 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,33 +733,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 344 system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26530000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26530000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26530000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26530000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26530000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26530000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.995330 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.659398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.335932 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy @@ -892,6 +892,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution @@ -905,14 +911,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 625747903..b9f25890e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41368500 # Number of ticks simulated -final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 41370500 # Number of ticks simulated +final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 372083 # Simulator instruction rate (inst/s) -host_op_rate 371955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1014555487 # Simulator tick rate (ticks/s) -host_mem_usage 290028 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 454115 # Simulator instruction rate (inst/s) +host_op_rate 453939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1238118753 # Simulator tick rate (ticks/s) +host_mem_usage 292408 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82737 # number of cpu cycles simulated +system.cpu.numCycles 82741 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles +system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -198,12 +198,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id @@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy @@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution @@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 849193946..5eff3b495 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 61608000 # Number of ticks simulated -final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61610000 # Number of ticks simulated +final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214452 # Simulator instruction rate (inst/s) -host_op_rate 214360 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049936831 # Simulator tick rate (ticks/s) -host_mem_usage 674692 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 402374 # Simulator instruction rate (inst/s) +host_op_rate 402048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3843418590 # Simulator tick rate (ticks/s) +host_mem_usage 682268 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61358000 # Total gap between requests +system.mem_ctrl.totGap 61360000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -205,9 +205,9 @@ system.mem_ctrl.totBusLat 2230000 # To system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage @@ -219,7 +219,7 @@ system.mem_ctrl.readRowHits 340 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137573.99 # Average gap between requests +system.mem_ctrl.avgGap 137578.48 # Average gap between requests system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) @@ -282,7 +282,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 61608 # number of cpu cycles simulated +system.cpu.numCycles 61610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6440 # Number of instructions committed @@ -301,7 +301,7 @@ system.cpu.num_mem_refs 2063 # nu system.cpu.num_load_insts 1195 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61608 # Number of busy cycles +system.cpu.num_busy_cycles 61610 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1054 # Number of branches fetched @@ -341,14 +341,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6450 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -445,14 +445,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id @@ -471,12 +471,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses @@ -489,12 +489,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,25 +509,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -541,14 +547,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 511 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 511 # Request fanout histogram system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) @@ -558,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index dde0dd6ed..727647065 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79800 # Simulator instruction rate (inst/s) -host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 797317444 # Simulator tick rate (ticks/s) -host_mem_usage 690160 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 351391 # Simulator instruction rate (inst/s) +host_op_rate 406109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3506224066 # Simulator tick rate (ticks/s) +host_mem_usage 699088 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # B system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s @@ -226,28 +226,28 @@ system.mem_ctrl_0.preEnergy 189750 # En system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) +system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states +system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,14 +427,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -461,14 +461,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -489,14 +489,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,14 +513,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -529,24 +529,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id @@ -565,12 +565,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -583,12 +583,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,25 +603,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -635,14 +641,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 461 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram +system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 461 # Request fanout histogram system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) @@ -652,16 +658,16 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id @@ -688,17 +694,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -721,17 +727,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,17 +757,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -773,17 +779,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 00ce95d37..5eab4cd6f 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 807198 # Simulator instruction rate (inst/s) -host_op_rate 805914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8425106508 # Simulator tick rate (ticks/s) -host_mem_usage 672980 # Number of bytes of host memory used +host_inst_rate 489554 # Simulator instruction rate (inst/s) +host_op_rate 489001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5114816745 # Simulator tick rate (ticks/s) +host_mem_usage 679136 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -514,6 +514,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -527,15 +533,15 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 528 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram system.l2bus.snoop_fanout::total 528 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 279d13e98..82b97827e 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53332000 # Number of ticks simulated -final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53334000 # Number of ticks simulated +final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257745 # Simulator instruction rate (inst/s) -host_op_rate 257613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2475242240 # Simulator tick rate (ticks/s) -host_mem_usage 673312 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 497623 # Simulator instruction rate (inst/s) +host_op_rate 497044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4772617450 # Simulator tick rate (ticks/s) +host_mem_usage 679800 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53236000 # Total gap between requests +system.mem_ctrl.totGap 53238000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # B system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage @@ -224,21 +224,21 @@ system.mem_ctrl.readRowHits 295 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135116.75 # Average gap between requests +system.mem_ctrl.avgGap 135121.83 # Average gap between requests system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) @@ -255,7 +255,7 @@ system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 53332 # number of cpu cycles simulated +system.cpu.numCycles 53334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -274,7 +274,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles +system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -314,12 +314,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -344,10 +344,10 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles @@ -368,10 +368,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency @@ -392,10 +392,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles @@ -408,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -444,12 +444,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -462,12 +462,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,25 +482,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -514,14 +520,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 468 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram +system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 468 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) @@ -531,13 +537,13 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy @@ -567,17 +573,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -600,17 +606,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,17 +636,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -652,17 +658,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index eeac393c4..29a5c5d19 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212931 # Simulator instruction rate (inst/s) -host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2076955895 # Simulator tick rate (ticks/s) -host_mem_usage 693340 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 284010 # Simulator instruction rate (inst/s) +host_op_rate 512497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2773065846 # Simulator tick rate (ticks/s) +host_mem_usage 698700 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # B system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s @@ -313,14 +313,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -500,6 +500,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -513,14 +519,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 428 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 428 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) @@ -530,13 +536,13 @@ system.l2bus.respLayer0.utilization 1.3 # La system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy @@ -565,15 +571,15 @@ system.l2cache.overall_misses::cpu.data 135 # nu system.l2cache.overall_misses::total 364 # number of overall misses system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles +system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -598,15 +604,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 # system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,15 +634,15 @@ system.l2cache.overall_mshr_misses::cpu.data 135 system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -650,15 +656,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1 system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bc3ca9120..81d1f8ac8 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041221500 # Number of ticks simulated -final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041346500 # Number of ticks simulated +final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1077194 # Simulator instruction rate (inst/s) -host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1748701394 # Simulator tick rate (ticks/s) -host_mem_usage 444972 # Number of bytes of host memory used -host_seconds 84.09 # Real time elapsed on the host +host_inst_rate 870528 # Simulator instruction rate (inst/s) +host_op_rate 874854 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1413203999 # Simulator tick rate (ticks/s) +host_mem_usage 449664 # Number of bytes of host memory used +host_seconds 104.05 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,13 +22,13 @@ system.physmem.num_reads::cpu.inst 577 # Nu system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082443 # number of cpu cycles simulated +system.cpu.numCycles 294082693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy @@ -586,6 +586,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution @@ -601,14 +607,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index b23c645a0..053bb8ee0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107049000 # Number of ticks simulated -final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 107711000 # Number of ticks simulated +final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93620 # Simulator instruction rate (inst/s) -host_op_rate 93620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10161795 # Simulator tick rate (ticks/s) -host_mem_usage 304708 # Number of bytes of host memory used -host_seconds 10.53 # Real time elapsed on the host -sim_insts 986230 # Number of instructions simulated -sim_ops 986230 # Number of ops (including micro ops) simulated +host_inst_rate 152784 # Simulator instruction rate (inst/s) +host_op_rate 152784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16568657 # Simulator tick rate (ticks/s) +host_mem_usage 311444 # Number of bytes of host memory used +host_seconds 6.50 # Real time elapsed on the host +sim_insts 993230 # Number of instructions simulated +sim_ops 993230 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107021000 # Total gap between requests +system.physmem.totGap 107683000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,9 +120,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -216,446 +216,446 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation -system.physmem.totQLat 6009250 # Total ticks spent queuing -system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation +system.physmem.totQLat 6590000 # Total ticks spent queuing +system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.11 # Data bus utilization in percentage -system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.09 # Data bus utilization in percentage +system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 511 # Number of row buffer hits during reads +system.physmem.readRowHits 510 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160692.19 # Average gap between requests -system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 161686.19 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ) -system.physmem_0.averagePower 748.690472 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states +system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.440907 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ) -system.physmem_1.averagePower 730.471639 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states +system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.430757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81022 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81565 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 214099 # number of cpu cycles simulated +system.cpu0.numCycles 215423 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued -system.cpu0.iq.rate 1.801713 # Inst issue rate +system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued +system.cpu0.iq.rate 1.803452 # Inst issue rate system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ +system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed +system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73033 # number of nop insts executed -system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76355 # Number of branches executed -system.cpu0.iew.exec_stores 74340 # Number of stores executed -system.cpu0.iew.exec_rate 1.796991 # Inst execution rate -system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227714 # num instructions producing a value -system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value +system.cpu0.iew.exec_nop 73578 # number of nop insts executed +system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76909 # Number of branches executed +system.cpu0.iew.exec_stores 74891 # Number of stores executed +system.cpu0.iew.exec_rate 1.798759 # Inst execution rate +system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229361 # num instructions producing a value +system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449946 # Number of instructions committed -system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453252 # Number of instructions committed +system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219688 # Number of memory references committed -system.cpu0.commit.loads 146121 # Number of loads committed +system.cpu0.commit.refs 221341 # Number of memory references committed +system.cpu0.commit.loads 147223 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75454 # Number of branches committed +system.cpu0.commit.branches 76005 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303394 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305598 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 646481 # The number of ROB reads -system.cpu0.rob.rob_writes 928572 # The number of ROB writes +system.cpu0.rob.rob_reads 651013 # The number of ROB reads +system.cpu0.rob.rob_writes 935136 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377676 # Number of Instructions Simulated -system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688304 # number of integer regfile reads -system.cpu0.int_regfile_writes 310378 # number of integer regfile writes +system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 380431 # Number of Instructions Simulated +system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693268 # number of integer regfile reads +system.cpu0.int_regfile_writes 312587 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits -system.cpu0.dcache.overall_hits::total 148294 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits +system.cpu0.dcache.overall_hits::total 149410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses -system.cpu0.dcache.overall_misses::total 1118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses +system.cpu0.dcache.overall_misses::total 1102 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -666,68 +666,68 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses @@ -743,12 +743,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 784 # system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses system.cpu0.icache.overall_misses::total 784 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses @@ -761,12 +761,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -787,399 +787,399 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 50039 # Number of BP lookups -system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits +system.cpu1.branchPred.lookups 53924 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 161348 # number of cpu cycles simulated +system.cpu1.numCycles 162664 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued -system.cpu1.iq.rate 1.332331 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued +system.cpu1.iq.rate 1.453419 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 34741 # number of nop insts executed -system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed -system.cpu1.iew.exec_branches 44094 # Number of branches executed -system.cpu1.iew.exec_stores 32748 # Number of stores executed -system.cpu1.iew.exec_rate 1.326090 # Inst execution rate -system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 120431 # num instructions producing a value -system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value +system.cpu1.iew.exec_nop 38619 # number of nop insts executed +system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed +system.cpu1.iew.exec_branches 48027 # Number of branches executed +system.cpu1.iew.exec_stores 37584 # Number of stores executed +system.cpu1.iew.exec_rate 1.447253 # Inst execution rate +system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 134020 # num instructions producing a value +system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 240471 # Number of instructions committed -system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 265858 # Number of instructions committed +system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 100469 # Number of memory references committed -system.cpu1.commit.loads 68518 # Number of loads committed -system.cpu1.commit.membars 5139 # Number of memory barriers committed -system.cpu1.commit.branches 43053 # Number of branches committed +system.cpu1.commit.refs 114070 # Number of memory references committed +system.cpu1.commit.loads 77284 # Number of loads committed +system.cpu1.commit.membars 4232 # Number of memory barriers committed +system.cpu1.commit.branches 46981 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 165641 # Number of committed integer instructions. +system.cpu1.commit.int_insts 183171 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 405414 # The number of ROB reads -system.cpu1.rob.rob_writes 511356 # The number of ROB writes -system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 431808 # The number of ROB reads +system.cpu1.rob.rob_writes 561746 # The number of ROB writes +system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 201492 # Number of Instructions Simulated -system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 368266 # number of integer regfile reads -system.cpu1.int_regfile_writes 172947 # number of integer regfile writes +system.cpu1.committedInsts 223857 # Number of Instructions Simulated +system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 409049 # number of integer regfile reads +system.cpu1.int_regfile_writes 191377 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 73089 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 73089 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 73089 # number of overall hits -system.cpu1.dcache.overall_hits::total 73089 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 504 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 504 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses -system.cpu1.dcache.overall_misses::total 664 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9769000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9769000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3369500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3369500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 693500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 693500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13138500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13138500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13138500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13138500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41873 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41873 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 31880 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 31880 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 73753 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 73753 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 73753 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 73753 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012036 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.012036 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005019 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005019 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.788732 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.009003 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.009003 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.009003 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency +system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits +system.cpu1.dcache.overall_hits::total 81866 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses +system.cpu1.dcache.overall_misses::total 648 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,106 +1188,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits -system.cpu1.icache.overall_hits::total 21349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses -system.cpu1.icache.overall_misses::total 579 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits +system.cpu1.icache.overall_hits::total 19439 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses +system.cpu1.icache.overall_misses::total 581 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1296,409 +1296,409 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 42880 # Number of BP lookups -system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits +system.cpu2.branchPred.lookups 55489 # Number of BP lookups +system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160976 # number of cpu cycles simulated +system.cpu2.numCycles 162291 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued -system.cpu2.iq.rate 1.076160 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued +system.cpu2.iq.rate 1.508309 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 27525 # number of nop insts executed -system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed -system.cpu2.iew.exec_branches 36863 # Number of branches executed -system.cpu2.iew.exec_stores 22775 # Number of stores executed -system.cpu2.iew.exec_rate 1.069917 # Inst execution rate -system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 93200 # num instructions producing a value -system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value +system.cpu2.iew.exec_nop 40321 # number of nop insts executed +system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed +system.cpu2.iew.exec_branches 49723 # Number of branches executed +system.cpu2.iew.exec_stores 39200 # Number of stores executed +system.cpu2.iew.exec_rate 1.501993 # Inst execution rate +system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 138958 # num instructions producing a value +system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 191691 # Number of instructions committed -system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 275802 # Number of instructions committed +system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 73311 # Number of memory references committed -system.cpu2.commit.loads 51335 # Number of loads committed -system.cpu2.commit.membars 7910 # Number of memory barriers committed -system.cpu2.commit.branches 35845 # Number of branches committed +system.cpu2.commit.refs 118948 # Number of memory references committed +system.cpu2.commit.loads 80570 # Number of loads committed +system.cpu2.commit.membars 4324 # Number of memory barriers committed +system.cpu2.commit.branches 48669 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 131277 # Number of committed integer instructions. +system.cpu2.commit.int_insts 189737 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 360642 # The number of ROB reads -system.cpu2.rob.rob_writes 413593 # The number of ROB writes -system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 445356 # The number of ROB reads +system.cpu2.rob.rob_writes 582010 # The number of ROB writes +system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 157149 # Number of Instructions Simulated -system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 286558 # number of integer regfile reads -system.cpu2.int_regfile_writes 135654 # number of integer regfile writes +system.cpu2.committedInsts 232019 # Number of Instructions Simulated +system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 423842 # number of integer regfile reads +system.cpu2.int_regfile_writes 197927 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads +system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits -system.cpu2.dcache.overall_hits::total 55890 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses -system.cpu2.dcache.overall_misses::total 639 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 56529 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013950 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.013950 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007122 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.732394 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011304 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.011304 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011304 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.011304 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits +system.cpu2.dcache.overall_hits::total 85153 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses +system.cpu2.dcache.overall_misses::total 686 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,517 +1707,517 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 364 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 364 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 172 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3514000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3514000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3514000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3514000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004968 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004968 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004702 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004702 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.732394 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits -system.cpu2.icache.overall_hits::total 27109 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses -system.cpu2.icache.overall_misses::total 571 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked +system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits +system.cpu2.icache.overall_hits::total 19454 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses +system.cpu2.icache.overall_misses::total 573 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 58611 # Number of BP lookups -system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits +system.cpu3.branchPred.lookups 42820 # Number of BP lookups +system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160611 # number of cpu cycles simulated +system.cpu3.numCycles 161928 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle -system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued -system.cpu3.iq.rate 1.629365 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued +system.cpu3.iq.rate 1.068166 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43196 # number of nop insts executed -system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed -system.cpu3.iew.exec_branches 52784 # Number of branches executed -system.cpu3.iew.exec_stores 43135 # Number of stores executed -system.cpu3.iew.exec_rate 1.623027 # Inst execution rate -system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 149829 # num instructions producing a value -system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value +system.cpu3.iew.exec_nop 27464 # number of nop insts executed +system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed +system.cpu3.iew.exec_branches 36861 # Number of branches executed +system.cpu3.iew.exec_stores 22696 # Number of stores executed +system.cpu3.iew.exec_rate 1.062126 # Inst execution rate +system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 92998 # num instructions producing a value +system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 295833 # Number of instructions committed -system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 191557 # Number of instructions committed +system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 129866 # Number of memory references committed -system.cpu3.commit.loads 87548 # Number of loads committed -system.cpu3.commit.membars 3423 # Number of memory barriers committed -system.cpu3.commit.branches 51706 # Number of branches committed +system.cpu3.commit.refs 73159 # Number of memory references committed +system.cpu3.commit.loads 51261 # Number of loads committed +system.cpu3.commit.membars 7996 # Number of memory barriers committed +system.cpu3.commit.branches 35851 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 203693 # Number of committed integer instructions. +system.cpu3.commit.int_insts 131131 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 464044 # The number of ROB reads -system.cpu3.rob.rob_writes 620441 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 361140 # The number of ROB reads +system.cpu3.rob.rob_writes 412450 # The number of ROB writes +system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249913 # Number of Instructions Simulated -system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 456401 # number of integer regfile reads -system.cpu3.int_regfile_writes 212686 # number of integer regfile writes +system.cpu3.committedInsts 156923 # Number of Instructions Simulated +system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 285937 # number of integer regfile reads +system.cpu3.int_regfile_writes 135307 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads +system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits -system.cpu3.dcache.overall_hits::total 92057 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 674 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 674 # number of overall misses -system.cpu3.dcache.overall_misses::total 674 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits +system.cpu3.dcache.overall_hits::total 55817 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses +system.cpu3.dcache.overall_misses::total 617 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2226,106 +2226,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 369 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 48 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 417 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 417 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 417 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 18767 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 18767 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 17696 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17696 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17696 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17696 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17696 # number of overall hits -system.cpu3.icache.overall_hits::total 17696 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 573 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 573 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 573 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 573 # number of overall misses -system.cpu3.icache.overall_misses::total 573 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18269 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 18269 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 18269 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031365 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.031365 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031365 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.031365 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031365 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.031365 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits +system.cpu3.icache.overall_hits::total 27370 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses +system.cpu3.icache.overall_misses::total 571 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,77 +2334,77 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # 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average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use -system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use +system.l2c.tags.total_refs 2348 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25618 # Number of tag accesses -system.l2c.tags.data_accesses 25618 # Number of data accesses +system.l2c.tags.tag_accesses 25610 # Number of tag accesses +system.l2c.tags.data_accesses 25610 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 491 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits @@ -2413,36 +2413,36 @@ system.l2c.ReadSharedReq_hits::cpu3.data 11 # nu system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 490 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1670 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 246 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 410 # number of overall hits +system.l2c.overall_hits::cpu1.inst 409 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 491 # number of overall hits +system.l2c.overall_hits::cpu2.inst 490 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 491 # number of overall hits +system.l2c.overall_hits::cpu3.inst 493 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits system.l2c.overall_hits::total 1670 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 7 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses @@ -2451,62 +2451,62 @@ system.l2c.ReadSharedReq_misses::cpu3.data 1 # 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number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2544,16 +2544,16 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 89 # Transaction distribution -system.membus.trans_dist::ReadExReq 161 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 87 # Transaction distribution +system.membus.trans_dist::ReadExReq 162 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 233 # Total snoops (count) -system.membus.snoop_fanout::samples 988 # Request fanout histogram +system.membus.snoops 231 # Total snoops (count) +system.membus.snoop_fanout::samples 984 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 988 # Request fanout histogram -system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 984 # Request fanout histogram +system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution +system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) @@ -2839,41 +2845,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1026 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoops 1019 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 6ed919c46..9e7ba2833 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1750110 # Simulator instruction rate (inst/s) -host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 226603798 # Simulator tick rate (ticks/s) -host_mem_usage 303668 # Number of bytes of host memory used +host_inst_rate 1726221 # Simulator instruction rate (inst/s) +host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223510854 # Simulator tick rate (ticks/s) +host_mem_usage 306324 # Number of bytes of host memory used host_seconds 0.39 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated @@ -743,9 +743,9 @@ system.cpu3.icache.cache_copies 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use -system.l2c.tags.total_refs 2271 # Total number of references to valid blocks. +system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor @@ -770,8 +770,8 @@ system.l2c.tags.occ_task_id_blocks::1024 421 # Oc system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23864 # Number of tag accesses -system.l2c.tags.data_accesses 23864 # Number of data accesses +system.l2c.tags.tag_accesses 19424 # Number of tag accesses +system.l2c.tags.data_accesses 19424 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits @@ -950,24 +950,30 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) @@ -979,21 +985,21 @@ system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 89934d478..f34aec4c9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000260 # Number of seconds simulated -sim_ticks 260073500 # Number of ticks simulated -final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000261 # Number of seconds simulated +sim_ticks 260712500 # Number of ticks simulated +final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1077387 # Simulator instruction rate (inst/s) -host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 425087977 # Simulator tick rate (ticks/s) -host_mem_usage 303432 # Number of bytes of host memory used -host_seconds 0.61 # Real time elapsed on the host -sim_insts 659129 # Number of instructions simulated -sim_ops 659129 # Number of ops (including micro ops) simulated +host_inst_rate 1018019 # Simulator instruction rate (inst/s) +host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 401917302 # Simulator tick rate (ticks/s) +host_mem_usage 306320 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host +sim_insts 660333 # Number of instructions simulated +sim_ops 660333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -36,164 +36,164 @@ system.physmem.num_reads::cpu2.data 22 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 520147 # number of cpu cycles simulated +system.cpu0.numCycles 521425 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157434 # Number of instructions committed -system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses +system.cpu0.committedInsts 157788 # Number of instructions committed +system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108448 # number of integer instructions +system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108684 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73451 # number of memory refs -system.cpu0.num_load_insts 48627 # Number of load instructions -system.cpu0.num_store_insts 24824 # Number of store instructions +system.cpu0.num_mem_refs 73628 # number of memory refs +system.cpu0.num_load_insts 48745 # Number of load instructions +system.cpu0.num_store_insts 24883 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26707 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction +system.cpu0.Branches 26766 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157496 # Class of executed instruction +system.cpu0.op_class::total 157850 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits -system.cpu0.dcache.overall_hits::total 73037 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits +system.cpu0.dcache.overall_hits::total 73215 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses +system.cpu0.dcache.overall_misses::total 352 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,98 +204,98 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits -system.cpu0.icache.overall_hits::total 157030 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits +system.cpu0.icache.overall_hits::total 157384 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 520147 # number of cpu cycles simulated +system.cpu1.numCycles 521425 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 165571 # Number of instructions committed -system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses +system.cpu1.committedInsts 168182 # Number of instructions committed +system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111555 # number of integer instructions +system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110851 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read -system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written +system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 56707 # number of memory refs -system.cpu1.num_load_insts 41448 # Number of load instructions -system.cpu1.num_store_insts 15259 # Number of store instructions -system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles -system.cpu1.Branches 32668 # Number of branches fetched -system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction -system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction -system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 54346 # number of memory refs +system.cpu1.num_load_insts 41092 # Number of load instructions +system.cpu1.num_store_insts 13254 # Number of store instructions +system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles +system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles +system.cpu1.Branches 34327 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction +system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction +system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 165603 # Class of executed instruction +system.cpu1.op_class::total 168214 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits -system.cpu1.dcache.overall_hits::total 56366 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses -system.cpu1.dcache.overall_misses::total 265 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits +system.cpu1.dcache.overall_hits::total 53996 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses +system.cpu1.dcache.overall_misses::total 271 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits -system.cpu1.icache.overall_hits::total 165238 # number of overall hits +system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits +system.cpu1.icache.overall_hits::total 167849 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 520146 # number of cpu cycles simulated +system.cpu2.numCycles 521424 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 160598 # Number of instructions committed -system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses +system.cpu2.committedInsts 165155 # Number of instructions committed +system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls -system.cpu2.num_int_insts 111601 # number of integer instructions +system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110249 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read -system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written +system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59264 # number of memory refs -system.cpu2.num_load_insts 41473 # Number of load instructions -system.cpu2.num_store_insts 17791 # Number of store instructions -system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles -system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles -system.cpu2.Branches 30158 # Number of branches fetched -system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction -system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction -system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 54956 # number of memory refs +system.cpu2.num_load_insts 40791 # Number of load instructions +system.cpu2.num_store_insts 14165 # Number of store instructions +system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles +system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles +system.cpu2.Branches 33115 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction +system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction +system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 160630 # Class of executed instruction +system.cpu2.op_class::total 165187 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits -system.cpu2.dcache.overall_hits::total 58928 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses -system.cpu2.dcache.overall_misses::total 261 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits +system.cpu2.dcache.overall_hits::total 54608 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses +system.cpu2.dcache.overall_misses::total 269 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 269 # 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mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # 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Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # 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miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,158 +844,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 520146 # number of cpu cycles simulated +system.cpu3.numCycles 521424 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 175526 # Number of instructions committed -system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses +system.cpu3.committedInsts 169208 # Number of instructions committed +system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls -system.cpu3.num_int_insts 107877 # number of integer instructions +system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110441 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read -system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written +system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read +system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 46213 # number of memory refs -system.cpu3.num_load_insts 39592 # Number of load instructions -system.cpu3.num_store_insts 6621 # Number of store instructions -system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles -system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles -system.cpu3.Branches 39491 # Number of branches fetched -system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction -system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction -system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 53219 # number of memory refs +system.cpu3.num_load_insts 40883 # Number of load instructions +system.cpu3.num_store_insts 12336 # Number of store instructions +system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles +system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles +system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles +system.cpu3.Branches 35047 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction +system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction +system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 175558 # Class of executed instruction +system.cpu3.op_class::total 169240 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits -system.cpu3.dcache.overall_hits::total 45837 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses -system.cpu3.dcache.overall_misses::total 287 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits +system.cpu3.dcache.overall_hits::total 52867 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses +system.cpu3.dcache.overall_misses::total 270 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits -system.cpu3.icache.overall_hits::total 175192 # number of overall hits +system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits +system.cpu3.icache.overall_hits::total 168874 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1111,56 +1111,56 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5004500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5004500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5004500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5004500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5004500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5004500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002169 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use +system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19677 # Number of tag accesses -system.l2c.tags.data_accesses 19677 # Number of data accesses +system.l2c.tags.tag_accesses 19669 # Number of tag accesses +system.l2c.tags.data_accesses 19669 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits @@ -1194,10 +1194,10 @@ system.l2c.overall_hits::cpu3.inst 358 # nu system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses @@ -1233,44 +1233,44 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 795500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7472000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14963500 # number of ReadCleanReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) @@ -1308,7 +1308,7 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1344,37 +1344,37 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53033.333333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52619.718310 # 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mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1513,88 +1513,94 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42619.718310 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average ReadCleanReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42518.361582 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::UpgradeReq 271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 914 # Request fanout histogram +system.membus.snoop_fanout::samples 913 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 914 # Request fanout histogram -system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 913 # Request fanout histogram +system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) @@ -1604,41 +1610,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1037 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoops 1034 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 96f88f923..61ea5a710 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1817 +1,1819 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000889 # Number of seconds simulated -sim_ticks 888991000 # Number of ticks simulated -final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 518362500 # Number of ticks simulated +final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 170326912 # Simulator tick rate (ticks/s) -host_mem_usage 278304 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host +host_tick_rate 97254136 # Simulator tick rate (ticks/s) +host_mem_usage 280792 # Number of bytes of host memory used +host_seconds 5.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory -system.physmem.bytes_read::total 628365 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory -system.physmem.bytes_written::total 439804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory +system.physmem.bytes_read::total 656343 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory +system.physmem.bytes_written::total 460429 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99131 # number of read accesses completed -system.cpu0.num_writes 55164 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22535 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks. +system.cpu0.num_reads 99891 # number of read accesses completed +system.cpu0.num_writes 54838 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22327 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits -system.cpu0.l1c.overall_hits::total 9783 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses -system.cpu0.l1c.overall_misses::total 60648 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits +system.cpu0.l1c.overall_hits::total 9862 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses +system.cpu0.l1c.overall_misses::total 60368 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks -system.cpu0.l1c.writebacks::total 9979 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks +system.cpu0.l1c.writebacks::total 9814 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99860 # number of read accesses completed -system.cpu1.num_writes 55211 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22541 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks. +system.cpu1.num_reads 99259 # number of read accesses completed +system.cpu1.num_writes 55194 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22288 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits -system.cpu1.l1c.overall_hits::total 9891 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses -system.cpu1.l1c.overall_misses::total 60508 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2255662665 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits +system.cpu1.l1c.overall_hits::total 9869 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36456 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23797 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses +system.cpu1.l1c.overall_misses::total 60253 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks -system.cpu1.l1c.writebacks::total 9897 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks +system.cpu1.l1c.writebacks::total 9824 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99820 # number of read accesses completed -system.cpu2.num_writes 54950 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22307 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. +system.cpu2.num_reads 99508 # number of read accesses completed +system.cpu2.num_writes 54525 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22121 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits -system.cpu2.l1c.overall_hits::total 9993 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses -system.cpu2.l1c.overall_misses::total 60635 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits +system.cpu2.l1c.overall_hits::total 9936 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36608 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses +system.cpu2.l1c.overall_misses::total 60459 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks -system.cpu2.l1c.writebacks::total 9745 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks +system.cpu2.l1c.writebacks::total 9721 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99181 # number of read accesses completed -system.cpu3.num_writes 54913 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22385 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55096 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22478 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits -system.cpu3.l1c.overall_hits::total 9698 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses -system.cpu3.l1c.overall_misses::total 60513 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8879 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits +system.cpu3.l1c.overall_hits::total 10018 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36721 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses +system.cpu3.l1c.overall_misses::total 60648 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks -system.cpu3.l1c.writebacks::total 9719 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks +system.cpu3.l1c.writebacks::total 10011 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99531 # number of read accesses completed -system.cpu4.num_writes 55217 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22414 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use +system.cpu4.num_reads 98810 # number of read accesses completed +system.cpu4.num_writes 55636 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22565 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits -system.cpu4.l1c.overall_hits::total 9858 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses -system.cpu4.l1c.overall_misses::total 60389 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits +system.cpu4.l1c.overall_hits::total 9864 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60479 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60479 # number of overall misses +system.cpu4.l1c.overall_misses::total 60479 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70343 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70343 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859773 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859773 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859773 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks -system.cpu4.l1c.writebacks::total 9784 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks +system.cpu4.l1c.writebacks::total 10039 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60479 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55296 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22532 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks. +system.cpu5.num_reads 98552 # number of read accesses completed +system.cpu5.num_writes 54926 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22151 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits -system.cpu5.l1c.overall_hits::total 9941 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses -system.cpu5.l1c.overall_misses::total 60368 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9730 # number of overall hits +system.cpu5.l1c.overall_hits::total 9730 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36363 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36363 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23944 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60307 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60307 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60307 # number of overall misses +system.cpu5.l1c.overall_misses::total 60307 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70037 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861073 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861073 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks -system.cpu5.l1c.writebacks::total 9981 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks +system.cpu5.l1c.writebacks::total 9825 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60307 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60307 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99879 # number of read accesses completed -system.cpu6.num_writes 55426 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks. +system.cpu6.num_reads 98949 # number of read accesses completed +system.cpu6.num_writes 55414 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22111 # number of replacements +system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits -system.cpu6.l1c.overall_hits::total 9921 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses -system.cpu6.l1c.overall_misses::total 60654 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337246 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8611 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8611 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9755 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9755 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9755 # number of overall hits +system.cpu6.l1c.overall_hits::total 9755 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36346 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36346 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24035 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24035 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60381 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60381 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60381 # number of overall misses +system.cpu6.l1c.overall_misses::total 60381 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1291646289 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70136 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70136 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860913 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860913 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860913 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks -system.cpu6.l1c.writebacks::total 9808 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks +system.cpu6.l1c.writebacks::total 9648 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60381 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60381 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99237 # number of read accesses completed -system.cpu7.num_writes 54706 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22568 # number of replacements -system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks. +system.cpu7.num_reads 99388 # number of read accesses completed +system.cpu7.num_writes 55153 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22255 # number of replacements +system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits -system.cpu7.l1c.overall_hits::total 9873 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses -system.cpu7.l1c.overall_misses::total 60373 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338136 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338136 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8702 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8702 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1125 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1125 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9827 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9827 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9827 # number of overall hits +system.cpu7.l1c.overall_hits::total 9827 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36623 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36623 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23879 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23879 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60502 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60502 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60502 # number of overall misses +system.cpu7.l1c.overall_misses::total 60502 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1300684949 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1300684949 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70329 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70329 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860271 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860271 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860271 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860271 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 764751 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61551 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.424672 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks -system.cpu7.l1c.writebacks::total 9950 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9698 # number of writebacks +system.cpu7.l1c.writebacks::total 9698 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60502 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13238 # number of replacements -system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use -system.l2c.tags.total_refs 163749 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks. +system.l2c.tags.replacements 14059 # number of replacements +system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use +system.l2c.tags.total_refs 163279 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14835 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 731.907933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.714754 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006353 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765123 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2093442 # Number of tag accesses -system.l2c.tags.data_accesses 2093442 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77141 # number of Writeback hits -system.l2c.Writeback_hits::total 77141 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 237 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2068 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2060 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16581 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4635 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4534 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4676 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4617 # number of ReadExReq misses +system.l2c.tags.occ_blocks::writebacks 728.191655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.576246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.765492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.413353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.547486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.173407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.531253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.038544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.596181 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.711125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007240 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007005 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006874 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768392 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 637 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2098126 # Number of tag accesses +system.l2c.tags.data_accesses 2098126 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77297 # number of Writeback hits +system.l2c.Writeback_hits::total 77297 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 246 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 270 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 282 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 269 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 297 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2204 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1720 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1708 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14127 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10721 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10733 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 11023 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10756 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10769 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10556 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10900 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86354 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12676 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12773 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12656 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2011 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2018 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16379 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4713 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4655 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4594 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu4 4660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4704 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4691 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 682 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 701 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 683 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 732 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 682 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 708 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 684 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5549 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5317 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5211 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5300 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5392 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5375 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 61770000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 60743499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 60997499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 60764000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 494388493 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 252681459 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 247510963 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 255306957 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 251987957 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 254124963 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 254900472 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 257627958 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 256511954 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2030652683 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 41112446 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 40920945 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 42356442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 41376937 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 44597922 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 42076925 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 42377442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 41033442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 335852501 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 293793905 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 288431908 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 297663399 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 293364894 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 298722885 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 296977397 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 300005400 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 297545396 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2366505184 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 293793905 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 288431908 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 297663399 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 293364894 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2319 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18688 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6380 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6433 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6391 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6443 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6547 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6463 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6421 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17851 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17926 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17890 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17949 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17814 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143292 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17826 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17851 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17926 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17890 # 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miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.887254 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.726489 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.713342 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.726877 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.722422 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.723266 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.714984 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.727835 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.730572 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723218 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.059584 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.058895 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.060645 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.059211 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.063947 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.059320 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.061640 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.060037 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.060408 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.298272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.291916 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.298855 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.295660 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.301397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.301521 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.301729 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.298321 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.298272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.291916 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.295660 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.301397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.297218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.301521 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.301729 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.298321 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29972.358121 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30263.732620 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30704.012422 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29711.153003 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29288.762447 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29602.095029 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29495.889265 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29497.087379 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29816.566733 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54515.956634 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54589.978606 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54599.434773 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54578.288282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54533.253863 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54454.277291 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54767.848214 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54681.721168 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54590.372681 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 60282.178886 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 60444.527326 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 60422.884451 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 60581.166911 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 60926.122951 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61696.370968 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 59855.144068 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 59990.412281 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 60524.869526 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55255.577393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55350.586836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55358.638460 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55351.866792 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55401.128524 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55375.237181 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55433.370288 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55357.282977 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55360.731373 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55255.577393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55350.586836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55358.638460 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55351.866792 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55401.128524 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55375.237181 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55433.370288 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55357.282977 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55360.731373 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 8992 # number of cycles access was blocked +system.l2c.ReadExReq_misses::cpu5 4574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4699 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4645 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37147 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 745 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 703 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 745 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 740 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 719 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 741 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 779 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5907 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5352 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5334 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5379 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5434 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5424 # number of demand (read+write) misses +system.l2c.demand_misses::total 43054 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5458 # number of overall misses +system.l2c.overall_misses::cpu1 5358 # number of overall misses +system.l2c.overall_misses::cpu2 5352 # number of overall misses +system.l2c.overall_misses::cpu3 5334 # number of overall misses +system.l2c.overall_misses::cpu4 5379 # number of overall misses +system.l2c.overall_misses::cpu5 5315 # number of overall misses +system.l2c.overall_misses::cpu6 5434 # number of overall misses +system.l2c.overall_misses::cpu7 5424 # number of overall misses +system.l2c.overall_misses::total 43054 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 60264491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 62631489 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 64255988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 63421482 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 62636494 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 62720987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 60083486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 62493486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 498507903 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 264922404 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 260661407 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 257895914 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 258059392 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 261142926 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 256126416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 263147923 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 259849424 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2081805806 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 46156062 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 44483916 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 46780409 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 45792918 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 45003906 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 46499399 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 45597417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 48662406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 368976433 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 311078466 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 305145323 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 304676323 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 303852310 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 306146832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 302625815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 308745340 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 308511830 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2450782239 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 311078466 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 305145323 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 304676323 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 303852310 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 306146832 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 302625815 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 308745340 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 308511830 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2450782239 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77297 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77297 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2224 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2294 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2420 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2374 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2323 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2315 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18583 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6433 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6493 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6492 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51274 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11466 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11436 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11641 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11763 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11475 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11510 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11679 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92261 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17799 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17871 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18080 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143535 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17799 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17871 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18080 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143535 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.889388 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.883173 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.888430 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.880792 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.875592 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.880153 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.882018 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.871706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881397 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.732629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.731573 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.721309 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724149 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717696 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.719069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.723814 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.724480 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.064975 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.061473 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063998 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.062909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.062658 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.064379 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065096 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.066701 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064025 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.304933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.301028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296872 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.294582 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.299366 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.305573 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.300000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.299955 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.304933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.301028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296872 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.294582 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.299366 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.305573 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.300000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.299955 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30467.386754 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30913.864265 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29886.506047 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30330.694405 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30794.736480 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30285.363110 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29877.417205 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30968.030723 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30435.796019 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 56210.991725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55996.005800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55979.143477 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 56173.137135 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 56039.254506 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55996.155662 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 56000.834858 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55941.748977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56042.366974 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61954.445638 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 63277.263158 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62792.495302 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61882.321622 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 62592.358832 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62752.225371 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62037.302041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62467.786906 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 62464.268326 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 19361 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1204 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3488 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.468439 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.550745 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6188 # number of writebacks -system.l2c.writebacks::total 6188 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6515 # number of writebacks +system.l2c.writebacks::total 6515 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 5 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 26 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 12 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1198 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1198 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2057 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2093 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2098 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2109 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2051 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2068 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2059 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16579 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4532 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4674 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4616 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4656 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4680 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4700 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4687 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37172 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 679 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 720 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5503 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5305 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5205 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5374 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5376 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5353 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5402 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5365 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42675 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5305 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5205 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5374 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5295 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5376 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5353 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5402 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5365 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42675 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9717 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9883 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78862 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5354 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5486 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5463 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5457 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5585 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43772 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15071 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15230 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15346 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15445 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15427 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122634 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89873000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 90484998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 92033997 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92268499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 92811998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 90292999 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 90927999 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 90564000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 729257490 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 206241460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 202149464 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 208464458 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 205784957 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 207399964 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 208084972 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 210466959 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 209572454 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1658164688 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 34242946 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 34066945 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 35309442 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 34442937 # 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number of overall MSHR hits +system.l2c.overall_mshr_hits::total 103 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1301 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1301 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1977 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2026 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2150 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2090 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2069 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2011 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2017 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4709 # 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number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 731 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 730 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 770 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5838 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5447 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5339 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5323 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5425 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5409 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 437879200 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3531476593 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 247492955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 251693437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 254031943 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 244392771 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 255999435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 255282926 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253764437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 253334431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2015992335 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 689037659 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 694515799 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 699146134 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 682435479 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687551804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 703842791 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 699725631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 691213631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5547468928 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880276 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877186 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.899441 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.893526 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.898977 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.884433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.877759 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885591 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.887147 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725235 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713027 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726566 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.722266 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.722645 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.714831 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.727216 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.729949 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722713 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059235 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.058547 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060559 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.058864 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062899 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.058537 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061118 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059908 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297818 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297818 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 43969.178082 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 43988.817696 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 43972.287148 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 43979.265491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44007.585586 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44023.890297 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 43969.051741 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 43984.458475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78861 # Transaction distribution -system.membus.trans_dist::ReadResp 84355 # Transaction distribution -system.membus.trans_dist::WriteReq 43772 # Transaction distribution -system.membus.trans_dist::WriteResp 43770 # Transaction distribution -system.membus.trans_dist::Writeback 6188 # Transaction distribution -system.membus.trans_dist::CleanEvict 1234 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution -system.membus.trans_dist::ReadExReq 49401 # Transaction distribution -system.membus.trans_dist::ReadExResp 3090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57121 # Total snoops (count) -system.membus.snoop_fanout::samples 253876 # Request fanout histogram +system.membus.trans_dist::ReadReq 78487 # Transaction distribution +system.membus.trans_dist::ReadResp 84311 # Transaction distribution +system.membus.trans_dist::WriteReq 43469 # Transaction distribution +system.membus.trans_dist::WriteResp 43465 # Transaction distribution +system.membus.trans_dist::Writeback 6515 # Transaction distribution +system.membus.trans_dist::CleanEvict 1324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution +system.membus.trans_dist::ReadExReq 49356 # Transaction distribution +system.membus.trans_dist::ReadExResp 3201 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57043 # Total snoops (count) +system.membus.snoop_fanout::samples 255514 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253876 # Request fanout histogram -system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 35.7 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_fanout::total 255514 # Request fanout histogram +system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 59.8 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 335326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index d439f20bd..76540bca6 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1806 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000517 # Number of seconds simulated -sim_ticks 516502000 # Number of ticks simulated -final_tick 516502000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 517786000 # Number of ticks simulated +final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 87177041 # Simulator tick rate (ticks/s) -host_mem_usage 277532 # Number of bytes of host memory used -host_seconds 5.92 # Real time elapsed on the host +host_tick_rate 99723528 # Simulator tick rate (ticks/s) +host_mem_usage 280036 # Number of bytes of host memory used +host_seconds 5.19 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77818 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80958 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 77616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77018 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78103 # Number of bytes read from this memory -system.physmem.bytes_read::total 628157 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 397760 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5375 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5446 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5475 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5563 # Number of bytes written to this memory -system.physmem.bytes_written::total 441591 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10975 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10902 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10819 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5520 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5375 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5475 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5563 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 150663502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 156742859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 150272409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 157916136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 149699324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 149114621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 150551208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 151215291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1216175349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 770103504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10813124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10687277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10406542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10553686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10485923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10544006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10600153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10770529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 854964744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 770103504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 161476625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 167430136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 160678952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 168469822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 160185246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 159658627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 161151360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 161985820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2071140092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory +system.physmem.bytes_read::total 656710 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory +system.physmem.bytes_written::total 459030 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99458 # number of read accesses completed -system.cpu0.num_writes 55230 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22190 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.694293 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13468 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22585 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596325 # Average number of references to valid blocks. +system.cpu0.num_reads 99592 # number of read accesses completed +system.cpu0.num_writes 55369 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22465 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.694293 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337088 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337088 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1212 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1212 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits -system.cpu0.l1c.overall_hits::total 9897 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36327 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36327 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23903 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60230 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60230 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60230 # number of overall misses -system.cpu0.l1c.overall_misses::total 60230 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1261783446 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1261783446 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70127 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70127 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70127 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70127 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858870 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858870 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858870 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858870 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 738586 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits +system.cpu0.l1c.overall_hits::total 9899 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses +system.cpu0.l1c.overall_misses::total 60570 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60679 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.172020 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60230 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60230 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks +system.cpu0.l1c.writebacks::total 9922 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99343 # number of read accesses completed -system.cpu1.num_writes 54840 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22376 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.102021 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13319 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.585142 # Average number of references to valid blocks. +system.cpu1.num_reads 99505 # number of read accesses completed +system.cpu1.num_writes 55135 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22526 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.102021 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.767777 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.767777 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337670 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337670 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8618 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8618 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1175 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9793 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9793 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9793 # number of overall hits -system.cpu1.l1c.overall_hits::total 9793 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36716 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36716 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23707 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23707 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60423 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60423 # number of overall misses -system.cpu1.l1c.overall_misses::total 60423 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1266259413 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1266259413 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70216 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70216 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70216 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70216 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860530 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860530 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860530 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860530 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 733404 # number of cycles access was blocked +system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits +system.cpu1.l1c.overall_hits::total 9854 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses +system.cpu1.l1c.overall_misses::total 60684 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60457 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.131002 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9757 # number of writebacks -system.cpu1.l1c.writebacks::total 9757 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60423 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks +system.cpu1.l1c.writebacks::total 9855 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99555 # number of read accesses completed -system.cpu2.num_writes 54722 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22333 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.011664 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13583 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22742 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.597265 # Average number of references to valid blocks. +system.cpu2.num_reads 99747 # number of read accesses completed +system.cpu2.num_writes 54917 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22440 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.011664 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337922 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337922 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9967 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9967 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9967 # number of overall hits -system.cpu2.l1c.overall_hits::total 9967 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36445 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36445 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23901 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23901 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses -system.cpu2.l1c.overall_misses::total 60346 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1269216347 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1269216347 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70313 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70313 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70313 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70313 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858248 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858248 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858248 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858248 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 742378 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits +system.cpu2.l1c.overall_hits::total 9763 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses +system.cpu2.l1c.overall_misses::total 60345 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60996 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.170929 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9726 # number of writebacks -system.cpu2.l1c.writebacks::total 9726 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks +system.cpu2.l1c.writebacks::total 9836 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99759 # number of read accesses completed -system.cpu3.num_writes 54933 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22211 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.604025 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13361 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22604 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.591090 # Average number of references to valid blocks. +system.cpu3.num_reads 98987 # number of read accesses completed +system.cpu3.num_writes 55311 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22430 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.604025 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336889 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336889 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8685 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1067 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9752 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9752 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9752 # number of overall hits -system.cpu3.l1c.overall_hits::total 9752 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36549 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36549 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23764 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23764 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60313 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60313 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60313 # number of overall misses -system.cpu3.l1c.overall_misses::total 60313 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1264129060 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1264129060 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70065 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70065 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70065 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70065 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860815 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860815 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860815 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860815 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 744732 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits +system.cpu3.l1c.overall_hits::total 9734 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses +system.cpu3.l1c.overall_misses::total 60391 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70125 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70125 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70125 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70125 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861191 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861191 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861191 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861191 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61238 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.161272 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu3.l1c.writebacks::total 9780 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60313 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60313 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 10012 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks +system.cpu3.l1c.writebacks::total 9891 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 55127 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22421 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.948683 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13931 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22818 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.610527 # Average number of references to valid blocks. +system.cpu4.num_writes 54901 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22108 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.948683 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339409 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339409 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 9015 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 9015 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1217 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1217 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10232 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10232 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10232 # number of overall hits -system.cpu4.l1c.overall_hits::total 10232 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36534 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36534 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23911 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23911 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60445 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60445 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60445 # number of overall misses -system.cpu4.l1c.overall_misses::total 60445 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1264592958 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1264592958 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70677 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70677 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70677 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70677 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855229 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855229 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855229 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855229 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 737141 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits +system.cpu4.l1c.overall_hits::total 9941 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses +system.cpu4.l1c.overall_misses::total 60419 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60832 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.117652 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9985 # number of writebacks -system.cpu4.l1c.writebacks::total 9985 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60445 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks +system.cpu4.l1c.writebacks::total 9736 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99788 # number of read accesses completed -system.cpu5.num_writes 55138 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22475 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.735284 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13651 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.596817 # Average number of references to valid blocks. +system.cpu5.num_reads 99420 # number of read accesses completed +system.cpu5.num_writes 55050 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22127 # number of replacements +system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.735284 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 340255 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 340255 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8878 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8878 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1131 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10009 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10009 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10009 # number of overall hits -system.cpu5.l1c.overall_hits::total 10009 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36858 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36858 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23929 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23929 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60787 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60787 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60787 # number of overall misses -system.cpu5.l1c.overall_misses::total 60787 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1271570393 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1271570393 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70796 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70796 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70796 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70796 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858622 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858622 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858622 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858622 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 731203 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits +system.cpu5.l1c.overall_hits::total 10048 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses +system.cpu5.l1c.overall_misses::total 60404 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60676 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.050943 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9872 # number of writebacks -system.cpu5.l1c.writebacks::total 9872 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60787 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60787 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks +system.cpu5.l1c.writebacks::total 9761 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99577 # number of read accesses completed -system.cpu6.num_writes 55267 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22184 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.209079 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13575 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.601382 # Average number of references to valid blocks. +system.cpu6.num_reads 99130 # number of read accesses completed +system.cpu6.num_writes 55082 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22211 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.209079 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337224 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337224 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8787 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8787 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1092 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9879 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9879 # number of overall hits -system.cpu6.l1c.overall_hits::total 9879 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36436 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36436 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23858 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23858 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60294 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60294 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60294 # number of overall misses -system.cpu6.l1c.overall_misses::total 60294 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1268942964 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1268942964 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70173 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70173 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70173 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70173 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859219 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859219 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859219 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859219 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 742965 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits +system.cpu6.l1c.overall_hits::total 9828 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses +system.cpu6.l1c.overall_misses::total 60544 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61020 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.175762 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9883 # number of writebacks -system.cpu6.l1c.writebacks::total 9883 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60294 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks +system.cpu6.l1c.writebacks::total 9790 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99427 # number of read accesses completed -system.cpu7.num_writes 55134 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22242 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.816785 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13453 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22633 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594398 # Average number of references to valid blocks. +system.cpu7.num_reads 99282 # number of read accesses completed +system.cpu7.num_writes 55000 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22412 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.816785 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338054 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338054 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8636 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8636 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9784 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9784 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9784 # number of overall hits -system.cpu7.l1c.overall_hits::total 9784 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36700 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36700 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23832 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60532 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60532 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60532 # number of overall misses -system.cpu7.l1c.overall_misses::total 60532 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1273616748 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1273616748 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70316 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70316 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70316 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70316 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860857 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860857 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860857 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860857 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 739183 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits +system.cpu7.l1c.overall_hits::total 9727 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses +system.cpu7.l1c.overall_misses::total 60557 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 60836 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.150421 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9689 # number of writebacks -system.cpu7.l1c.writebacks::total 9689 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60532 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60532 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks +system.cpu7.l1c.writebacks::total 9927 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13635 # number of replacements -system.l2c.tags.tagsinuse 787.795797 # Cycle average of tags in use -system.l2c.tags.total_refs 163881 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.364052 # Average number of references to valid blocks. +system.l2c.tags.replacements 14184 # number of replacements +system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use +system.l2c.tags.total_refs 165124 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 732.377461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.931961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.975655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.944636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.398268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.695089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.188919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.047720 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.236089 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.715212 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006812 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006782 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006538 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007066 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769332 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 786 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2092959 # Number of tag accesses -system.l2c.tags.data_accesses 2092959 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77190 # number of Writeback hits -system.l2c.Writeback_hits::total 77190 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 242 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 286 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 254 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 287 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2215 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1812 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1725 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1792 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1760 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1773 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14082 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10725 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10956 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10775 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10922 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10805 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10917 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10735 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10921 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86756 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12482 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12701 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12597 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12677 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12694 # number of demand (read+write) hits -system.l2c.demand_hits::total 100838 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12482 # number of overall hits -system.l2c.overall_hits::cpu1 12701 # number of overall hits -system.l2c.overall_hits::cpu2 12587 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12597 # number of overall hits -system.l2c.overall_hits::cpu5 12677 # number of overall hits -system.l2c.overall_hits::cpu6 12453 # number of overall hits -system.l2c.overall_hits::cpu7 12694 # number of overall hits -system.l2c.overall_hits::total 100838 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2065 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2004 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2022 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2044 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2054 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2029 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2097 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2076 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16391 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4632 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4551 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4586 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4720 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36848 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 688 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 732 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 715 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5548 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5320 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5348 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5257 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5212 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5317 # number of demand (read+write) misses -system.l2c.demand_misses::total 42396 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5320 # number of overall misses -system.l2c.overall_misses::cpu1 5255 # number of overall misses -system.l2c.overall_misses::cpu2 5290 # number of overall misses -system.l2c.overall_misses::cpu3 5348 # number of overall misses -system.l2c.overall_misses::cpu4 5257 # number of overall misses -system.l2c.overall_misses::cpu5 5212 # number of overall misses -system.l2c.overall_misses::cpu6 5397 # number of overall misses -system.l2c.overall_misses::cpu7 5317 # number of overall misses -system.l2c.overall_misses::total 42396 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 61352981 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 61176995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 58729489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 63986497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 59053489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 58462992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 64338488 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 61927494 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 489028425 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 253959415 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 249536911 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 250480927 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 252977424 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 251220434 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 249579925 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 257995414 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 252050416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2017800866 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 42779912 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 43250421 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 44195907 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 44710425 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 41223921 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 40317415 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 42323414 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 44497906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 343299321 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 296739327 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 292787332 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 294676834 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 297687849 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 292444355 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 289897340 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 300318828 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 296548322 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2361100187 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 296739327 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 292787332 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 294676834 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 297687849 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 292444355 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 289897340 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 300318828 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 296548322 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2361100187 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77190 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77190 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2307 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2340 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2363 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18606 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6392 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6378 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6321 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6438 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50930 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11413 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11660 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11485 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11654 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11476 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11568 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11412 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11636 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92304 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17802 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17956 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17877 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17854 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17889 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17850 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18011 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143234 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17802 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17956 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17877 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17854 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17889 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17850 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18011 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143234 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.895102 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.878177 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.874567 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.872386 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.877778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.879116 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.891961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.878544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880952 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.722840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.716521 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.727961 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.719034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.721563 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.733147 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.721882 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723503 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.060282 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.060377 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.061820 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062811 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.058470 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.056276 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.059324 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.061447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.060106 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.298843 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292660 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.295911 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.297194 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294444 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291352 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.302353 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.295208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.295991 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.298843 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292660 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.295911 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.297194 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294444 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291352 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.302353 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.295208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.295991 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29710.886683 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30527.442615 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29045.246785 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 31304.548434 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28750.481500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28813.697388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 30681.205532 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29830.199422 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29835.179367 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54827.162133 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54831.226324 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54690.158734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54804.467938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54779.859137 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54720.439597 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54660.045339 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54769.755758 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54760.119030 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 62180.104651 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61435.257102 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62247.756338 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61079.815574 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61436.543964 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61931.513057 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62516.121123 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62234.833566 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 61878.031903 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 18273 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2105340 # Number of tag accesses +system.l2c.tags.data_accesses 2105340 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits +system.l2c.Writeback_hits::total 77391 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits +system.l2c.demand_hits::total 101445 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12719 # number of overall hits +system.l2c.overall_hits::cpu1 12685 # number of overall hits +system.l2c.overall_hits::cpu2 12670 # number of overall hits +system.l2c.overall_hits::cpu3 12575 # number of overall hits +system.l2c.overall_hits::cpu4 12772 # number of overall hits +system.l2c.overall_hits::cpu5 12663 # number of overall hits +system.l2c.overall_hits::cpu6 12614 # number of overall hits +system.l2c.overall_hits::cpu7 12747 # number of overall hits +system.l2c.overall_hits::total 101445 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses +system.l2c.demand_misses::total 43103 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5430 # number of overall misses +system.l2c.overall_misses::cpu1 5384 # number of overall misses +system.l2c.overall_misses::cpu2 5365 # number of overall misses +system.l2c.overall_misses::cpu3 5464 # number of overall misses +system.l2c.overall_misses::cpu4 5284 # number of overall misses +system.l2c.overall_misses::cpu5 5329 # number of overall misses +system.l2c.overall_misses::cpu6 5404 # number of overall misses +system.l2c.overall_misses::cpu7 5443 # number of overall misses +system.l2c.overall_misses::total 43103 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 502016733 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 260655915 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 258218912 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 254645420 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 260879417 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 253975429 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 255536909 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 257461916 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 261401431 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2062775349 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 45984404 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 45132427 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 48152413 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6431 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6428 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6491 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51214 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11734 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11676 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11705 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11608 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11719 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11603 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11590 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 93334 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18149 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18069 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18056 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17992 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18190 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144548 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18149 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18056 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18190 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144548 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.883059 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.895129 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.889223 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882581 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.894333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.884599 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.886295 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.880591 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.886969 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.730164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.726732 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.724645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.732234 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.721793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.720457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.721998 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725312 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.725427 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.063576 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.063207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.066467 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.065041 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.060585 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.062570 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065833 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.297969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.297477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.302899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.292645 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.296187 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.299922 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.299230 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298192 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30032.130916 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29753.669118 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 31060.351038 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29925.190546 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 31209.143402 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 31055.167729 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30747.311220 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30705.074748 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30566.045604 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55648.145816 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55578.758502 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55514.589056 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55400.173498 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55525.891780 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55515.296328 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55475.525964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55522.818819 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55522.592297 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61641.292225 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61155.050136 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 61892.561697 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 62234.327152 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61550.595775 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62517.095041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 61741.699869 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62302.601361 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 61879.654512 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17704 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3257 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.610378 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6215 # number of writebacks -system.l2c.writebacks::total 6215 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6492 # number of writebacks +system.l2c.writebacks::total 6492 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 55 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 87 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1195 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1195 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2064 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2004 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2022 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2053 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2028 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2097 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2076 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16388 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4548 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4577 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4579 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4556 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4715 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36816 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 683 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 697 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 705 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 723 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 661 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 644 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 672 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 708 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5493 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5245 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5282 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5240 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5387 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5307 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42309 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5310 # 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number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 93067979 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92238981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 94104480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 91562476 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91964478 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 93840981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 737657156 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 213700915 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 211685412 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 208764420 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 213671917 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 208164429 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 209421909 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 210919416 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 214243431 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1690571849 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38320904 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37446428 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 40065914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 39278917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 36377424 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38015411 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39226917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 38343914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 307075829 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252021819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 249131840 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 248830334 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 252950834 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 244541853 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 247437320 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 250146333 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252587345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1997647678 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252021819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 249131840 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 248830334 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 252950834 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 244541853 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 247437320 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 250146333 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252587345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1997647678 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 434119876 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432203209 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 433941865 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 434763383 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 440636377 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 440018712 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 437840875 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 433521379 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3487045676 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 249140431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 246794950 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 253993435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 250261774 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 246746570 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 252474432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253706432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 248671425 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2001789449 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 683260307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 678998159 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 687935300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 685025157 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687382947 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 692493144 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 691547307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 682192804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5488835125 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.894668 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.878177 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.874567 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.872386 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877350 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878683 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.891961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.880791 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.724213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.722363 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.727803 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717937 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720772 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.732370 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721412 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722875 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059844 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.059777 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.061384 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062039 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057598 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.055671 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058885 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060846 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.295384 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.295384 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78781 # Transaction distribution -system.membus.trans_dist::ReadResp 84254 # Transaction distribution -system.membus.trans_dist::WriteReq 43831 # Transaction distribution -system.membus.trans_dist::WriteResp 43828 # Transaction distribution -system.membus.trans_dist::Writeback 6215 # Transaction distribution -system.membus.trans_dist::CleanEvict 1216 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61094 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50117 # Transaction distribution -system.membus.trans_dist::ReadExReq 49522 # Transaction distribution -system.membus.trans_dist::ReadExResp 3101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5483 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57394 # Total snoops (count) -system.membus.snoop_fanout::samples 254906 # Request fanout histogram +system.membus.trans_dist::ReadReq 78406 # Transaction distribution +system.membus.trans_dist::ReadResp 84270 # Transaction distribution +system.membus.trans_dist::WriteReq 43542 # Transaction distribution +system.membus.trans_dist::WriteResp 43539 # Transaction distribution +system.membus.trans_dist::Writeback 6492 # Transaction distribution +system.membus.trans_dist::CleanEvict 1226 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution +system.membus.trans_dist::ReadExReq 49587 # Transaction distribution +system.membus.trans_dist::ReadExResp 3167 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57207 # Total snoops (count) +system.membus.snoop_fanout::samples 255615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254906 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254906 # Request fanout histogram -system.membus.reqLayer0.occupancy 291050214 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 309370624 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 59.9 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 78782 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371328 # Transaction distribution +system.membus.snoop_fanout::total 255615 # Request fanout histogram +system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 60.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43832 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43827 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83405 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20435 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29579 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29579 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161223 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161218 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292561 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122267 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122810 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 980614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769994 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778957 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1770860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783783 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1787183 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1781792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778193 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14229418 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335158 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 800908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7.017024 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.129362 # Request fanout histogram +system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335027 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 787273 98.30% 98.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 13635 1.70% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 800908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495395322 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101110391 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101309873 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101121441 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101199500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101216377 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101535375 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101020631 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101318353 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 8965da370..e56af27bf 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133625 # Nu sim_ticks 133625300500 # Number of ticks simulated final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1195401 # Simulator instruction rate (inst/s) -host_op_rate 1195401 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1808178963 # Simulator tick rate (ticks/s) -host_mem_usage 302688 # Number of bytes of host memory used -host_seconds 73.90 # Real time elapsed on the host +host_inst_rate 1279205 # Simulator instruction rate (inst/s) +host_op_rate 1279205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1934942472 # Simulator tick rate (ticks/s) +host_mem_usage 304832 # Number of bytes of host memory used +host_seconds 69.06 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -482,6 +482,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3862 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3862 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution @@ -497,15 +503,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 131016 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.190864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.392983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005626 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.074797 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 555419 80.91% 80.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 131016 19.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 682573 99.44% 99.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3862 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 22fc38403..11714b3d8 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127292683500 # Number of ticks simulated -final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127296 # Number of seconds simulated +sim_ticks 127296402500 # Number of ticks simulated +final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 884807 # Simulator instruction rate (inst/s) -host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1600449674 # Simulator tick rate (ticks/s) -host_mem_usage 320712 # Number of bytes of host memory used -host_seconds 79.54 # Real time elapsed on the host +host_inst_rate 692014 # Simulator instruction rate (inst/s) +host_op_rate 883507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1251758978 # Simulator tick rate (ticks/s) +host_mem_usage 324360 # Number of bytes of host memory used +host_seconds 101.69 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254585367 # number of cpu cycles simulated +system.cpu.numCycles 254592805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,18 +215,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 137266 # n system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses system.cpu.dcache.overall_misses::total 177392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,42 +418,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94651 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id @@ -487,16 +487,16 @@ system.cpu.l2cache.overall_misses::cpu.data 123820 # system.cpu.l2cache.overall_misses::total 127770 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) @@ -525,16 +525,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,16 +561,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses @@ -587,17 +587,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution @@ -613,14 +619,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 94651 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index e9eb9ae35..9438e6b22 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.202233 # Number of seconds simulated -sim_ticks 202232894500 # Number of ticks simulated -final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 202232960500 # Number of ticks simulated +final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1204132 # Simulator instruction rate (inst/s) -host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1811881435 # Simulator tick rate (ticks/s) -host_mem_usage 302340 # Number of bytes of host memory used -host_seconds 111.61 # Real time elapsed on the host +host_inst_rate 1135828 # Simulator instruction rate (inst/s) +host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1709104516 # Simulator tick rate (ticks/s) +host_mem_usage 304720 # Number of bytes of host memory used +host_seconds 118.33 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,20 +25,20 @@ system.physmem.num_reads::cpu.data 122297 # Nu system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404465789 # number of cpu cycles simulated +system.cpu.numCycles 404465921 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -97,12 +97,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810202 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792048 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.109705 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.039667 # Average percentage of cache occupancy @@ -471,6 +471,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution @@ -486,15 +492,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 98298 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 925ba174e..6c0305fad 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316500 # Number of ticks simulated final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1465795 # Simulator instruction rate (inst/s) -host_op_rate 1465795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1893656296 # Simulator tick rate (ticks/s) -host_mem_usage 298240 # Number of bytes of host memory used -host_seconds 62.70 # Real time elapsed on the host +host_inst_rate 1432938 # Simulator instruction rate (inst/s) +host_op_rate 1432938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1851208744 # Simulator tick rate (ticks/s) +host_mem_usage 301400 # Number of bytes of host memory used +host_seconds 64.14 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -472,6 +472,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution @@ -487,15 +493,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index dfc2f4ccb..879b8d2d0 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173358500 # Number of ticks simulated -final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230174 # Number of seconds simulated +sim_ticks 230173520500 # Number of ticks simulated +final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1194511 # Simulator instruction rate (inst/s) -host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1599980237 # Simulator tick rate (ticks/s) -host_mem_usage 316228 # Number of bytes of host memory used -host_seconds 143.86 # Real time elapsed on the host +host_inst_rate 1035845 # Simulator instruction rate (inst/s) +host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1387457275 # Simulator tick rate (ticks/s) +host_mem_usage 319880 # Number of bytes of host memory used +host_seconds 165.90 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346717 # number of cpu cycles simulated +system.cpu.numCycles 460347041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842484 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300312 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -582,6 +582,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution @@ -597,14 +603,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 221e57a79..b410464ce 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563082500 # Number of ticks simulated -final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270563083500 # Number of ticks simulated +final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1293394 # Simulator instruction rate (inst/s) -host_op_rate 1293395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809017316 # Simulator tick rate (ticks/s) -host_mem_usage 297764 # Number of bytes of host memory used -host_seconds 149.56 # Real time elapsed on the host +host_inst_rate 1207450 # Simulator instruction rate (inst/s) +host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1688810940 # Simulator tick rate (ticks/s) +host_mem_usage 300136 # Number of bytes of host memory used +host_seconds 160.21 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 372793 # To system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126165 # number of cpu cycles simulated +system.cpu.numCycles 541126167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id @@ -219,12 +219,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -248,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -266,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -286,33 +286,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 298530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 298530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298530500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 298530500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340822 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy @@ -454,6 +454,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution @@ -469,14 +475,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 24228 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 395ca7a25..00e1fc087 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953957500 # Number of ticks simulated -final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953958500 # Number of ticks simulated +final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 750520 # Simulator instruction rate (inst/s) -host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1426094126 # Simulator tick rate (ticks/s) -host_mem_usage 340216 # Number of bytes of host memory used -host_seconds 175.97 # Real time elapsed on the host +host_inst_rate 759533 # Simulator instruction rate (inst/s) +host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1443220819 # Simulator tick rate (ticks/s) +host_mem_usage 343748 # Number of bytes of host memory used +host_seconds 173.88 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -32,7 +32,7 @@ system.physmem.bw_total::total 1207552 # To system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907915 # number of cpu cycles simulated +system.cpu.numCycles 501907917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -93,12 +93,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id @@ -202,12 +202,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -231,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -249,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,33 +269,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution @@ -458,14 +464,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) |